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Verification Techniques for System-Level Design
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This book will explain how to verify SoC (Systems on Chip) logic designs using “formal and “semiformal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in “functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.
For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
• First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs.
• Formal verification of high-level designs (RTL or higher).
• Verification techniques are discussed with associated system-level design methodology.
For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
• First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs.
• Formal verification of high-level designs (RTL or higher).
• Verification techniques are discussed with associated system-level design methodology.
Related to Verification Techniques for System-Level Design
Titles in the series (21)
Processor Description Languages Embedded DSP Processor Design: Application Specific Instruction Set Processors Rating: 0 out of 5 stars0 ratingsASIC and FPGA Verification: A Guide to Component Modeling Rating: 5 out of 5 stars5/5Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation Rating: 0 out of 5 stars0 ratingsReadings in Hardware/Software Co-Design Rating: 3 out of 5 stars3/5Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores Rating: 5 out of 5 stars5/5The Designer's Guide to VHDL Rating: 4 out of 5 stars4/5The System Designer's Guide to VHDL-AMS: Analog, Mixed-Signal, and Mixed-Technology Modeling Rating: 5 out of 5 stars5/5Modeling Embedded Systems and SoC's: Concurrency and Time in Models of Computation Rating: 0 out of 5 stars0 ratingsMultiprocessor Systems-on-Chips Rating: 0 out of 5 stars0 ratingsSystem Level Design with Rosetta Rating: 0 out of 5 stars0 ratingsESL Design and Verification: A Prescription for Electronic System Level Methodology Rating: 0 out of 5 stars0 ratingsSystem-on-Chip Test Architectures: Nanometer Design for Testability Rating: 0 out of 5 stars0 ratingsAspect-Oriented Programming with the e Verification Language: A Pragmatic Guide for Testbench Developers Rating: 0 out of 5 stars0 ratingsElectronic Design Automation: Synthesis, Verification, and Test Rating: 0 out of 5 stars0 ratingsVerification Techniques for System-Level Design Rating: 0 out of 5 stars0 ratingsVHDL-2008: Just the New Stuff Rating: 5 out of 5 stars5/5On-Chip Communication Architectures: System on Chip Interconnect Rating: 0 out of 5 stars0 ratingsNetworks on Chips: Technology and Tools Rating: 5 out of 5 stars5/5Network Processors: Architecture, Programming, and Implementation Rating: 0 out of 5 stars0 ratingsLow-Power Design of Nanometer FPGAs: Architecture and EDA Rating: 0 out of 5 stars0 ratings
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Verification Techniques for System-Level Design - Masahiro Fujita
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