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    Reliability Prediction from Burn-In Data Fit to Reliability Models
    Reliability Prediction from Burn-In Data Fit to Reliability Models
    Reliability Prediction from Burn-In Data Fit to Reliability Models
    Ebook168 pages1 hour

    Reliability Prediction from Burn-In Data Fit to Reliability Models

    By Joseph Bernstein

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    About this ebook

    This work will educate chip and system designers on a method for accurately predicting circuit and system reliability in order to estimate failures that will occur in the field as a function of operating conditions at the chip level. This book will combine the knowledge taught in many reliability publications and illustrate how to use the knowledge presented by the semiconductor manufacturing companies in combination with the HTOL end-of-life testing that is currently performed by the chip suppliers as part of their standard qualification procedure and make accurate reliability predictions. This book will allow chip designers to predict FIT and DPPM values as a function of operating conditions and chip temperature so that users ultimately will have control of reliability in their design so the reliability and performance will be considered concurrently with their design.
    • The ability to include reliability calculations and test results in their product design
    • The ability to use reliability data provided to them by their suppliers to make meaningful reliability predictions
    • Have accurate failure rate calculations for calculating warrantee period replacement costs
    LanguageEnglish
    PublisherAcademic Press
    Release dateMar 6, 2014
    ISBN9780128008195
    Reliability Prediction from Burn-In Data Fit to Reliability Models
    Author

    Joseph Bernstein

    Joseph B. Bernstein is Professor of Electrical Engineering at Ariel University, Ariel, Israel. He received his PhD from MIT, Cambridge, MA, USA, and has previously worked as a Professor at Bar Ilan University, Israel, and at the University of Maryland and the MIT Lincoln Laboratory. He has co-authored two books.

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      Book preview

      Reliability Prediction from Burn-In Data Fit to Reliability Models - Joseph Bernstein

      www.bqr.com.

      Chapter 1

      Shortcut to Accurate Reliability Prediction

      This chapter outlines the method of combining physics of failure models, either from the foundry or from the publications, as a theoretical input to a matrix, which is then solved against accelerated test data where the relative significance of each mechanism is determined by solving the matrix.

      Keywords

      M-HTOL; Matrix; FIT; Accelerated Test

      The traditional high-temperature operating life (HTOL) test is based on the outdated JEDEC standard that has not been supported or updated for many years. The major drawback of this method is that it is not based on a model that predicts failures in the field. Nonetheless, the electronics industry continues to provide data from tests of fewer than 100 parts, subjected to their maximum allowed voltages and temperatures for as many as 1000 h. The result based on zero, or a maximum of 1, failure out of the number of parts tested does not actually predict. This null result is then fit into an average acceleration factor (AF), which is the product of a thermal factor and a voltage factor. The result is a reported failure rate as described by the standard failure in time (FIT, also called Failure unIT) model, which is the number of expected failures per billion part hours of operation. FIT is still an important metric for failure rate in today’s technology; however, it does not account for the fact that multiple failure mechanisms simply cannot be averaged for either thermal or voltage AFs.

      One of the major limitations of advanced electronic systems qualification, including advanced microchips and components, is providing reliability specifications that match the variety of user applications. The standard HTOL qualification that is based on a single high-voltage and high-temperature burn-in does not reflect actual failure mechanisms that would lead to a failure in the field. Rather, the manufacturer is expected to meet the system’s reliability criteria without any real knowledge of the possible failure causes or the relative importance of any individual mechanism. More than this, as a consequence of the nonlinear nature of individual mechanisms, it is impossible for the dominant mechanism at HTOL test to reflect the expected dominant mechanism at operating conditions, essentially sweeping the potential cause of failure under the rug while generating an overly optimistic picture for the actual reliability.

      Two problems exist with the current HTOL approach, as recognized by JEDEC in publication JEP122G: (1) multiple failure mechanisms actually compete for dominance in our modern electronic devices and (2) each mechanism has a vastly different voltage and temperature AFs depending on the device operation. This more recent JEDEC publication recommends explicitly that multiple mechanisms should be addressed in a sum-of-failure-rates approach. We agree that a single point HTOL test with zero failures can, by no means, account for a multiplicity of competing mechanisms.

      In order to address this fundamental limitation, we developed a special multiple-mechanism qualification approach that allows companies to tailor specifications to a variety of customers’ needs. This approach will work with nearly any circuit to design a custom multiple HTOL (M-HTOL) test at multiple conditions and match the results with the foundrys’ reliability models to make accurate FIT calculations based on specific customers’ environments including voltage, temperature, and

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