Systems on Silicon Series

Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap between the separate worlds of hardware and software design— the key feature of reconfigurable computing is its groundbreaking ability to perform computations in hardware to increase performance while retaining the flexibility of a software solution. Reconfigurable computers serve as affordable, fast, and accurate tools for developing designs ranging from single chip architectures to multi-chip and embedded systems. Scott Hauck and Andre DeHon have assembled a group of the key experts in the fields of both hardware and software computing to provide an introduction to the entire range of issues relating to reconfigurable computing. FPGAs (field programmable gate arrays) act as the “computing vehicles to implement this powerful technology. Readers will be guided into adopting a completely new way of handling existing design concerns and be able to make use of the vast opportunities possible with reconfigurable logic in this rapidly evolving field. Designed for both hardware and software programmers Views of reconfigurable programming beyond standard programming languages Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

Efficient design of embedded processors plays a critical role in embedded systems design. Processor description languages and their associated specification, exploration and rapid prototyping methodologies are used to find the best possible design for a given set of applications under various design constraints, such as area, power and performance. This book is the first, comprehensive survey of modern architecture description languages and will be an invaluable reference for embedded system architects, designers, developers, and validation engineers. Readers will see that the use of particular architecture description languages will lead to productivity gains in designing particular (application-specific) types of embedded processors. * Comprehensive coverage of all modern architecture description languages... use the right ADL to design your processor to fit your application; * Most up-to-date information available about each architecture description language from the developers...save time chasing down reliable documentation; * Describes how each architecture desccription language enables key design automation tasks, such as simulation, synthesis and testing...fit the ADL to your design cycle;

This book provides design methods for Digital Signal Processors and Application Specific Instruction set Processors, based on the author's extensive, industrial design experience. Top-down and bottom-up design methodologies are presented, providing valuable guidance for both students and practicing design engineers. Coverage includes design of internal-external data types, application specific instruction sets, micro architectures, including designs for datapath and control path, as well as memory sub systems. Integration and verification of a DSP-ASIP processor are discussed and reinforced with extensive examples. Instruction set design for application specific processors based on fast application profiling Micro architecture design methodology Micro architecture design details based on real examples Extendable architecture design protocols Design for efficient memory sub systems (minimizing on chip memory and cost) Real example designs based on extensive, industrial experiences

The demand is exploding for complete, integrated systems that sense, process, manipulate, and control complex entities such as sound, images, text, motion, and environmental conditions. These systems, from hand-held devices to automotive sub-systems to aerospace vehicles, employ electronics to manage and adapt to a world that is, predominantly, neither digital nor electronic. To respond to this design challenge, the industry has developed and standardized VHDL-AMS, a unified design language for modeling digital, analog, mixed-signal, and mixed-technology systems. VHDL-AMS extends VHDL to bring the successful HDL modeling methodology of digital electronic systems design to these new design disciplines. Gregory Peterson and Darrell Teegarden join best-selling author Peter Ashenden in teaching designers how to use VHDL-AMS to model these complex systems. This comprehensive tutorial and reference provides detailed descriptions of both the syntax and semantics of the language and of successful modeling techniques. It assumes no previous knowledge of VHDL, but instead teaches VHDL and VHDL-AMS in an integrated fashion, just as it would be used by designers of these complex, integrated systems. Explores the design of an electric-powered, unmanned aerial vehicle system (UAV) in five separate case studies to illustrate mixed-signal, mixed-technology, power systems, communication systems, and full system modeling.

Over the last decade, advances in the semiconductor fabrication process have led to the realization of true system-on-a-chip devices. But the theories, methods and tools for designing, integrating and verifying these complex systems have not kept pace with our ability to build them. System level design is a critical component in the search for methods to develop designs more productively. However, there are a number of challenges that must be overcome in order to implement system level modeling. This book directly addresses that need by developing organizing principles for understanding, assessing, and comparing the different models of computation necessary for system level modeling. Dr. Axel Jantsch identifies the representation of time as the essential feature for distinguishing these models. After developing this conceptual framework, he presents a single formalism for representing very different models, allowing them to be easily compared. As a result, designers, students, and researchers are able to identify the role and the features of the "right" model of computation for the task at hand. *Offers a unique and significant contribution to the emerging field of models of computation *Presents a systematic way of understanding and applying different Models of Computation to embedded systems and SoC design *Offers insights and illustrative examples for practioners, researchers and students of complex electronic systems design.

Microprocessor cores used for SOC design are the direct descendents of Intel’s original 4004 microprocessor. Just as packaged microprocessor ICs vary widely in their attributes, so do microprocessors packaged as IP cores. However, SOC designers still compare and select processor cores the way they previously compared and selected packaged microprocessor ICs. The big problem with this selection method is that it assumes that the laws of the microprocessor universe have remained unchanged for decades. This assumption is no longer valid. Processor cores for SOC designs can be far more plastic than microprocessor ICs for board-level system designs. Shaping these cores for specific applications produces much better processor efficiency and much lower system clock rates. Together, Tensilica’s Xtensa and Diamond processor cores constitute a family of software-compatible microprocessors covering an extremely wide performance range from simple control processors, to DSPs, to 3-way superscalar processors. Yet all of these processors use the same software-development tools so that programmers familiar with one processor in the family can easily switch to another. This book emphasizes a processor-centric MPSOC (multiple-processor SOC) design style shaped by the realities of the 21st-century and nanometer silicon. It advocates the assignment of tasks to firmware-controlled processors whenever possible to maximize SOC flexibility, cut power dissipation, reduce the size and number of hand-built logic blocks, shrink the associated verification effort, and minimize the overall design risk. · An essential, no-nonsense guide to the design of 21st-century mega-gate SOCs using nanometer silicon. · Discusses today's key issues affecting SOC design, based on author's decades of personal experience in developing large digital systems as a design engineer while working at Hewlett-Packard's Desktop Computer Division and at EDA workstation pioneer Cadnetix, and covering such topics as an award-winning technology journalist and editor-in-chief for EDN magazine and the Microprocessor Report. · Explores conventionally accepted boundaries and perceived limits of processor-based system design and then explodes these artificial constraints through a fresh outlook on and discussion of the special abilities of processor cores designed specifically for SOC design. · Thorough exploration of the evolution of processors and processor cores used for ASIC and SOC design with a look at where the industry has come from, and where it's going. · Easy-to-understand explanations of the capabilities of configurable and extensible processor cores through a detailed examination of Tensilica's configurable, extensible Xtensa processor core and six pre-configured Diamond cores. · The most comprehensive assessment available of the practical aspects of configuring and using multiple processor cores to achieve very difficult and ambitious SOC price, performance, and power design goals.

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.

Embedded system designers are constantly looking for new tools and techniques to help satisfy the exploding demand for consumer information appliances and specialized industrial products. One critical barrier to the timely release of embedded system products is integrating the design of the hardware and software systems. Hardware/software co-design is a set of methodologies and techniques specifically created to support the concurrent design of both systems, effectively reducing multiple iterations and major redesigns. In addition to its critical role in the development of embedded systems, many experts believe that co-design will be a key design methodology for Systems-on-a-Chip. Readings in Hardware/Software Co-Design presents the papers that have shaped the hardware/software co-design field since its inception in the early 90s. Field experts -- Giovanni De Micheli, Rolf Ernst, and Wayne Wolf -- introduce sections of the book, and provide context for the paper that follow. This collection provides professionals, researchers and graduate students with a single reference source for this critical aspect of computing design. * Over 50 peer-reviewed papers written from leading researchers and designers in the field * Selected, edited, and introduced by three of the fields' most eminent researchers and educators * Accompanied by an annually updated companion Web site with links and references to recently published papers, providing a forum for the editors to comment on how recent work continues or breaks with previous work in the field

Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs. VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools. This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals. * Details how the new standard allows for increased portability across tools. * Covers related standards, including the Numeric Synthesis Package and the Synthesis Operability Package, demonstrating how they can be used for digital systems design. * Presents four extensive case studies to demonstrate and combine features of the language taught across multiple chapters. * Requires only a minimal background in programming, making it an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.

The steady and unabated increase in the capacity of silicon has brought the semiconductor industry to a watershed challenge. Now a single chip can integrate a radio transceiver, a network interface, multimedia functions, all the "glue" needed to hold it together as well as a design that allows the hardware and software to be reconfigured for future applications. Such complex heterogeneous systems demand a different design methodology. A consortium of industrial and government labs have created a new language and a new design methodology to support this effort. Rosetta permits designers to specify requirements and constraints independent of their low level implementation and to integrate the designs of domains as distinct as digital and analog electronics, and the mechanical, optical, fluidic and thermal subsystems with which they interact. In this book, Perry Alexander, one of the developers of Rosetta, provides a tutorial introduction to the language and the system-level design methodology it was designed to support. * The first commercially published book on this system-level design language * Teaches you all you need to know on how to specify, define, and generate models in Rosetta * A presentation of complete case studies analyzing design trade-offs for power consumption, security requirements in a networking environment, and constraints for hardware/software co-design

Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications

Visit the authors' companion site! http://www.electronicsystemlevel.com/ - Includes interactive forum with the authors! Electronic System Level (ESL) design has mainstreamed – it is now an established approach at most of the world’s leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with ‘no links to implementation’, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems. This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption. ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today. Table of Contents CHAPTER 1: WHAT IS ESL? CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT CHAPTER 4: WHAT ARE THE ENABLERS OF ESL? CHAPTER 5: ESL FLOW CHAPTER 6: SPECIFICATIONS AND MODELING CHAPTER 7: PRE-PARTITIONING ANALYSIS CHAPTER 8: PARTITIONING CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG CHAPTER 10: POST-PARTITIONING VERIFICATION CHAPTER 11: HARDWARE IMPLEMENTATION CHAPTER 12: SOFTWARE IMPLEMENTATION CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS APPENDIX: LIST OF ACRONYMS * Provides broad, comprehensive coverage not available in any other such book * Massive global appeal with an internationally recognised author team * Crammed full of state of the art content from notable industry experts

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. On-Chip Communication Architecures is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures. A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends Detailed analysis of all popular standards for on-chip communication architectures Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts Future trends that with have a significant impact on research and design of communication architectures over the next several years

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. Practical problems at the end of each chapter for students.

What’s this AOP thing anyway, really—when you get right down to it—and can someone please explain what an aspect actually is? Aspect-Oriented Programming with the e Verification Language takes a pragmatic, example based, and fun approach to unraveling the mysteries of AOP. In this book, you’ll learn how to: • Use AOP to organize your code in a way that makes it easy to deal with the things you really care about in your verification environments. Forget about organizing by classes, and start organizing by functionality, layers, components, protocols, functional coverage, checking, or anything that you decide is important to you • Easily create flexible code that eases your development burden, and gives your users the power to quickly do what they need to do with your code • Truly create a plug-and-play environment that allows you to add and remove functionality without modifying your code. Examples include how to use AOP to create pluggable debug modules, and a pluggable module that lets you check that your testbench is still working before you begin a regression • Utilize AOP to sidestep those productivity roadblocks that seem to plague all projects at the most inconvenient of times • Discover why “return is evil, and some other “gotchas with the AOP features of e All of the methodologies, tips, and techniques described in this book have been developed and tested on real projects, with real people, real schedules and all of the associated problems that come with these. Only the ones that worked, and worked well, have made it in, so by following the advice given in this book, you’ll gain access to the true power of AOP while neatly avoiding the effort of working it all out yourself. • Use AOP to organize your code in a way that makes it easy to deal with the things you really care about in your verification environments. Forget about organizing by classes, and start organizing by functionality, layers, components, protocols, functional coverage, checking, or anything that you decide is important to you • Easily create flexible code that eases your development burden, and gives your users the power to quickly do what they need to do with your code • Truly create a plug-and-play environment that allows you to add and remove functionality without modifying your code. Examples include how to use AOP to create pluggable debug modules, and a pluggable module that lets you check that your testbench is still working before you begin a regression • Utilize AOP to sidestep those productivity roadblocks that seem to plague all projects at the most inconvenient of times • Discover why “return is evil, and some other “gotchas with the AOP features of e

The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution. This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions. * Leading-edge research from world-renowned experts in academia and industry with state-of-the-art technology implementations/trends * An integrated presentation not currently available in any other book * A thorough introduction to current design methodologies and chips designed with NoCs

This book will explain how to verify SoC (Systems on Chip) logic designs using “formal and “semiformal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in “functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs. • First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs. • Formal verification of high-level designs (RTL or higher). • Verification techniques are discussed with associated system-level design methodology.

VHDL-2008: Just the New Stuff, as its title says, introduces the new features added to the latest revision of the IEEE standard for the VHDL hardware description language. Written by the Chair and Technical Editor of the IEEE working group, the book is an authoritative guide to how the new features work and how to use them to improve design productivity. It will be invaluable for early adopters of the new language version, for tool implementers, and for those just curious about where VHDL is headed. * First in the market describing the new features of VHDL 2008; * Just the new features, so existing users and implementers can focus on what's new; * Helps readers to learn the new features soon, rather than waiting for new editions of complete VHDL reference books. * Authoritative, written by experts in the area; * Tutorial style, making it more accessible than the VHDL Standard Language Reference Manual.

Low-Power Design of Nanometer FPGAs Architecture and EDA is an invaluable reference for researchers and practicing engineers concerned with power-efficient, FPGA design. State-of-the-art power reduction techniques for FPGAs will be described and compared. These techniques can be applied at the circuit, architecture, and electronic design automation levels to describe both the dynamic and leakage power sources and enable strategies for codesign. Low-power techniques presented at key FPGA design levels for circuits, architectures, and electronic design automation, form critical, "bridge" guidelines for codesign Comprehensive review of leakage-tolerant techniques empowers designers to minimize power dissipation Provides valuable tools for estimating power efficiency/savings of current, low-power FPGA design techniques

Network processors are the basic building blocks of today's high-speed, high-demand, quality-oriented communication networks. Designing and implementing network processors requires a new programming paradigm and an in-depth understanding of network processing requirements. This book leads the reader through the requirements and the underlying theory of networks, network processing, and network processors. It covers implementation of network processors and intergrates EZchip Microcode Development Environment so that you can gain hands-on experience in writing high-speed networking applications. By the end of the book, the reader will be able to write and test applications on a simulated network processor. Comprehensive, theoretical, and pracitical coverage of networks and high-speed networking applications Descirbes contemporary core, metro, and access networks and their processing algorithms Covers network processor architectures and programming models, enabling readers to assess the optimal network processor typer and configuration for their application Free download from http://www.cse.bgu.ac.il/npbook includes microcode development tools that provide hands-on experience with programming a network processor

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book. Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes