01 Yoshitomi MOS-AK 08

Copyright 2008, Toshiba Corporation.
Compact Model Challenges of Compact Model Challenges of Compact Model Challenges of Compact Model Challenges of
65nm RF 65nm RF 65nm RF 65nm RF- -- -CMOS technology CMOS technology CMOS technology CMOS technology
TOSHIBACorp. Semiconductor Company
Sadayuki Yoshitomi (sadayuki.yoshitomi@toshiba.co.jp)
Tadamasa Katoh (tadamasa.katoh@toshiba.co.jp)
Toshifumi Nakanose (toshifumi.nakanose@toshiba.co.jp)
Fumie Fujii (fumie.fujii@toshiba.co.jp)
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 2
CMOS Technology Innovation
CMOS1
BSIM3
0.13um
90nm
0.18um
0.25um
0.35um
65nm
40nm
32nm
CMOS2
BSIM3 EKV
CMOS3
BSIM3 EKV*
CMOS4
BSIM4 EKV*
CMOS5
BSIM4 PSP
EKV*
CMOS6

CMOS7

1995
STI
Dual Gate / Ti Salicide
Logic Based eDRAM
Cu Interconnect
Low k
Stress control
Low-k II
Strained-Si, High-k
Low-k III
Metal Gate
High-k
Toshibas been a leader
for many process generations
Release RF-CMOS
Technology from 0.13um
CMOS3
06/Q2
CMOS4
07/Q2
CMOS5
08/Q2
EKV available for internal use
only
10
100
1000
10 100 1000
Toshiba
TSMC
NXP
ITRS
C
u
t
-
o
f
f

F
r
e
q
u
e
n
c
y

[
G
H
z
]
Lg [nm]
f
T
Trend and Benchmarking
TOSHIBA
CMOS5
(65nm)
Agenda
Challenges of RF scalable model creation of 65nm RF-CMOS
technology
Methodology of creation of RF-CMOS scalable model
Observation of RF-scaling law
Extensional validation issues.
RF Switch
High-linear circuits
Diode
CJDB
Diode
CJDS
R
RSUB2
Port
DRAIN
Num= 2
L
LD
R
RD
R
RSUB1
R
RSUB4
R
RSUB3
C
CFGS
C
CFGD
R
RS
L
LG
R
RG
L
LS
Port
SOURCE
Num= 3
Port
GATE
Num=1 MOSFET_NMOS
c3_fast _n
What is needed for RF-CMOS compact model ?
Scalable and compact
For portability, parasitic elements should be scalable function of
Lg (Gate Length)
Wf (Finger Length)
NF (Finger Numbers)
(SA,SB,SD)
Accurate for all design purpose
LNA (NQS effect, Thermal noise)
Linear: S-parameters > 100GHz
De-embedding: SOLT ? TRL ?
VCO and Mixer (Harmonic distortion, Flicker noise)
Flicker noise close to the carrier.
ACPR, EVM
Power amplifier
Self Heating
Load-pull
MOSFET : Extrinsic Parasitic elements
Yuhua Cheng et al.(2000b) MOSFET modeling for RF circuit design,
Proceeding of the 2000 Third IEEE International Caracas Conference on
Devices, Circuits and Systems, D23/1-D23/8
Gm*vgs+Gds*Vds
Simplified Equivalent Circuit when MOSFET=OFF
Port
SB
Num=2
R
RDB
R
RDSB
Port
G
Num=2
Port
D
Num=2
R
RD
Diode
CBD
R
RG
C
CGBpulsCGS
I_DC
Gm+Gds
C
CFGD1
Source and Back-gate grounded
VG=VD=VS=VB=0

Equivalent Circuit when MOSFET=SI & Linear
Port
SB
Num=2
R
RDB
R
RDSB
Port
G
Num=2
Port
D
Num=2
R
RD
Diode
CBD
R
RG
C
CGBpulsCGS
I_DC
Gm+Gds
C
CFGD1
Source and Back-gate grounded
VG=VDD, VD=low, VS=VB=0
R
gds
RDSB
RDB
Measure of components from y-parameters
( ) ( )
( ) ( )
CB CD CS G
GD BD m GD GD G BD G G DS
m GD m GD G G m
G GD G
G G
G G G C
C C j C C C C C C R G Y
C C j C C C R G Y
j C C R Y
j R C Y
+ + =
+ + + + +
+ +

+
2
22
2
21
2
12
2 2
11
GD
G
C
C
( )
( )
( )
( )
12
12 11
12 22
12
Re
Im
Im
Im
Z R
Y Y C C
Y Y C
Y C
DB
GS GB
DB
GD
+ +
+ =
=
Starting point the formula (12.7a~12.7d) : Christian C.Enz, Eric A. Vittoz ,
Charge-based MOS Transistor Modeling Wiley 2006.
( )
( )
( ) ( )
|
|
\
|
=
=
=
22
2
11
11
1
Re
Im
Re
Y
R
R R
Y
Y
R
DSB
S D
G
22
Z Re
SI and linear region OFF region
Q1
Does RG scaling follows classical ohmic-law ?
Nf Lg
Wf
k R
rg G
=
K : constant depending on the configuration of gate contact
NO : Gate resistance behaves complex behavior
0
1
2
3
4
5
0.01 0.1 1 10
Lg [um]
N
o
r
m
a
l
i
z
e
d

g
a
t
e

r
e
s
i
s
t
a
n
c
e
Scaling dependence of Rg on gate-length (Lg)
LV NMOSFET
Wf=1um, NF=40
Lg
-1
Lg
model
Meas.
0
1
2
3
4
5
0.01 0.1 1
Lg [um]
N
o
r
m
a
l
i
z
e
d

R
g
(
(
+
g
RGL
g
f
RGL
L
K
L
N
K
2 1
Scaling dependence of Rg on Wf/Nf
0
1
2
3
4
5
0 0 .05 0.1 0.1 5
W f/ Nf
N
o
r
m
a
l
i
z
e
d

R
G
LV NMOSFET
Lg=50nm
Wf*NF=40um
model
Meas.
NF*Wf
-1
NF*Wf
2um*20
0.5um*80
1.0um*40
(
(
+
f
RGL
f
W
K
W
3
Q2 Does capacitance scaling has unique behaviour ?
NO : It is typical behavior
( )
( )
( )
12 11
12 22
12
Im
Im
Im
Y Y C C
Y Y C
Y C
GS GB
DB
GD
+ +
+
0
1
2
3
4
5
0.01 0.1 1 10
Lg [um]
N
o
r
m
a
l
i
z
e
d

C
a
p
a
c
i
t
a
n
c
e
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
0.001 0.01 0.1 1
Wf/Nf
N
o
r
m
a
l
i
z
e
d

C
a
a
c
i
t
a
n
c
e
CGB+CGS
CGD
CDB
CGB+CGS
CGD
CDB
Shorter Wf
More # of NF
CGB
Observation of the RB scaling
0
2
4
6
8
10
12
0.01 0.1 1 10
Lg [um]
N
o
r
m
a
l
i
z
e
d

R
B
0
0.5
1
1.5
2
2.5
3
0 50 100 150 200
Wf*NF
N
o
r
m
a
l
i
z
e
d

R
B
NF
-1
*Wf
-1
NF Wf
Rsh
NF
Wf
Lg Rsh
+
1
2 1
RF-CMOS modeling summary
f f RCL
N W K
CGB G-B capacitance
RSUB1
RSUB2
RSUB3
RSUB4
Substrate resistance
CFGD
CFGS
G-D,G-S overlap
capacitance
RG
NQS
Gate resistance
Geometric
dependency
Item
name
Component name
(
(
+
(
(
+
f
RGL
f
g
RGL
g
f
RGL
W
K
W
L
K
L
N
K
3 2 1
K
CGB
,K
RGL1
, K
RGL2
, K
RGL3
,K
RCL
,K
Rsh1,
K
Rsh2
: Constants
Nf Lg K CGB
CGB
=
NF Wf
Rsh
NF
Wf
Lg Rsh
+
1
2 1
Verification of 65nm RF-CMOS via peak-fT
1.00E+09
1.00E+10
1.00E+11
1.00E+12
1.00E-08 1.00E-07 1.00E-06 1.00E-05
Lg [m]
P
e
a
k

f
T

[
H
z
]
NMOS
PMOS
model
Meas.
LV MOSFETs
Wf=1um Nf=40
Model Verification
Improve
NMOSFET Lg=0.3um Wf=20um NF=100
S D
G
DeepNwell
Pwell
LINE1
LINE2
LINE3
449.61 45.93 Pwell-RPOLY-PAD LINE3
192.48 44.39 GATE-RPOLY-PAD LINE2
355 25.04
DeepNwell-RPOLY-
PAD
LINE1
Lngth of M6S
[um]
Length of M1
[um]
PATH
Line width all 0.3um
MOSFET MOSFET MOSFET MOSFET- -- -Switch Switch Switch Switch
RF1
Gate(Vg)
RF2
BackGate(Vbg) D-Nwell(Vdn)
FET
R=10k(All)
PSUB
D-Nwell B-Gate
Source
Gate
Drain
Psub
Deep-Nwell
n
p
n+ n+
STI
P-N Diode
Define
5 Term MOS
BSIM4_NMOS
CORE
Port
G
Num=2
Port
DNW
Num=2
Port
PW
Num=4
Port
PSUB
Num=5
Diode
Dpsubwb
Diode
Dwpwb
C
CGB1
Port
S
Num=3
R
RS
Port
D
Num=1
R
RD
R
RG
R
RSUB2
R
RSUB1
R
RSUB3
R
RSUB4
Diode
Djds
L
LD
L
LS
L
LG
C
CFGS
C
CFGD
Diode
Djdb
Simulation does not match
NMOSFET Lg=0.3um Wf=20um NF=100
50MHz~20.05GHz (201 PTS
VG, V_DNW 0V,2.5V
VD=VS=0V
Blue:Meas
Red Model
Define
Hard Implemantation
Cov_hk
RGB
CGB
DIO_CJO
Rline1
Rline2
Rline3
Cov_CJW
Analyze
Cpad
Transmission Line
LindSelf inductaoce
Rind:Series Resistance
CoxCap between Metal and Si
RsLoss of Si substrate
CsLoss of Si substrate
2.48 2.03 1.07 2.03 1.97 2.93 Cs [fF]
609 436 1422 436 771.5 697 Rs [Ohm]
7.89 3.22 3.37 3.22 6.22 1.86 Cox [fF]
21.6 6.89 9.26 6.89 17.1 3.82 Rind [Ohm]
0.39 0.04 0.17 0.05 0.31 0.02 Lind [nH]
M6S M1 M6S M1 M6S M1
LINE3 LINE2 LINE1
Improve
Completed schematic
Improve
5term MOS
LINE1
transLine
LINE1
TransLine
LINE2
TransLine
LINE2
TransLine
LINE3
TransLine
LINE3
Transline
Comparison before and after
Improve
1E9 1E10 1E8 3E10
-30
-25
-20
-15
-10
-5
-35
0
freq, Hz
S
2
1

[
d
B
]
SWEEP.freq, Hz
Eqn Dev=100.9+130.8+207.1+132.0
Dev
570.800
1
E
9
1
E
1
0
1
E
8
3
E
1
0
5.0E3
1.0E4
0.0
1.5E4
SWEEP.freq, Hz
m
a
g
(
S
2
1
_
e
r
r
)
VDNW
0.000E0
2.500E0
Sum_S21_Err
Vgsh=0.000E0 Vgsh=2.500E0
1.009E2 1.308E2
2.071E2 1.320E2
1E9 1E10 1E8 3E10
-30
-25
-20
-15
-10
-5
-35
0
freq, Hz
S
2
1

[
d
B
]
SWEEP.freq, Hz
Eqn Dev1=5.862+5.202+1.234+0.726
Dev1
13.024
1
E
9
1
E
1
0
1
E
8
3
E
1
0
20
40
60
0
80
SWEEP.freq, Hz
m
a
g
(
S
2
1
_
e
r
r
)
VDNW
0.000E0
2.500E0
Sum_S21_Err
Vgsh=0.000E0 Vgsh=2.500E0
-1.234E0 -5.862E0
-7.260E-1 -5.202E0
Before
after
f req (50.00MHz to 20.05GHz)
(
S
(
2
,
1
)
)
SWEEP.freq (50.00MHz to 20.05GHz)
(
z
Y
6
8
_
I
_
f
e
t
0
1
_
m
.
.
s
p
a
r
_
v
g
0
.
I
C
C
A
P
_
S
W
E
P
T
_
D
A
T
A
.
X
F
O
R
M
.
s
d
(
2
,
1
)
)
(
z
y
6
8
_
I
_
f
e
t
0
1
_
m
.
.
s
p
a
r
_
v
g
2
p
5
.
I
C
C
A
P
_
S
W
E
P
T
_
D
A
T
A
.
X
F
O
R
M
.
s
d
(
2
,
1
)
)
freq (50.00MHz to 20.05GHz)
(
S
(
1
,
1
)
)
SWEEP. freq (50. 00MHz to 20.05GHz)
(
z
y
6
8
_
I
_
f
e
t
0
1
_
m
.
.
s
p
a
r
_
v
g
0
.
I
C
C
A
P
_
S
W
E
P
T
_
D
A
T
A
.
X
F
O
R
M
.
s
d
(
1
,
1
)
)
(
z
y
6
8
_
I
_
f
e
t
0
1
_
m
.
.
s
p
a
r
_
v
g
2
p
5
.
I
C
C
A
P
_
S
W
E
P
T
_
D
A
T
A
.
X
F
O
R
M
.
s
d
(
1
,
1
)
)
freq (50. 00MHz to 20.05GHz)
(
S
(
2
,
1
)
)
SWEEP. freq (50.00MHz to 20.05GHz)
(
z
Y
6
8
_
I
_
f
e
t
0
1
_
m
.
.
s
p
a
r
_
v
g
0
.
I
C
C
A
P
_
S
W
E
P
T
_
D
A
T
A
.
X
F
O
R
M
.
s
d
(
2
,
1
)
)
(
z
y
6
8
_
I
_
f
e
t
0
1
_
m
.
.
s
p
a
r
_
v
g
2
p
5
.
I
C
C
A
P
_
S
W
E
P
T
_
D
A
T
A
.
X
F
O
R
M
.
s
d
(
2
,
1
)
)
freq (50.00MHz to 20.05GHz)
(
S
(
1
,
1
)
)
SWEEP.freq (50.00MHz to 20.05GHz)
(
z
y
6
8
_
I
_
f
e
t
0
1
_
m
.
.
s
p
a
r
_
v
g
0
.
I
C
C
A
P
_
S
W
E
P
T
_
D
A
T
A
.
X
F
O
R
M
.
s
d
(
1
,
1
)
)
(
z
y
6
8
_
I
_
f
e
t
0
1
_
m
.
.
s
p
a
r
_
v
g
2
p
5
.
I
C
C
A
P
_
S
W
E
P
T
_
D
A
T
A
.
X
F
O
R
M
.
s
d
(
1
,
1
)
)
S-Parameter before and after
Improve
Before
After
S21
S11
S21
S11
Summary
65nm-RFCMOS compact models development
Scaling approach based on COLD-measurement and SI & Linear
measurement still works.
It is possible to get a simple guess by taking look at Y and Z parameters.
Substrate modeling is needed in case of RF switch which controls back-
gate bias.
All possible modeling efforts by the aid of EM simulation is sure needed.
Thank you !

01 Yoshitomi MOS-AK 08

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Copyright 2008, Toshiba Corporation.

Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 8

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