The VHDL code for 4 bit Johnson counter is

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity johnson_counter is port ( DAT_O : out unsigned(3 downto 0); RST_I : in std_logic; CLK_I : in std_logic ); end johnson_counter; architecture Behavioral of johnson_counter is signal temp : unsigned(3 downto 0):=(others => '0'); begin DAT_O <= temp; process(CLK_I) begin if( rising_edge(CLK_I) ) then if (RST_I = '1') then temp <= (others => '0'); else temp(1) <= temp(0); temp(2) <= temp(1); temp(3) <= temp(2); temp(0) <= not temp(3);

end if; end if; end process; end Behavioral;

The testbench code used for testing the design is

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY tb2 IS END tb2; ARCHITECTURE behavior OF tb2 IS --Inputs signal RST_I : std_logic := '0'; signal CLK_I : std_logic := '0'; --Outputs signal DAT_O : unsigned(3 downto 0); -- Clock period definitions constant CLK_I_period : time := 1 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity work.johnson_counter PORT MAP ( DAT_O => DAT_O, RST_I => RST_I, CLK_I => CLK_I ); -- Clock process definitions CLK_I_process :process begin CLK_I <= '0'; wait for CLK_I_period/2; CLK_I <= '1'; wait for CLK_I_period/2; end process; -- Stimulus process stim_proc: process begin RST_I <= '1';

wait for 2 ns; RST_I <= '0'; wait for 2 ns; RST_I <= '1'; wait for 1 ns; RST_I <= '0'; wait; end process; END;

Output