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  • Implement VHDL Decade Counter

    Încărcat de

    Rohit Panwar
    44 vizualizări4 pagini
    EXPERIMENT NO. 12 Aim To implement VHDL code for down counter Tool required Mentor Graphics FPGA advantage 8.1ps Model sim 6.3a Theory counter a Decade Counter is one that counts in decimal digits, rather than binary. A Decade Counter may have each digit binary encoded (that is, it may count in binary-coded decimal, as the7490 integrated circuit did) or other binary encodings.

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    Decade Counter

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    EXPERIMENT NO. 12 Aim To implement VHDL code for down counter Tool required Mentor Graphics FPGA advantage 8.1ps Model sim 6.3a Theory counter a Decade Counter is one that counts in decimal digits, rather than binary. A Decade Counter may have each digit binary encoded (that is, it may count in binary-coded decimal, as the7490 integrated circuit did) or other binary encodings.

    Drepturi de autor:

    Attribution Non-Commercial (BY-NC)
    Descărcați ca DOCX, PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    44 vizualizări4 pagini

    Implement VHDL Decade Counter

    Încărcat de

    Rohit Panwar
    EXPERIMENT NO. 12 Aim To implement VHDL code for down counter Tool required Mentor Graphics FPGA advantage 8.1ps Model sim 6.3a Theory counter a Decade Counter is one that counts in decimal digits, rather than binary. A Decade Counter may have each digit binary encoded (that is, it may count in binary-coded decimal, as the7490 integrated circuit did) or other binary encodings.

    Drepturi de autor:

    Attribution Non-Commercial (BY-NC)
    Descărcați ca DOCX, PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    din 4

    EXPERIMENT NO.

    12
    Aim
    To implement VHDL code for Decade Counter

    Tool required
    Mentor Graphics FPGA advantage 8.1ps Model sim 6.3a

    Theory

    Counter
    In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal.

    Decade Counter
    A decade counter is one that counts in decimal digits, rather than binary. A decade counter may have each digit binary encoded (that is, it may count in binary-coded decimal, as the7490 integrated circuit did) or other binary encodings (such as the bi-quinary encoding of the7490 integrated circuit).

    Fig (12.1)

    Truth Table
    TABLE (12.1)

    CLOCK 0 1 2 3 4 5 6 7 8 9 10

    E 0 0 0 0 0 0 1 1 1 1 0

    D 0 0 0 1 1 1 0 0 1 1 0

    C 0 0 1 0 0 1 0 0 0 1 0

    B 0 1 1 1 1 1 1 1 0 1 0

    A 0 1 1 0 1 0 0 1 0 1 0

    Timing Diagram

    VHDL code for down counter


    LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; ENTITY decade IS port(cr,pr,clk:in std_logic; q:inout std_logic_vector(0 to 4)); END ENTITY decade; ARCHITECTURE decade_beh OF decade IS signal temp:std_logic_vector(0 to 4); BEGIN process(cr,pr,clk) begin if(cr='0')then temp<="00000"; elsif(pr='0')then temp<="11111"; elsif(clk='1' and clk 'event)then if(temp="00000")then temp<="00011"; elsif(temp="00011")then temp<="00111"; elsif (temp="00111")then temp<="01010"; elsif(temp="01010")then temp<="01011"; elsif(temp="01011")then temp<="01110"; elsif(temp="01110")then

    temp<="10010"; elsif(temp="10010")then temp<="10011"; elsif(temp="10011")then temp<="11000"; elsif(temp="11000")then temp<="11111"; end if; end if; end process; END ARCHITECTURE decade_beh;

    Output

    Result window of decade counter

    Result - The VHDL code for Decade counter were implemented and simulated successfully.

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