MINGSTAR ELECTRONIC CORPORATION

Spec. No. 233-220-053 Version : 0 Total pages: 21 Date : 1998/07/20

TFT-LCD CONTROLLER LSI (UPS015) PRELIMINARY SPECIFICATION

MODEL NAME: UPS015

The content of this technical information is subject to change without notice. Please contact Mingstar or its agent for further information.

Mingstar copyright 1999 All rights reserved, copying forbidden.

SPEC NO.:233-220-053 PAGE :1/21

Contents: A. General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P2 B. Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P2 C. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P3 D. DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P5 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P5 2. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . P5 3. General DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P5 4. Current consumption for 5 volts operation . . . . . . . . . . . . . . . . . . . P5 E. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P7 1. Timing condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P7 ( i )220 x 280 resolution mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P7 a. Input signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . P7 b. Output signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . P7 ( ii )234 x 480 resolution mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P8 a. Input signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . P8 b. Output signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . P8 ( iii )220 x 528 resolution mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P9 a. Input signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . P9 b. Output signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . P9

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SPEC NO.:233-220-053 PAGE :2/21

( iv )234 x 960 resolution mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P10 a. Input signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . P10 b. Output signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . P11 ( v )234 x 1152 resolution mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P12 a. Input signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . P12 b. Output signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . P12 2. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P13 F. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P14 G. Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P15 Appendix Fig.1 Fig.2-(a) Fig.2-(b) Fig.3 Fig.4-(a) Fig.4-(b) Sampling clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . Horizontal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detail horizontal timing . . . . . . . . . . . . . . . . . . . . . . . . . Vertical shift clock timing . . . . . . . . . . . . . . . . . . . . . . . . Vertical timing (UDC="H") . . . . . . . . . . . . . . . . . . . . . . . Vertical timing (UDC="L") . . . . . . . . . . . . . . . . . . . . . . . P16 P17 P18 P19 P20 P21

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SPEC NO.:233-220-053 PAGE :3/21

A.General description:
This timing controller is a synchronizing signal controlling CMOS array LSI for Mingstar LCD module. It provides all the necessary control timing signals to the LCD source and gate drivers. With external VCO as the master clock, the controller has built-in phase locked loop system which can synchronize the master clock with the horizontal and vertical Sync. signals from a classical TV system. The applicable Mingstar TFT-LCD modules are SM261D series, MTL020D01,MTL025D01, MTL040D01 , MTL068D01, MTL070W01.

B. Feature:
* Programmable resolution mode. * Low Power Consumption. * Single Supply : +5.0 Volts. * 48 pins TQFP. * Shift Clocks Signal for the Source Driver. (3 - v Clock) * Line Inversion Driving Scheme. * NTSC TV Standard System . * Master Clock Frequency : 26 MHz max. * Provides Timing Scan Signals for Left / Right and Up / Down Shift Control. * Display Timing Range = 49.6l s

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SPEC NO.:233-220-053 PAGE :4/21

C.Pin description:
Pin no 1 2 3 4 5 6 7 8 9 10 Symbol INV/O INV/I OEH OEV TEST TEST GND Q1HA A18 STV1 O I O Ground Sample & hold sequence control signal for source driver Resolution mode selecting pin I Gate driver start pulse. when (1).UDC=H, STV1 is output pin of start pulse. (2).UDC=L, STV1 is in high impedance state. Gate driver start pulse. when (1).UDC=H, STV2 is in high impedance state. (2).UDC=L, STV2 is output pin of start pulse. Source driver start pulse. when (1).LRC=H, STHL is in high impedance state. (2).LRC=L, STHL is output pin of start pulse. Source driver start pulse. when (1).LRC=H, STHR is output pin of start pulse. (2).LRC=L, STHR is in high impedance state. Negative polarity phase detector output. Gate driver shift clock. Source driver shift clock v1 . Source driver shift clock v2 . Source driver shift clock v3 . Note 1 Note 1 I Resolution mode selecting pin B Ground O I Inverted OSC signal output Master system clock input. This input pin is connected to the external VCO output for system clock timing & synchronization to the TV sync. signals through the phase locked loop block. Note 2 Note 2 I/O O I O O Inverter output Inverter input Output enable control signal for source driver Output enable control signal for source driver Note 1 Note 1 Description Remark

11

STV2

12 13

VCC STHL O

14

STHR

15 16 17 18 19 20 21 22 23 24 25 26

NPD CKV CK1A CK2A CK3A TEST TEST RC1 GND VCC OSC/O OSC/I

O O O O O

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SPEC NO.:233-220-053 PAGE :5/21

Pin no 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol VSY / O TEST GR VSY/I UD GND RC2 HSY/O Csync GND UDC TEST LRC LRA TEST TEST NPC PFRP TEST CP/O CP/I VCC O I Compare pulse output. Compare pulse input. I O It should be pulled to Vcc in normal operation. Polarity alternating signal for Vcom I O Left / Right scan control pin. Inverted LRC signal output. Note 1 Note 1 I I O I I I O Global reset. It should be connected to VCC in normal operation. If connected to GND, the controller is in reset state. Vertical synchronization signal input from the sync. separator of a TV system. It should be a negative polarity. Inverted UDC signal output. Ground Resolution mode selecting pin III . Negative polarity horizontal sync. output. Positive polarity composite sync. input. Ground Up / Down scan control pin. Note 1 I/O O Description Negative polarity vertical sync. output Note 1 Remark

Note 1 : All the test pins should be electrically opened. Note 2 : Resolution setting : A18 L L H H H RC1 L H L H L RC2 H H H H L Resolutiion mode (VXH) 220 X 528 220 X 280 234 X 960 234 X 480 234 X 1152 Appicable Mingstar LCD MTL020D01 SM261D series MTL025D01 , MTL040D01 MTL068D01, MTL070W01

This chip can drive different Mingstar's LCD according to the above table.

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SPEC NO.:233-220-053 PAGE :6/21

D.DC characteristics
1.Absolute maximum ratings:
SYMBOL VCC VIN VOUT TSTG PARAMETER Power supply Input voltage Output voltage Storage temperature RATING -0.3 to 6.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -40 to 125 UNITS V V V o C

2.Recommended operating conditions:

SYMBOL VCC VIN TOPR PARAMETER Power supply Input voltage Operating temperature MIN 4.5 0 -20 TYP 5.0 MAX 5.5 VCC 85 UNITS V V o C

3.General DC characteristics:
SYMBOL PARAMETER IIL Input low current IIH Input high current IOZ Tri-state leakage current CIN COUT VIL VSIL VIH VSIH VOL VOH RI Input capacitance Output capacitance Input low voltage Schmitt input low voltage Input high voltage Schmitt input high voltage Output low voltage Output high voltage Input pull up/down resistance CMOS CMOS CMOS CMOS IOL=4mA IOH=4mA VIL=0V or VIH=VCC CONDITIONS no pull-up or pull-down no pull-up or pull-down MIN -1 -1 -10 3 0.7Vcc 3.5 TYP 3 MAX 1 1 10 6 UNITS Remark lA lA lA pF pF V V V V V V KW Note 1 Note 1

0.3Vcc 1.76 3.2 0.4 50 -

Note 1: The applicable pins are A18, OSC/I, GR, VSY/I, Csync, CP/I. 4.Current consumption for 5 volts operating: Symbol Parameter Condition Min 3 5 Current 4 IIN Vcc=5V consumption 4 8 9

Typ 5 8 7 7 13 15

Max 7 11 10 10 18 21

Unit mA mA mA mA mA mA

Loading SM261D series MTL020D01 MTL025D01 MTL040D01 234 X 960 mode MTL068D01

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SPEC NO.:233-220-053 PAGE :7/21

E. AC characteristics
1.Timing condition ( i ) 220 X 280 resolution mode. a.Input signal characteristics
Parameter OSC/I period Csync period Csync pulse width Csync rising time Csync falling time VSY/I pulse width VSY/I rising time VSY/I falling Horizontal lines per field Symbol tOSC tH tCSYN tCr tCf tVSY tVr tVf Min. 150 61.5 4 1 256 Typ. 166 63.5 4.7 3 262.5 Max. 183 65.5 5.4 300 300 5 700 700 268 Unit. ns ls ls ns ns tH ns ns line Note 1 Remark

Note 1: Please don't use odd horizontal lines to drive LCD panel for both odd and even field simultaneously. b.Output signal characteristics
Parameter Rising time Falling time Clock high and low level pulse width Clock pulse duty 3v clock phase difference Symbol tr tf tCPH tCWH tC12 tC23 tC31 tSUH tSTH tHSY tOEH tDIS1 tOEV tCKV tCP tWCP t1 t2 t3 t4 Min. 40 Typ. 3 50 tCPH /3 Max. 10 10 60 Unit. ns ns tOSC % ns Remark Note 1 Note 1 CK1A~CK3A CK1A~CK3A

STH setup time STH pulse width HSY/O pulse width OEH pulse width Sample & hold disable time OEV pulse width CKV pulse width CP/O period CP/O pulse duty HSY/O-OEH timing difference HSY/O-CKV timing difference HSY/O-OEV timing difference HSY/O-CP/O timing difference

tCPH /2 1 9 2 16 10 11 1 1/2 5 4 3 6

ns tCPH tCPH tCPH tCPH tCPH tCPH tH tH tCPH tCPH tCPH tCPH

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SPEC NO.:233-220-053 PAGE :8/21

STV setup time STV pulse width VSY/O-STV1 timing difference(UDC="H") VSY/O-STV2 timing difference(UDC="L") OEH-STV timing difference tSUV tSTV tVS1 tVS2 tOES 2 1 19 19 2 tCPH tH tH tH tH

Note 1: For all of the logic signals.

( ii ) 234 X 480 resolution mode. a.Input signal characteristics

Parameter OSC/I period Csync period Csync pulse width Csync rising time Csync falling time VSY/I pulse width VSY/I rising time VSY/I falling Horizontal lines per field Symbol tOSC tH tCSYN tCr tCf tVSY tVr tVf Min. 94 61.5 4 1 256 Typ. 104 63.5 4.7 3 262.5 Max. 114 65.5 5.4 300 300 5 700 700 268 Unit. ns ls ls ns ns tH ns ns line Note 1 Remark

Note 1: Please don't use odd horizontal lines to drive LCD panel for both odd and even field simultaneously. b.Output signal characteristics
Parameter Rising time Falling time Clock high and low level pulse width Clock pulse duty 3v clock phase difference Symbol tr tf tCPH tCWH tC12 tC23 tC31 tSUH tSTH tHSY tOEH tDIS1 tOEV tCKV Min. 40 Typ. 3 50 tCPH /3 Max. 10 10 60 Unit. ns ns tOSC % ns Remark Note 1 Note 1 CK1A~CK3A CK1A~CK3A

STH setup time STH pulse width HSY/O pulse width OEH pulse width Sample & hold disable time OEV pulse width CKV pulse width

tCPH /2 1 15 3 27 13 20

ns tCPH tCPH tCPH tCPH tCPH tCPH

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SPEC NO.:233-220-053 PAGE :9/21

CP/O period CP/O pulse duty HSY/O-OEH timing difference HSY/O-CKV timing difference HSY/O-OEV timing difference HSY/O-CP/O timing difference STV setup time STV pulse width VSY/O-STV1 timing difference(UDC="H") VSY/O-STV2 timing difference(UDC="L") OEH-STV timing difference tCP tWCP t1 t2 t3 t4 tSUV tSTV tVS1 tVS2 tOES 1 1/2 8 6 2 10 3 1 19 19 2 tH tH tCPH tCPH tCPH tCPH tCPH tH tH tH tH

Note 1: For all of the logic signals.

( iii ) 220 X 528 resolution mode. a.Input signal characteristics

Parameter OSC/I period Csync period Csync pulse width Csync rising time Csync falling time VSY/I pulse width VSY/I rising time VSY/I falling Horizontal lines per field Symbol tOSC tH tCSYN tCr tCf tVSY tVr tVf Min. 85 61.5 4 1 256 Typ. 94 63.5 4.7 3 262.5 Max. 103 65.5 5.4 300 300 5 700 700 268 Unit. ns ls ls ns ns tH ns ns line Note 1 Remark

Note 1: Please don't use odd horizontal lines to drive LCD panel for both odd and even field simultaneously. b.Output signal characteristics
Parameter Rising time Falling time Clock high and low level pulse width Clock pulse duty 3v clock phase difference Symbol tr tf tCPH tCWH tC12 tC23 tC31 Min. 40 Typ. 3 50 tCPH /3 Max. 10 10 60 Unit. ns ns tOSC % ns Remark Note 1 Note 1 CK1A~CK3A CK1A~CK3A

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SPEC NO.:233-220-053 PAGE :10 /21

STH setup time STH pulse width HSY/O pulse width OEH pulse width Sample & hold disable time OEV pulse width CKV pulse width CP/O period CP/O pulse duty HSY/O-OEH timing difference HSY/O-CKV timing difference HSY/O-OEV timing difference HSY/O-CP/O timing difference STV setup time STV pulse width VSY/O-STV1 timing difference(UDC="H") VSY/O-STV2 timing difference(UDC="L") OEH-STV timing difference tSUH tSTH tHSY tOEH tDIS1 tOEV tCKV tCP tWCP t1 t2 t3 t4 tSUV tSTV tVS1 tVS2 tOES tCPH /2 1 18 5 27 14 24 1 1/2 8 7 1 12 4 1 19 19 2 ns tCPH tCPH tCPH tCPH tCPH tCPH tH tH tCPH tCPH tCPH tCPH tCPH tH tH tH tH

Note 1: For all of the logic signals.

( iv ) 234 X 960 resolution mode. a.Input signal characteristics

Parameter OSC/I period Csync period Csync pulse width Csync rising time Csync falling time VSY/I pulse width VSY/I rising time VSY/I falling Horizontal lines per field Symbol tOSC tH tCSYN tCr tCf tVSY tVr tVf Min. 47 61.5 4 1 256 Typ. 52 63.5 4.7 3 262.5 Max. 57 65.5 5.4 300 300 5 700 700 268 Unit. ns ls ls ns ns tH ns ns line Note 1 Remark

Note 1: Please don't use odd horizontal lines to drive LCD panel for both odd and even field simultaneously.

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SPEC NO.:233-220-053 PAGE :11 /21

b.Output signal characteristics
Parameter Rising time Falling time Clock high and low level pulse width Clock pulse duty 3v clock phase difference Symbol tr tf tCPH tCWH tC12 tC23 tC31 tSUH tSTH tHSY tOEH tDIS1 tOEV tCKV tCP tWCP t1 t2 t3 t4 tSUV tSTV tVS1 tVS2 tOES Min. 40 Typ. 3 50 tCPH /3 Max. 10 10 60 Unit. ns ns tOSC % ns Remark Note 1 Note 1 CK1A~CK3A CK1A~CK3A

STH setup time STH pulse width HSY/O pulse width OEH pulse width Sample & hold disable time OEV pulse width CKV pulse width CP/O period CP/O pulse duty HSY/O-OEH timing difference HSY/O-CKV timing difference HSY/O-OEV timing difference HSY/O-CP/O timing difference STV setup time STV pulse width VSY/O-STV1 timing difference(UDC="H") VSY/O-STV2 timing difference(UDC="L") OEH-STV timing difference

tCPH /2 1 30 7 54 26 40 1 1/2 14 12 4 20 6 1 19 19 2

ns tCPH tCPH tCPH tCPH tCPH tCPH tH tH tCPH tCPH tCPH tCPH tCPH tH tH tH tH

Note 1: For all of the logic signals.

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SPEC NO.:233-220-053 PAGE :12 /21

( v ) 234 X 1152 resolution mode. a.Input signal characteristics
Parameter OSC/I period Csync period Csync pulse width Csync rising time Csync falling time VSY/I pulse width VSY/I rising time VSY/I falling Horizontal lines per field Symbol tOSC tH tCSYN tCr tCf tVSY tVr tVf Min. 39 61.5 4 1 256 Typ. 43 63.5 4.7 3 262.5 Max. 47 65.5 5.4 300 300 5 700 700 268 Unit. ns ls ls ns ns tH ns ns line Note 1 Remark

Note 1: Please don't use odd horizontal lines to drive LCD panel for both odd and even field simultaneously. b.Output signal characteristics
Parameter Rising time Falling time Clock high and low level pulse width Clock pulse duty 3v clock phase difference Symbol tr tf tCPH tCWH tC12 tC23 tC31 tSUH tSTH tHSY tOEH tDIS1 tOEV tCKV tCP tWCP t1 t2 t3 t4 tSUV tSTV Min. 40 Typ. 3 50 tCPH /3 Max. 10 10 60 Unit. ns ns tOSC % ns Remark Note 1 Note 1 CK1A~CK3A CK1A~CK3A

STH setup time STH pulse width HSY/O pulse width OEH pulse width Sample & hold disable time OEV pulse width CKV pulse width CP/O period CP/O pulse duty HSY/O-OEH timing difference HSY/O-CKV timing difference HSY/O-OEV timing difference HSY/O-CP/O timing difference STV setup time STV pulse width

tCPH /2 1 36 9 62 40 50 1 1/2 18 14 12 26 8 1

ns tCPH tCPH tCPH tCPH tCPH tCPH tH tH tCPH tCPH tCPH tCPH tCPH tH

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SPEC NO.:233-220-053 PAGE :13 /21

VSY/O-STV1 timing difference(UDC="H") VSY/O-STV2 timing difference(UDC="L") OEH-STV timing difference tVS1 tVS2 tOES 19 19 2 tH tH tH

Note 1: For all of the logic signals. 2.Timing diagram Please refer to the attached drawing. from Fig.1 to Fig.4-(b).

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F. Test circuit

/PD R105 R106 823F R109 473F R111 473F R115 472F R112 104F R116 472F

C101 @102B 105F C102 C

R103 R L

R160 101F @225A R108 105F

S1 SW

CK3A CK2A CK1A CKV

C105 @104F U3 3 _ O 2 1 G + V

PH2

PH1

VCC

CKV

RC1

CK3A

CK2A

CK1A

NJM2107F C107 @104F C108 @104F

R113 R

R114 101F

25 26

STHR

STHL

PD(-)

GND

C106 C

D1 MA335

L101

R110 103F

R107 VR103F

24

23

22

21

20

19

18

17

16

15

14

13

U2

OSC/O OSC/I VSY/O HSYW GR VSY/I /UDC GND RC2 CP/I HSY/O CSYNC(+) GND /CSYNC PD_SW NP_SW UDC NPC CP/O VCC LRC FRP LRA TC

VCC

12 11 10 9 8 7 6 5 4 3 2 1

(DOWN) STV2 (UP) STV1

A18 Q1HA

C109 C -10VA +5VP

27 28 29 30 31

UPS015

GND FD D_MOD OEV OEH INV/I INV/O

R120 153F GND R122 103F

R121 393F Q101 2SB709A 1 2 3 R126 302F R127 103F

32 S5 SW 33 34 R123 102F 35 36

QM1 6 CSYN R154 153F R124 C110 @221C 153F R125 C111 @221C 204F 5 4 E1 B1 C2 XN4501 C1 B2 E2

37

38

39

40

41

42

43

44

45

46

47

GNDU

R170 503

VCCU FRP

48

VR503F S4 SW S3 SW R130 102F R129

VCCU

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SPEC NO.: 233-220-053 PAGE :15/21

G. Package information

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SPEC NO.:233-220-053 PAGE :16 /21

t SUH

t STH

t C31

tf

90% 90%

10%

t CPH

10%

t CWH

tr

STHL(R)

OSC/ O

OSC/ I

CK1A

CK2A

50%

50%

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CK3A

Fig.1

Sampling clock timing

t C12

t C23

SPEC NO.: 233-220-053 PAGE : 17/21

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SPEC NO.:233-220-053 PAGE :18 /21

(Csync)

STHL(R)

t3

HSY/O

Q1HA

(CP/ I)

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PFRP

OEV

CKV

OEH

CP/O

NPD

In 234 x 960 & 234 x 1152 resolution mode , Q1HA always keeps low. Fig.2-(b) Detail horizontal timing

tH

t STH

t CSYN

t HSY

t OEH

tDIS1

t CKV

t OEV

t1

t2

SPEC NO.:233-220-053 PAGE :19 /21

STV 1(2)

(C SYNC )

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CKV

Fig.3

Vertical shift clock timing

SPEC NO.:233-220-053 PAGE :20 /21

In 234 x 960 & 234 X 1152 resolution mode , Q1HA always keeps low.
STV1 PFRP(Even field) Q1HA PFRP(Odd field)

(Csync)

(VSY/ I)

t VSY

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OEH

Fig.4-(a) Vertical timing (UDC="H")

t OES

t VS1

SPEC NO.:233-220-053 PAGE :21 /21

In 234 x 960 & 234 x 1152 resolution mode , Q1HA always keeps low.
PFRP(Odd field) PFRP(Even field) Q1HA STV2

(VSY/ I)

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(Csync)

OEH

Fig.4-(b) Vertical timing (UDC="L")

t OES

t VS2

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