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Cache )L1 Data Cache( L1 64KB


.
Cache L1 ECC .
2 64 ( ) .
Cache ) L1 (L1 I-Cache 64 .
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L2 cache .

cache 16 .
L2 cache ECC .

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HyperTransport Mhz800 600 400 200


( 1200 800 400 ) MT/s 1600.

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CPU

HyperTransport .

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northbridge HyperTransport
CPU .

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Traditional

AMD

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CPU

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CPU

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DDR
SDRAM DIMM .

:

DIMM Registered 64 8
) (ECC :
DIMM 3 ....
Registered DIMM 4

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x-86 .

AMD64
MMX !3DNow

SSE , SSE2

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CPU

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CPU

RESET_L -1 1 PWROK . TMS 10


PWROK 10 PWROK High.

CLKIN_H/L-2 VDD .

PWROK -3 1 CLKIN_H/L
.
10 PWROK HyperTransport .
160-4 PLL PWROK .

-5 MEMCLK_H/L BIOS .
( MEMRESET_L-6 )Lidded parts BIOS Dram_init Dram
. . PLL DIMM
DIMM .

-7 MEMCLKA/B MEMRESET_L .

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CPU

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CPU

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A B .

.

.
] MEMBANKB[1:0 ] MEMADDB[13:0 A
.

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DIMM 2 6 DIMM 3 9
. 6
.

MEMRESET_L DIMM reset


Ram ) (ACPI S3 .

( )Ram 4 .

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power on reset MEMCKEA/B MEMRESET_L LOW PLL


.
. ] MEMCLK_H/L[7:0 BIOS
CLOCK .

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CPU

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CPU

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