Review for Exam 2

Using MUXs to implement logic Using ROMs to implement logic Timing Analysis The internal structure of flip-flops Flip-flop timings Rising and falling edge triggered flip-flops

Counters and state machines

Generating next state equations from counter sequences. Implementation using RS, D, T and JK flip-flops Reading state sequence from timing diagrams

Determining next states from schematics

Moore vs. Mealy Max frequency for a state machine Verilog code

Implementing Logic Functions With Muxes

Implement:

Z = AB + BC
AB C
0 1 00 01 11 10

I0 I1 4-to-1
MUX

0 0

1 1

1 0

0 0

I2 I3

for AB=00, Z=0 A B

Implementing Logic Functions With Muxes

Implement:

Z = AB + BC
AB C
0 1 00 01 11 10

0 1

I0 I1 4-to-1
MUX

0 0

1 1

1 0

0 0

I2 I3

for AB=01, Z=1 A B

Implementing Logic Functions With Muxes

Implement:

Z = AB + BC
AB C
0 1 00 01 11 10

0 1

I0 I1 4-to-1
MUX

0 0

1 1

1 0

0 0

I2

I3

for AB=11, Z=C

Implementing Logic Functions With Muxes

Implement:

Z = AB + BC
AB C
0 1 00 01 11 10

0 1 0 C

I0 I1 4-to-1
MUX

0 0

1 1

1 0

0 0

I2 I3

Implementing Logic Functions With Muxes

An alternate method
Z = AB + BC
A=0 B=0 A=0 B=1 A=1 B=0 A=1 B=1

Z = 1 0 + 0 C = 0 Z = 1 1 + 1 C = 1 Z = 0 0 + 0 C = 0 Z = 0 1 + 1 C = C

0 1 0 C

I0 I1 4-to-1
MUX

I2 I3

Using a ROM For Logic

Specify a truth table for a ROM which implements:
F = AB + ABC
G = ABC + C H = ABC + ABC + ABC

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Using a ROM For Logic

Specify a truth table for a ROM which implements:
F = AB + ABC
G = ABC + C H = ABC + ABC + ABC

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 0 0 1 0 0 0 1 1

Using a ROM For Logic

Specify a truth table for a ROM which implements:
F = AB + ABC
G = ABC + C H = ABC + ABC + ABC

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 0 0 1 0 0 0 1 1

G 1 1 1 0 1 0 1 0

Using a ROM For Logic

Specify a truth table for a ROM which implements:
F = AB + ABC
G = ABC + C H = ABC + ABC + ABC

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 0 0 1 0 0 0 1 1

G 1 1 1 0 1 0 1 0

H 0 1 0 0 1 0 1 0

Timing Analysis
A B=1 C=1 D
A B AB E C D CD F E+F X

E X F

Timing Analysis
A B=1 C=1 D
A B AB E C D CD F E+F X

E X F

Timing Analysis
A B=1 C=1 D
A B AB E C D CD F E+F X

E X F

Timing Analysis
A B=1 C=1 D
A B AB E C D CD F E+F X

E X F

Timing Analysis
A B=1 C=1 D
A B AB E C D CD F E+F X

E X F

Timing Analysis
A B=1 C=1 D
A B AB E C D CD F E+F X

E X F

Timing Analysis
A B=1 C=1 D
A B AB E C D CD F E+F X

E X F

The internal structure of flip-flops

D Q R GR Q S GS GATE GATE

D Q Q

CLK

D-type Flip-Flop

The internal structure of flip-flops

Q T Q

CLK

T-type Flip-Flop

The internal structure of flip-flops

J
Q

CLK

JK-type Flip-Flop

Flip-flop timings Clock-to-Q

D Q

CLK

tCLK Q = tNOT + tAND + 2 x tNOR

Flip-flop timings Clock-to-Q

CLK D Q

tCLK Q
time

Flip-flop timings Setup time

D
Q

CLK

tsetup = tNOT + tAND + 2 x tNOR

Flip-flop timings Setup time

tsetup
CLK D Q

time

Flip-flop timings Hold time

D
Q

thold = tNOT
CLK

Flip-flop timings Hold time

thold = tNOT
Clock edge
CLK D Q

AND gate turns off, D can change

time

Flip Flop Timing thold

tsetup
CLK D Q

tCLK Q
time

Rising and falling edge triggered flip-flops

D Q

CLK

Falling Edge Triggered DFF

Rising and falling edge triggered flip-flops

D Q

CLK

Rising Edge Triggered DFF

Generating next state equations from counter sequences.

Desired count sequence = 00 01 00 10 11 00

If current state = 00, next state = ?????

Implemented count sequence = 000

001

100

110

011

000

Q2 Q1 Q0 N2 N1 N0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 X X X 0 0 1 1 0 X X X 1 0 0 1 0 X X X

N2 = Q2 Q1 + Q1 Q0 N1 = Q2 N0 = Q2 Q0 + Q1 Q0

Implementation using RS, D, T and JK flip-flops

S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 0 1 1 N/A N/A Comment No change Reset Set
J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 0 1 1 1 0 Comment No change Reset Set Toggle

T 0 0 1 1

Q 0 1 0 1

Q+ 0 1 1 0

Q 0 0 1 1

Q+ 0 1 0 1

J 0 1 x x

K x x 1 0

Q 0 0 1 1

Q+ 0 1 0 1

T 0 1 1 0

Reading state sequence from timing diagrams

W X Y Z

WXYZ = 0010, 0110, 0011, 0101, 1100, 1000, 1001, 1101, 1110, 0010

Determining next states from schematics

Q2 Q1 Q1 Q0 CLK Q1 Q2

Q2 Q1 Q0

D Q

Initial state

0
0 1 1

0
0 0 1

0
1 0 0

Q2

D Q

Q2 Q0

CLK

Q1
Q0

D Q

Q0

CLK

Moore vs. Mealy

Outputs Output Timing

Delay Logic

Moore Function of Current State Only Outputs Available After Clock Transition (plus Gate Delays) Output Delayed One Clock Cycle Requires more

Mealy Function of Current State and Current Inputs Outputs Available Anytime (After Inputs Stabilize) Output Available on Current Clock Cycle Requires less

Max frequency for a state machine

Steps:

1. Determine the delay through the Flip Flops 2. Determine the delay through the IFL (max) 3. Add in setup time 4. Determine the smallest clock period possible 5. Max frequency = 1 -----------------clock period

Structural Verilog Code

and (output, input1, input2, );

nand (output, input1, input2, );

or (output, input1, input2, ); nor (output, input1, input2, ); not (output, input1); buf (output, input1); xor (output, input1, input2, ); xnor (output, input1, input2, );

Structural Verilog Code example

module mux21(q, sel, a, b); input sel, a, b; output q; wire selbar, a1, a2; not(selbar, sel); and(a1, selbar, a); and(a2, sel, b); or(q, a1, a2); endmodule a sel b

selbar

a1 a2

Dataflow Verilog Code

Operator Type Operator Symbol Operation Performed Comments * and / take LOTS of 2 hardware 2 1 As in C 2 As in C 2 As in C 1 As in C 2 As in C 2 As in C 2 As in C 2 2 As in C 2 As in C 1 Multi-bit input 1 Multi-bit input 1 Multi-bit input 1 Multi-bit input 1 Multi-bit input 1 Multi-bit input 2 Fill with 0's 2 Fill with 0's Any number Any number 3 As in C # of Operands

Arithmetic *, /, +, % Logical ! && || Bitwise ~ & | ^ ~^ Relational <, >, <=, >= Equality ==, != Reduction & ~& | ~| ^ ~^ Shift << >> Concat { } Replicate { { } } Cond ?:

As expected Modulo Logic NOT Logic AND Logic OR Bitwise NOT Bitwise AND Bitwise OR Bitwise XOR Bitwise XNOR As expected As expected Red. AND Red. NAND Red. OR Red. NOR Red. XOR Red. XNOR Left shift Right shift Concatenate Replicate As expected

Dataflow Verilog Code example

module mux21(q, sel, a, b); input sel, a, b; output q; assign q = (~sel & a) | (sel & b); endmodule OR

module mux21(q, sel, a, b); input sel, a, b; output q; assign q = sel?b:a; endmodule

Verilog Code Heirarchy

module mux41(q, sel, a, b, c, d); input[1:0] sel; input a, b, c, d; output q; wire tmp1, tmp2; mux21 M0(tmp1, sel[0], a, b); mux21 M1(tmp2, sel[0], c, d); mux21 M2(q, sel[1], tmp1, tmp2); endmodule a b c d sel[0] mux21 mux21 sel
2

a b c d

mux41

tmp1
sel[1] mux21 q

tmp2