Subject: professional practice

Topic: 8155-multipurpose programmable device

INTRODUCTION TO 8155
The 8155 is a multipurpose programmable peripheral device. It has a RAM & i/o ports built into itself Internally latch is present It is generally used to implement a minimum system with 8085 processor

block schematic OF 8155

VCC (+5V)
GND (0V)

CE
IO/M AD0-AD7 ALE RD WR

8155

PA 0-7

256*8 Static RAM

PB 0-7

PC 0-5

Timer

RESET

Timer in

Timer out

Pin diagram of 8155

Features

A 256 byte RAM 2 programmable 8 bit I/O ports 1 programmable 6 bit I/O port 1 programmable 14 bit binary counter/timer Internal address latch to demultiplxed AD0-AD7,using ALE line

Internal block diagram of 8155

Functions of blocks
Internal latch: it is used to latch lower address bus from data bus. Internal decoder: it is used to select the ports and control reg. CWR- it is used to select the ports in I/P or O/P mode. Ports: they can be used in I/P or O/P mode depending upon data pattern written in the control register.

Registers of 8155
Port A Port B Port C Timer Register Control Register Status Register

Control word (command register) format: D7 Timer command

D6

D5 IEB

D4 IEA

D3 PC

D2

D1 PB

D0 PA

D0, D1: mode for PA and PB, 0=i/p, 1=o/p D2, D3: mode for PC D4, D5: interrupt enable for PA and PB, 0=disable 1=enable D6, D7: Timer command: o 00: No effect o 01: Stop if running else no effect o 10: Stop after terminal count (TC) if running, else no effect o 11: Start if not running, reload at TC if running.

Port C bits (D2, D3): ALT D3 D2 PC5 PC4 PC3 PC2 1 0 0 I 2 1 1 O 3 0 1 O I O O I O O I O PC1 PC0 I O I O

STB - A BF-A INTR-A

4 1 0 STB-B BF-B INtR-B STB-A BF-A INTR-A I - input O - output

Timer register
M2 M1 T15 T12 T11 T10 T9 T8

TIMER MODE

MSB OF CNT LENGTH

T7

T6

T5

T4

T3

T2

T1

T0

LSB OF CNT LENGTH

Interfacing of 8155
8085
AD0-AD7 IO/M RD WR ALE RESET OUT A15 A14

8155
AD0-AD7 IO/M RD WR ALE RESET Port A

Port B

A13
A12 A11

G2A G2B G1 7 C 6 5 3:8 B decoder 4 2 A 1 0

Port C

CS

Thank you