HARDWARE SUPPORT FOR EXPOSING MORE PARALLELISM AT COMPILE TIME.

# Introduction: The behavior of branch is not well known at compile time, couldnt uncover much ILP. Parallelism severely limited by control dependence and Memory reference. # Conditional or Predicated Instructions: Converting a control dependence into a data dependence, improve performance, eliminate branches and extremely useful for short sequence. Conditional move instruction: This moves a value from one register to another if the condition is true. Ex:1 original Code Branch Some Architectures have conditional instruction If ( A== 0 ) BNEZ R1, L; CMOV R2,R3,R1 // if conversion. { S=T } ADD R2, R3, R0 * used in Vector machine, Dependency is resolved: End of the pipeline * Front of the pipeline Ex: 2 code segment for absolute integer. // pair of conditional moves
If ( b < 0 ) { A= -B; } else { A=B; } Predicated Instruction: Convert the entire code segment to predicated execution or

speculatively move an instruction; make it predict and remove a control dependency. o Full predicate allows us to simply convert large block of code that are branch dependent Waste slot since 3rd LW dependent on result of 2nd LW
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Complication of Predicated Instruction: o Annulled ( Declare valid or invalid ) during instruction issue. o Predicated instructions are later in the pipeline before they commit any result or raises on exception. - Several factors are limited, o Predicated Instruction are annulled still take some processor resource ( slow down processor ) o Predicated Instructions are most useful when the predicate can be evaluated early but conditional evaluation and Predicated Instruction are not separated therefore that introduces data dependency ( Stalled ) o Conditional Instruction limited when control flow involves simple alternative sequence. o Conditional instructions have some speed penalty. Ex: MIPS, Alpha, Pentium processor support some conditional instruction. All the instructions in IA64 architecture support predicated # Compiler Speculation with hardware support: To move speculated instruction not only before the branch but before the conditional evaluation and predicated cannot achieve this. To speculate ambitiously requires 3 capabilities: Ability of the compiler (use of Register Renaming) to find instructions that can be speculatively moved and not affect the program data flow Ability of HW to ignore exceptions in speculated instructions, until we know that such exceptions should really occur Ability of HW to speculatively interchange loads and stores, or stores and stores, which may have address conflicts Two types of exceptions needs to be distinguished: Exceptions cause program error, which indicates the program must be terminated. Ex., memory protection error. Exceptions can be normally resumed, Ex., page faults #HW Support for Preserving Exception Behavior How to make sure that a mis-predicted speculated instruction (SI) can not cause an exception by Four methods HW and OS cooperatively ignore exceptions for SI o Return an undefined value for any terminating exception The program is allowed to continue, but almost generate incorrect results If the excepting instruction is not speculative program in error If the excepting instruction is speculativeprogram correct but speculative result will simply be unused (No harm) Never cause a correct program to fail, no matter how much speculation.

SI that never raise exceptions are used, and checks are introduced to determine when an exception should occur

Poison bits are attached to the result registers written by SI when SI causes exceptions. The poison bits cause a fault when a normal instruction attempts to use the register. Special instruction is needed to update poison bit of resultant speculated instruction

A mechanism to indicate that an instruction is speculative, and HW buffers the instruction result until it is certain that the instruction is no longer speculative o Speculative Instruction marked as sentinel if no longer speculative then allow the in-order commit otherwise raise an exception.
# HW Support for Memory Reference Speculation: H/W Use a special instruction to check for address conflicts. Speculated load in case if subsequent store before check instruction then speculation failed otherwise successful speculation. Speculation failure handling in two ways If only the load instruction was speculated, redo the load at the point of the check instruction If additional instruction that depended on the load were also speculated, then a fix-up sequence that re-executes all the SI starting with the load is needed Penalties!!