Siemens Simatic S 7 300 - 400 - Function Block Diagram For S7-300 and S7-400

Preface, Contents
Product Overview 1
Configuration and Elements of
Function Block Diagram 2
SIMATIC S7 Addressing 3
Bit Logic Instructions 4

Function Block Diagram (FBD)
for S7-300 and S7-400 Timer Instructions 5
Programming
Counter Instructions 6
Reference Manual
Integer Math Instructions 7
Floating-Point Math Instructions 8

This reference manual is part of the documentation
package with the order number: Comparison Instructions 9
Move and Conversion
6ES7810-4CA04-8BR0 Instructions 10
Word Logic Instructions 11
Shift and Rotate Instructions 12
Data Block Instructions 13
Jump Instructions 14
Status Bit Instructions 15
Program Control Instructions 16
10/98 Appendix
C79000-G7076-C566
Glossary, Index
Release 01
Safety Guidelines This manual contains notices which you should observe to ensure your own personal safety, as well as to
protect the product and connected equipment. These notices are highlighted in the manual by a warning
triangle and are marked as follows according to the level of danger:
Danger
! indicates that death, severe personal injury or substantial property damage will result if proper precautions
are not taken.
Warning
! indicates that death, severe personal injury or substantial property damage can result if proper precautions
are not taken.
Caution
! indicates that minor personal injury or property damage can result if proper precautions are not taken.
Note
draws your attention to particularly important information on the product, handling the product, or to a
particular part of the documentation.
Correct Usage Note the following:
Warning
! This device and its components may only be used for the applications described in the catalog or the
technical description, and only in connection with devices or components from other manufacturers which
have been approved or recommended by Siemens.
Trademarks SIMATIC, SIMATIC HMI and SIMATIC NET are registered trademarks of SIEMENS
AG.
Third parties using for their own purposes any other names in this document which refer to trademarks might
infringe upon the rights of the trademark owners.
Copyright Siemens AG 1998 All rights reserved

The reproduction, transmission or use of this document or its contents is We have checked the contents of this manual for agreement with the
not permitted without express written authority. Offenders will be liable for hardware and software described. Since deviations cannot be precluded
damages. All rights, including rights created by patent grant or registration entirely, we cannot guarantee full agreement. However, the data in this
of a utility model or design, are reserved. manual are reviewed regularly and any necessary corrections included in
subsequent editions. Suggestions for improvement are welcomed.
Siemens AG
Bereich Automatisierungs- und Antriebstechnik
Geschaeftsgebiet Industrie-Automatisierungssysteme Siemens AG 1998
Postfach 4848, D-90327 Nuernberg Technical data subject to change.
Siemens Aktiengesellschaft C79000-G7076-C566
Function Block Diagram (FBD) for S7-300 and S7-400

Preface
Purpose of the This manual is your guide to creating user programs in the Function Block
Manual Diagram (FBD) programming language.
This manual also includes a reference section that describes the syntax and
functions of the language elements of Function Block Diagram.
Audience The manual is intended for S7 programmers, operators, and

maintenance/service personnel. A working knowledge of automation
procedures is essential.
Where is this This manual is valid for release 5.0 of the STEP 7 programming software
Manual Valid? package.
Which Standards FBD corresponds to the “Function Block Diagram” language defined in the
Does the Software International Electrotechnical Commission’s standard IEC 1131-3. For
Comply With? further details, refer to the table of standards in the STEP 7 file
NORM_TBL.WRI.

C79000-G7076-C566-01 iii
Preface
Requirements To use this Function Block Diagram manual effectively, you should already
be familiar with the theory behind S7 programs which is documented in the
online help for STEP 7. The language packages also use the STEP 7 standard
software, so you should be familiar with handling this software and have read
the accompanying documentation.
Documentation Purpose Order Number

STEP 7 Basic Information with Basic information for technical 6ES7810-4CA04-8BA0
Working with STEP 7 V5.0, Getting Started personnel describing the methods of
Manual implementing control tasks with
STEP 7 and the S7-300/400
Programming with STEP 7 V5.0
programmable controllers.
Configuring Hardware and Communication
Connections, STEP 7 V5.0
From S5 to S7, Converter Manual
STEP 7 Reference with Provides reference information and 6ES7810-4CA04-8BA0
Ladder Logic (LAD)/Function Block describes the programming
Diagram (FBD)/Statement List (STL) for languages LAD, FBD and STL and
S7-300/400 manuals standard and system functions
extending the scope of the STEP 7
Standard and System Functions for basic information.
S7-300/400
Online Helps Purpose Order Number

Help on STEP 7 Basic information on programming Part of the STEP 7
and configuring hardware with Standard software.
STEP 7 in the form of an online
help.
Reference helps on STL/LAD/FBD Context-sensitive reference Part of the STEP 7
Reference help on SFBs/SFCs information. Standard software.
Reference help on Organization Blocks
Accessing the You can display the online help in the following ways:
Online Help
Context-sensitive help about the selected object with the menu command
Help > Context-Sensitive Help, with the F1 function key, or by clicking
the question mark symbol in the toolbar.
Help on STEP 7 via the menu command Help > Contents.
References References to other documentation are indicated by reference numbers in

slashes /.../. Using these numbers, you can check the exact title in the
References section at the end of the manual.

iv C79000-G7076-C566-01
Preface
SIMATIC Customer The SIMATIC Customer Support team offers you substantial additional
Support Online information about SIMATIC products via its online services:
Services
General current information can be obtained:
– on the Internet under
http://www.ad.siemens.de/simatic/html_00/simatic
– via the Fax-Polling number 08765-93 02 77 95 00
Current product information leaflets and downloads which you may find
useful are available:
– on the Internet under http://www.ad.siemens.de/support/html_00/
– via the Bulletin Board System (BBS) in Nuremberg (SIMATIC
Customer Support Mailbox) under the number +49 (911) 895-7100.
To dial the mailbox, use a modem with up to V.34 (28.8 Kbps) with
the following parameter settings: 8, N, 1, ANSI; or dial via ISDN
(x.75, 64 Kbps).
Additional If you have other questions, please contact the Siemens representative in your
Assistance area. The addresses are listed, for example, in catalogs and in Compuserve
(go autforum).
Our SIMATIC Basic Hotline is also ready to help:
in Nuremberg, Germany
– Monday to Friday 07:00 to 17:00 (local time): telephone:
+49 (911) 895–7000
– or E-mail: simatic.support@nbgm.siemens.de
in Johnson City (TN), USA
+1 423 461–2522
– or E-mail: simatic.hotline@sea.siemens.com
in Singapore
+65 740–7000
– or E-mail: simatic@singet.com.sg
The SIMATIC Premium Hotline is available round the clock worldwide
with the SIMATIC card (telephone: +49 (911) 895-7777).
Courses for Siemens offers a number of training courses to introduce you to the SIMATIC
SIMATIC Products S7 automation system. Please contact your regional training center or the
central training center in Nuremberg, Germany for details:
Telephone: +49 (911) 895-3154.

C79000-G7076-C566-01 v
Preface
Questionnaires on To help us to provide the best possible documentation for you and future
the Manual and STEP 7 users, we need your support. If you have any comments or
Online Help suggestions relating to this manual or the online help, please complete the
questionnaire at the end of the manual and send it to the address shown.
Please include your own personal rating of the documentation.

vi C79000-G7076-C566-01
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
1 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2 Configuration and Elements of Function Block Diagram . . . . . . . . . . . . . . . . . . . 2-1
2.1 Elements and Box Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Boolean Logic and Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3 Significance of the CPU Registers in Statements . . . . . . . . . . . . . . . . . . . . 2-9
3 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Types of Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
4 Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 AND Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3 OR Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4 AND-before-OR Logic Operation and OR-before-AND Logic Operation . 4-5
4.5 Exclusive OR Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.6 Insert Binary Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.7 Negate Binary Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.8 Assign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.9 Midline Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.10 Save RLO to BR Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.11 Set Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.12 Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.13 Set Counter Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.14 Up Counter Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.15 Down Counter Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.16 Pulse Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.17 Extended Pulse Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20

C79000-G7076-C566-01 vii
Contents
4.18 On-Delay Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22

4.19 Retentive On-Delay Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
4.20 Off-Delay Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
4.21 Positive RLO Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
4.22 Negative RLO Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
4.23 Address Positive Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
4.24 Address Negative Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
4.25 Set_Reset Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
4.26 Reset_Set Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
5 Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Memory Areas and Components of a Timer . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Choosing the Right Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3 Pulse S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.4 Extended Pulse S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.5 On-Delay S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.6 Retentive On-Delay S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.7 Off-Delay S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
6 Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1 Memory Address and Components of a Counter . . . . . . . . . . . . . . . . . . . . . 6-2
6.2 Up-Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.3 Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.4 Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
7 Integer Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1 Add Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2 Add Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.3 Subtract Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.4 Subtract Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.5 Multiply Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.6 Multiply Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.7 Divide Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.8 Divide Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.9 Return Fraction Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.10 Evaluating the Bits of the Status Word with Integer Math Instructions . . . 7-11

viii C79000-G7076-C566-01
Contents
8 Floating-Point Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2 Add Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.3 Subtract Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.4 Multiply Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.5 Divide Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.6 Evaluating the Bits of the Status Word with Floating-Point Instructions . . 8-7
8.7 Forming the Absolute Value of a Floating-Point Number . . . . . . . . . . . . . . 8-8
8.8 Forming the Square (SQR) of a Floating-Point Number . . . . . . . . . . . . . . . 8-9
8.9 Forming the Square Root (SQRT) of a Floating-Point Number . . . . . . . . . 8-10
8.10 Forming the Natural Logarithm of a Floating-Point Number . . . . . . . . . . . . 8-11
8.11 Forming the Exponential Value of a Floating-Point Number . . . . . . . . . . . . 8-12
8.12 Forming Trigonometric Functions of Angles as Floating-Point Numbers . 8-13
9 Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1 Compare Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2 Compare Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.3 Compare Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
10 Move and Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1 Assign Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.2 BCD to Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.3 Integer to BCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.4 Integer to Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.5 BCD to Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.6 Double Integer to BCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.7 Double Integer to Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.8 Ones Complement Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.9 Ones Complement Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.10 Twos Complement Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.11 Twos Complement Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.12 Negate Real Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.13 Round to Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.14 Truncate Double Integer Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.15 Ceiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.16 Floor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17

C79000-G7076-C566-01 ix
Contents
11 Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2 (Word) AND Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3 (Word) AND Double Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.4 (Word) OR Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.5 (Word) OR Double Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.6 (Word) Exclusive OR Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.7 (Word) Exclusive OR Double Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
12 Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2 Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
13 Data Block Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1 Open Data Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
14 Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.2 Unconditional Jump in a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.3 Conditional Jump in a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.4 Jump-If-Not . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.5 Jump Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
15 Status Bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.2 Exception Bit Binary Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.3 Result Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.4 Exception Bit Unordered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.5 Exception Bit Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.6 Exception Bit Overflow Stored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
16 Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1 Calling an FC/SFC without Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.2 Calling an FB, FC, SFB, SFC, and Multiple Instances . . . . . . . . . . . . . . . . 16-4
16.3 Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
16.4 Master Control Relay Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
16.5 Master Control Relay Activate/Deactivate . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.6 Master Control Relay On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
A Alphabetical Lists of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1 List of Instructions with International Names . . . . . . . . . . . . . . . . . . . . . . . . A-2

x C79000-G7076-C566-01
Contents
A.2 List of Instructions with International (English) Names and German

Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
A.3 List of Instructions with German SIMATIC Names . . . . . . . . . . . . . . . . . . . . A-10
A.4 List of Instructions with German Names and International (English)
Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14
B Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
B.2 Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
B.3 Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
B.4 Counter and Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11
B.5 Integer Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13
B.6 Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14
C References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary-1
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index-1

C79000-G7076-C566-01 xi
Contents

xii C79000-G7076-C566-01
Product Overview 1
What is FBD? FBD stands for Function Block Diagram. FBD is a graphic programming
language and uses logic boxes familiar from Boolean algebra to represent
logic. Complex functions (for example math functions) can also be
represented directly connected to the logic boxes.
The FBD The Function Block Diagram programming language has all the elements
Programming necessary for creating a complete user program. It contains a wide range of
Language instructions. These include the various basic instructions and a wide range of
addresses and address types. Functions and function blocks allow you to
structure your FBD program clearly.
The Programming The FBD programming package is an integral part of the STEP 7 Standard
Package Software. This means that following the installation of your STEP 7 software,
all the editor functions, compiler functions, and test/debug functions for FBD
are available to you.
Using FBD, you can create your own user program. With the Incremental
Editor, the input of the local data structure is made easier with the help of
table editors.
There are three programming languages in the standard software, STL, FBD,
and LAD. You can switch from one language to the other almost without
restriction and choose the most suitable language for the particular block you
are programming.
If you write programs in LAD or FBD, you can always switch over to the
STL representation. If you convert LAD programs into FBD programs and
vice versa, program elements that cannot be represented in the destination
language are displayed in STL.

C79000-G7076-C566-01 1-1
1-2 C79000-G7076-C566-01
Configuration and Elements of Function
Block Diagram 2
Chapter Section Description Page
Overview 2.1 Elements and Box Structure 2-2
2.2 Boolean Logic and Truth Tables 2-6
2.3 Significance of the CPU Registers in Statements 2-9

C79000-G7076-C566-01 2-1
Configuration and Elements of Function Block Diagram
2.1 Elements and Box Structure
FBD Instructions FBD instructions consist of elements and boxes that are connected
graphically to form networks. The elements and boxes can be classified in
the following groups:
Instructions as STEP 7 represents some of the FBD instructions as individual elements that
Elements do not require addresses or parameters (see Table 2-1).
Table 2-1 FBD Instruction as an Element without Address or Parameters
Element Description Section in this Manual
Negate binary input 4.7
Instruction as a STEP 7 represents some of the FBD instructions as boxes for which you must
Box with Address specify an address (see Table 2-2). For more detailed information about
addressing, refer to Chapter 3.
Table 2-2 FBD Instruction as Box with Address
<Address>
Assign 4.8
=
Instruction as a STEP 7 represents some of the FBD instructions as boxes for which you
Box with Address specify an address and a value (for example a timer or counter value, see
and Value Table 2-3).
For more detailed information about addressing, refer to Chapter 3.
Table 2-3 FBD Instruction as a Box with Address and Value

<Address>>
SS
Retentive on-delay timer 4.19
<Time
TV
value>

2-2 C79000-G7076-C566-01
Instruction as Box STEP 7 represents some of the FBD instructions as boxes with inputs and
with Parameters outputs (see Table 2-4). The inputs are on the left of the box and the outputs
on the right. You specify the input parameters and some of the output
parameters. Most outputs are provided by the STEP 7 software. To assign
parameters, you must use the specific notation of the data types.
The parameters of the Enable input (EN) and the Enable output (ENO) are
described below. For further information about input and output parameters,
refer to the descriptions of the individual instructions in this manual.
Table 2-4 FBD Operation as a Box with Inputs and Outputs
Box Description Section in this Manual
DIV_R
EN
Divide real 8.5
IN1 OUT
IN2 ENO
Enable Input and If the Enable input (EN) of an FBD box is activated, the box carries out a
Enable Output specific function. If the function is executed by the box without errors, the
Parameters Enable output (ENO) is activated. The parameters EN and ENO of an FBD
box are of the BOOL data type and can be located in the I, Q, M, D, or L
memory areas (see Table 2-5 and 2-6).
How EN and ENO function is described below:
If EN is not activated (its signal state is 0), the box does not execute its
function and ENO is not activated (its signal state is also 0).
If EN is activated (its signal state is 1) and if the box executes its function
without errors, ENO is also activated (its signal state is also 1).
If EN is activated (its signal state is 1) and if an error occurs during the
execution of the function, ENO is not activated (its signal state remains
0).
Memory Areas and The majority of the addresses in FBD refer to memory areas. The following
Functions table shows the types and their functions.

C79000-G7076-C566-01 2-3
Table 2-5 Memory Areas and Their Functions
Access to Area
Name of Area Function of Area Using Units of the Abbr.
Following Size:
Process input At the beginning of the scan cycle, the operating system reads Input bit I
image the inputs from the process and records the values in this area. Input byte IB
The program uses these values when it is running cyclically. Input word IW
Input double word ID
Process output During the scan cycle, the program calculates output values and Output bit Q
image enters them in this area. At the end of the scan cycle, the Output byte QB
operating system reads the calculated output values from this Output word QW
area and sends them to the process outputs. Output double word QD
Bit memory This area provides memory space for interim results calculated Memory bit M
in the program. Memory byte MB
Memory word MW
Memory double word MD
I/Os Using this area, your program has direct access to input and Peripheral input byte PIB
output modules (peripheral inputs and outputs). Peripheral input word PIW
Ext. inputs Peripheral input double PID
word
I/Os: Peripheral output byte PQB
Peripheral output word PQW
Ext. outputs Peripheral output double PQD
word
Timers Timers are function elements in FBD. This area provides Timer (T) T
memory space for timer cells. In this area, the clock timing
accesses the timer cells and updates them by decrementing the
timer value. Timer operations access these timer cells.
Counters Counters are function elements in FBD. This area provides Counter (C) C
memory space for counters. Count instructions access the cells
in this area.
Data block This area contains data that can be accessed from within any Data block opened with
block. If it is necessary to open two data blocks at the same the “OPN DB”
time, you can open one with the “OPN DB” instruction and the instruction:
other with the “OPN DI” instruction. The notation of the Data bit DBX
addresses, for example L DBWi and L DIWi identifies the data Data byte DBB
block to be accessed. Data word DBW
Although you can access any data block with the “OPN DI” Data double word DBD
i
instruction,
i this
hi iinstruction
i iis mainly
i l used
d to open iinstance ddata Data block opened with
blocks that are assigned to function blocks (FBs) and system the “OPN DI”
function blocks (SFBs). For more detailed information about instruction:
FBs and SFBs, refer to the STEP 7 Online Help. Data bit DIX
Data byte DIB
Data word DIW
Data double word DID
Local data This area contains temporary local data belonging to a logic Temporary local data bit L
block (FB or FC). This type of data is also called dynamic local Temporary local data LB
data. This area is used as a buffer. When the logic block is byte
closed, the data are lost. These data are located in the local data Temporary local data LW
stack (L stack). word
Temporary local data LD
double word

2-4 C79000-G7076-C566-01
Table 2-6 lists the maximum address ranges for the various memory areas.
For more detailed information about the address ranges on your CPU, refer to
the corresponding manual /70/ or /101/.
Table 2-6 Memory Areas and Their Address Ranges
Access Using
Name of Area M i
Maximum Address
Add Range
R
Units of the Following Sizes: Abbr.
Process input image Input bit I 0.0 to 65 535.7
Input byte IB 0 to 65 535
Input word IW 0 to 65 534
Input double word ID 0 to 65 532
Process output Output bit Q 0.0 to 65 535.7
image Output byte QB 0 to 65 535
Output word QW 0 to 65 534
Output double word QD 0 to 65 532
Bit memory Memory bit M 0.0 to 255.7
Memory byte MB 0 to 255
Memory word MW 0 to 254
Memory double word MD 0 to 252
I/Os: Peripheral input byte PIB 0 to 65 535
External inputs Peripheral input word PIW 0 to 65 534
Peripheral input double word PID 0 to 65 532
I/Os: Peripheral output byte PQB 0 to 65 535
External outputs Peripheral output word PQW 0 to 65 534
Peripheral output double word PQD 0 to 65 532
Timers Timer T 0 to 255
Counters Counter C 0 to 255
Data block Data block opened with the DB [OPN]
instruction
Data bit in the data block DBX 0.0 to 65 535.7

Data byte DBB 0 to 65 535
Data word DBW 0 to 65 534
Data double word DBD 0 to 65 532
Data block opened with the DI [OPN] instruction
Data bit in the instance DB DIX 0.0 to 65 535.7

Data byte DIB 0 to 65 535
Data word DIW 0 to 65 534
Data double word DID 0 to 65 532
Local data 1) Temporary local data bit L 0.0 to 65 535.7
Temporary local data byte LB 0 to 65 535
Temporary local data word LW 0 to 65 534
Temporary local data double word LD 0 to 65 532
1) With FBD instructions, you can only use an address in the L memory area when
you declare it as VAR_TEMP in the variable declaration table.

C79000-G7076-C566-01 2-5
2.2 Boolean Logic and Truth Tables
Boolean Logic The FBD programming language is based on the binary logic of Boolean
algebra in which variables can adopt the values “true” (1) or “false” (0).
Each logic instruction checks the signal state of a variable for 1 (true,
satisfied) or 0 (false, not satisfied) and then produces a result. The instruction
then either saves the result or uses it to perform a Boolean logic operation.
The result of the logic operation is known as the RLO.
To represent the logic, the logic boxes known from Boolean algebra are used.
The results of the logic instructions for all possible combinations of logical
variables are listed in truth tables.
The rules of Boolean logic are illustrated below based on the AND, OR, and
exclusive OR logic operations.
AND Logic In an AND logic operation, the signal states of two or more specified
Operation addresses are checked. If the signal state of the address is 1 the condition is
satisfied and the instruction produces the result 1. If the signal state of the
address is 0, the condition is not satisfied and the operation produces the
result 0.
Figure 2-1 illustrates an AND logic operation in the FBD programming
language.
& The condition is satisfied when the

I1.0 Q4.0 signal state is 1 at inputs I1.0 AND
= I1.1.
I1.1
Figure 2-1 AND Logic Operation in FBD
The possible results of an AND logic operation can be represented in a truth

table. Here, 1 means “satisfied” and 0 means “not satisfied”. The possible
logic instructions and their results are shown in Table 2-7.
Table 2-7 AND Truth Table

If the result of the signal and the result of the signal the result of the logic instruc-
state check at address I1.0 state check at address I1.1 tion is as follows:
is as below is as below
1 1 1
0 1 0
1 0 0
0 0 0

2-6 C79000-G7076-C566-01
OR Logic In an OR logic operation, the signal states of two or more specified addresses
Operation are checked. If the signal state of one of the addresses is 1, the condition is
satisfied and the instruction provides the result 1. If the signal state of all
addresses is 0, the condition is not satisfied and the instruction produces the
result 0.
Figure 2-2 shows an OR logic operation in the FBD programming language.
>=1 The condition is satisfied when the

I1.0 Q4.0 signal state is 1 at inputs I1.0 OR
= I1.1.
I1.1
Figure 2-2 OR Logic Operation in FBD
The possible results of an OR logic operation can be shown in a truth table.

Here, 1 means “satisfied” and 0 means “not satisfied”. The possible logic
operations and their results are shown in Table 2-8.
Table 2-8 OR Truth Table
If the result of the sig- and the result of the the result of the logic instruction
nal state check at ad- signal state check at is as follows:
dress I1.0 is as below address I1.1 is as below
1 0 1
0 1 1
1 1 1
0 0 0
Exclusive OR In an exclusive OR logic operation, the signal states of two or more specified
Logic Operation addresses are checked. If the signal state of one of the addresses is 1 the
condition is satisfied and the instruction provides the result 1. If the signal
state of all addresses is 0 or 1, the condition is not satisfied and the
instruction produces the result 0.
Figure 2-3 shows an exclusive OR logic operation in the FBD programming
language.
XOR The condition is satisfied when the

I1.0 Q4.0 signal state is 1 at input I1.0 OR at
= input I1.1 exclusively (i.e. not at
I1.1
both).
Figure 2-3 Exclusive OR Logic Operation in FBD

C79000-G7076-C566-01 2-7
The possible results of an exclusive OR logic operation can be represented in

a truth table. Here, 1 means “satisfied” and 0 means “not satisfied”. The
possible logic operations and their results are shown in Table 2-9.
Table 2-9 Exclusive OR Truth Table
If the result of the and the result of the the result of the logic instruction
signal state check at signal state check at is as follows:
address I1.0 is as below address I1.1 is as below
1 0 1
0 1 1
1 1 0
0 0 0

2-8 C79000-G7076-C566-01
2.3 Significance of the CPU Registers in Statements
Explanation Registers help the CPU perform logic, math, shift, or conversion instructions.
These registers are described below.
Accumulators The accumulators are general-purpose registers that you use to process bytes,
words, and double-words. The accumulators are 32-bits wide.
31 24 23 16 15 8 7 0
High byte Low byte High byte Low byte
High word Low word

Accumulator (1 or 2)
Figure 2-4 Areas of an Accumulator
Status Word The status word contains bits that you can reference in the address of bit
logic instructions. The following sections explain the significance of bits
0 through 8.
215... ...29 28 27 26 25 24 23 22 21 20
BR CC1 CC0 OV OS OR STA RLO FC
Figure 2-5 Structure of the Status Word
Changes in the Value Meaning

Bits of the Status 0 Sets the signal state to 0
Word
1 Sets the signal state to 1
x Changes the state
– State remains unchanged

C79000-G7076-C566-01 2-9
First Check Bit 0 of the status word is called the first-check bit (FC bit, see Figure 2-5).
At the start of an FBD network, the signal state of the FC bit is always 0,
unless the previous network ended with the SAVE box
Each logic instruction checks the signal state of the FC bit as well as the
signal state of the contact that the instruction addresses. The signal state of
the FC bit determines the sequence of a logic string. If the FC bit is 0 (at the
start of an FBD network), the instruction stores the result in the result of
logic operation bit (RLO) of the status word and sets the FC bit to 1. This is
known as the first check. The 1 or 0 that is set in the RLO bit after the first
check is then referred to as the result of first check.
If the signal state of the FC bit is 1, an instruction then combines the result of
its signal state check at the addressed contact with the RLO formed at the
addressed contact after the first check, and sets the result in the RLO bit.
A logic string made up of FBD instructions always ends with an output
instruction (for example set output, reset output, assign) or with a jump
instruction dependent on the result of the logic operation (RLO). These
instructions reset the FC bit to 0.
Result of Logic Bit 1 of the status word is called the result of logic operation bit (RLO bit,
Operation see Figure 2-5). This bit stores the result of a string of logic instructions or
compare instructions. The signal state of the RLO bit provides information
about signal flow.
The first instruction in an FBD network checks the signal state of an address
and produces a result of 1 or 0. The instruction enters the result of this signal
state in the RLO bit. The second instruction in a string of logic operations
also checks the signal state of an address and produces a result. The
instruction now combines this result with the value of the RLO bit of the
status word according to the rules of Boolean logic (see First Check above).
The result of the logic operation is entered in the RLO bit of the status word
and replaces the previous value in the RLO bit. Each subsequent instruction
in the string of logic operations combines two values: the result of the signal
check at the specified address and the current RLO.
You can, for example, assign the state of a bit memory location to the RLO
during a first check using a Boolean logic operation or trigger a jump
instruction.

2-10 C79000-G7076-C566-01
Status Bit Bit 2 of the status word is called the status bit (STA bit, see Figure 2-5). The
status bit stores the value of a bit that is referenced. The status of a logic
instruction that reads memory is always the same as the value of the bit that
this instruction checks (the bit on which it performs its logic operation). The
status of a bit instruction that writes to memory (Set Output, Reset Output, or
Assign) is the same as the value of the bit to which the instruction writes. If
no writing takes place, the value is the same as the value of the bit that the
instruction references. The status bit has no significance for bit instructions
that do not access memory. These instructions set the status bit to 1 (STA=1).
The status bit is not checked by an instruction. It is interpreted during
program test (program status) only.
OR Bit Bit 3 of the status word is called the OR bit (see Figure 2-5). The OR bit is
required to execute an AND before OR logic operation. An AND logic
operation can contain the instructions AND input and AND NOT input. The
OR bit indicates to the instructions that a previously executed AND logic
operation produced the value 1 so that the result of the OR logic operation
has already been determined. Any other bit-processing instruction resets the
OR bit.
Overflow Bit Bit 5 of the status word is called the overflow bit (OV bit, see Figure 2-5).
The OV bit indicates an error. It is set by a math instruction or a compare
floating-point numbers instruction after an error has occurred (overflow,
illegal instruction, illegal floating-point number). The bit is set or reset
according to the result of the math or compare instruction (error).
Stored Overflow Bit 4 of the status word is called the store overflow bit (OS bit, see Figure
Bit 2-5). The OS bit is set together with the OV bit when an error occurs. Since
the OS bit is unchanged when math instructions are executed without errors
(in contrast to the OV bit), this indicates whether or not an error occurred in
one of the previously executed instructions. The following instructions reset
the OS bit: JOS (jump if stored overflow bit = 1, must be programmed in
STL), block calls and block end statements.
CC1 and CC0 Bits 7 and 6 of the status word are called condition code 1 and condition
code 0 (CC1 and CC0, see Figure 2-5). The CC1 and CC0 bits provide
information about the following results or bits:
Result of a math instruction
Result of a compare instruction
Result of a digital instruction
Bits that have been shifted out of the address by a shift or rotate
instruction.
Tables 2-10 to 2-15 list the meaning of CC1 and CC0 after your program has
executed certain instructions.

C79000-G7076-C566-01 2-11
Table 2-10 CC1 and CC0 after Math Instructions, without Overflow
CC1 CC0 Explanation

0 0 Result = 0
0 1 Result < 0
1 0 Result > 0
Table 2-11 CC1 and CC0 after Integer Math Instructions, with Overflow
CC1 CC0 Explanation

0 0 Negative range overflow in Add Integer and Add Double Integer
Negative range overflow in Multiply Integer and Multiply
Double Integer
0 1 Positive range overflow in Add Integer, Subtract Integer, Add
Double Integer, Subtract Double Integer, Twos Complement
Integer, and Twos Complement Double Integer
Positive range overflow in Multiply Integer and Multiply Double
Integer, Divide Integer, and Divide Double Integer
1 0
Negative range overflow in Add Integer, Subtract Integer, Add
Double Integer, and Subtract Double Integer
Division by 0 in Divide Integer, Divide Double Integer, and
1 1
Return Fraction Double Integer
Table 2-12 CC1 and CC0 after Floating-Point Math Instructions, with Overflow
CC1 CC0 Explanation

0 0 Gradual underflow
0 1 Negative range overflow
1 0 Positive range overflow
1 1 Not a valid floating-point number

2-12 C79000-G7076-C566-01
Table 2-13 CC1 and CC0 after Comparison Instructions
CC1 CC0 Explanation

0 0 IN2 = IN1
0 1 IN2 < IN1
1 0 IN2 > IN1
1 1 IN1 or IN2 is not a valid floating-point number
Table 2-14 CC1 and CC0 after Shift and Rotate Instructions
CC1 CC0 Explanation

0 0 Bit shifted out last = 0
1 0 Bit shifted out last = 1
Table 2-15 CC1 and CC0 after Word Logic Instructions
CC1 CC0 Explanation

0 0 Result = 0
1 0 Result <> 0
Binary Result Bit Bit 8 of the status word is called the binary result bit (BR bit, see Figure 2-5).
The BR bit forms a link between the processing of bits and words. This bit is
an efficient method with which you can interpret the result of a word
instruction as a binary result and include this result in a binary string of logic
operations. The BR bit represents an internal memory bit in which the RLO
can be saved prior to a word instruction that changes the RLO so that the old
RLO is available again after the operation when the interrupted series of bit
instructions is resumed.
With the BR bit, you can, for example, program a function block (FB) or a
function (FC) in Statement List (STL) and call the FB or FC in FBD.
If you write a function block or a function that you want to call in FBD,
regardless of whether you write the FB or FC in STL or FBD, you must take
into account the BR bit. The BR bit corresponds to the Enable output (ENO)
of an FBD box. You save the RLO in the BR bit using the SAVE instruction
(in STL) or with the SAVE FBD box according to the following criteria:
Save an RLO of 1 in the BR bit when the FB or FC is processed without
errors.
Save an RLO of 0 in the BR bit if an error occurs during the processing of
an FB or FC.
Program these instructions at the end of the FB or FC so that they are the last
instructions executed in the block.

C79000-G7076-C566-01 2-13
Warning
! The BR bit can be reset to 0 unintentionally.
When you write FBs or FCs in FBD and do not handle the BR bit as
described above, an FB or FC might overwrite the BR bit of another FB or
FC.
To avoid this problem, save the RLO at the end of each FB or FC as
described above.
Meaning of The Enable input (EN) and Enable output (ENO) parameters of an FBD box
EN/ENO function as explained below:
If EN is not activated (its signal state is 0), the box does not execute its
function and ENO is not activated (it also has a signal state of 0).
If EN is activated (its signal state is 1) and the box executes its function
without errors, ENO is also activated (its signal state is also 1).
If EN is activated (its signal state is 1) and an error occurs while the
function is being executed, ENO is not activated (its signal state is 0).
When you call a system function block (SFB) or a system function (SFC) in
your program, the SFB or SFC indicates whether or not the CPU executed the
function without errors by setting the signal state of the BR bit:
If an error occurred during execution, the BR bit is set to 0.
If the function was executed without errors, the BR bit is 1.

2-14 C79000-G7076-C566-01
Addressing 3
Overview 3.1 Overview 3-2
3.2 Types of Addresses 3-4

C79000-G7076-C566-01 3-1
Addressing
3.1 Overview
What is Many FBD instructions operate with one or more addresses. The address
Addressing? specifies a constant or a location at which the instruction finds a variable
which it uses to perform a logic operation. This location can be a bit, byte,
word, or double word.
Examples of possible addresses are as follows:
A constant, the value of a timer or counter, or an ASCII character string
A bit in the status word of the programmable controller
A data block and a location within the data block area
Immediate and The following types of addressing are available:

Direct Addressing
Immediate addressing (specifying a constant as the address)
Direct addressing (specifying a variable as the address)
Figure 3-1 shows an example of immediate and direct addressing.
The function of the box is to compare two input parameters (in this case, two
16-bit integers) to see if the first input is less than or equal to the second. The
constant 50 is entered as input parameter IN1. Memory word MW200, a
location in memory, is entered as input parameter IN2.
Because the constant 50 in the example is the actual value with which IN1 of
the box will work, 50 is an immediate address of the instruction box. Because
MW200 points to a location in memory where there is another value with
which IN2 of the box will work, MW200 is a direct address. MW200 is a
location, not the actual value itself.
CMP
<= I
50 IN1
MW200 IN2
Figure 3-1 Immediate and Direct Addressing

3-2 C79000-G7076-C566-01
Addressing
Table 3-1 Constant Formats for Immediate Addressing Using Addresses of Elementary Data Types
Type and Size in Format Options Range and Number Notation Example
Description Bits (Lowest Value to Highest Value)
BOOL 1 Boolean Text TRUE/FALSE TRUE
(Bit)
BYTE 8 Hexadecimal B#16#0 to B#16#FF B#16#10
(Byte) byte#16#10
WORD 16 Binary 2#0 to 2#0001_0000_0000_0000
(Word) 2#1111_1111_1111_1111
Hexadecimal W#16#0 to W#16#FFFF W#16#1000
word16#1000
BCD C#0 to C#999 C#998
Unsigned decimal B#(0,0) to B#(255,255) B#(10,20)
byte#(10,20)
DWORD 32 Binary 2#0 to 2#1000_0001_0001_1000_
(Double 2#1111_1111_1111_1111_ 1011_1011_0111_1111
word) 1111_1111_1111_1111
Hexadecimal DW#16#0000_0000 to DW#16#00A2_1234
Unsigned decimal DW#16#FFFF_FFFF dword#16#00A2_1234
B#(0,0,0,0) to B#(1,14,100,120)
B#(255,255,255,255) byte#(1,14,100,120)
INT 16 Signed decimal -32768 to 32767 1
(Integer)
DINT 32 Signed decimal L#-2147483648 to L#2147483647 L#1
(Double
integer)
REAL 32 IEEE Upper limit: ±3.402823e+38 1.234567e+13
(Floating floating point Lower limit: ±1.175495e-38 )
point)
S5TIME 16 S5 Time in S5T#0H_0M_0S_10MS to S5T#0H_1M_0S_0MS
(SIMATIC 10-ms units (as S5T#2H_46M_30S_0MS and S5TIME#0H_1M_0S_0MS
time) default value) S5T#0H_0M_0S_0MS
TIME 32 IEC time in 1-ms T#-24D_20H_31M_23S_648MS to T#0D_1H_1M_0S_0MS
(IEC time) units, signed T#24D_20H_31M_23S_647MS TIME#0D_1H_1M_0S_0MS
integer
DATE 16 IEC date D#1990-1-1 to D#1994-3-15
(IEC date) in 1-day units D#2168-12-31 DATE#1994-3-15
TIME_OF_ 32 Time of day in TOD#0:0:0.0 to TOD#1:10:3.3
DAY 1-ms units TOD#23:59:59.999 TIME_OF_DAY#1:10:3.3
(Time of
day)
CHAR 8 Character ’A’,’B’, etc. ’E’
(Character)

C79000-G7076-C566-01 3-3
Addressing
3.2 Types of Addresses
Possible One of the following elements can be used as the address of an FBD
Addresses instruction:
A bit whose signal state will be checked
A bit to which the signal state of the logic operation string will be
assigned
A bit to which the result of logic operation (RLO) will be assigned
A bit that will be set or reset
A number that indicates a counter that will be incremented or
decremented
A number that indicates a timer to be used
An edge memory bit that saves the previous RLO
An edge memory bit that saves the previous signal state of a different
address
A byte, word, or double word containing a value with which the FBD
element or box will work
The number of a data block (DB or DI) that will be opened or created
The number of a function (FC), system function (SFC), a function block
(FB), or system function block (SFB) that will be called
A label as the destination for a jump
Address Identifiers Variables as addresses consist of an address identifier and an address within
the memory area indicated by the address identifier. An address identifier can
be one of the following two basic types:
An address identifier that indicates the following two data objects:
– The memory area in which the instruction finds a value (data object)
with which it can perform a logic operation (for example “I” for
process input image, see Table 2-5).
– The size of a value (data object) with which the instruction will
perform a logic operation (for example B for “Byte”, W for “Word”
and D for “Double Word”, see Table 2-5).
An address identifier that indicates a memory area but not the size of the
data object in the area (for example an identifier for the T area (timers), C
(counters), or DB or DI (data block) and the number of the timer, counter,
or data block, see Table 2-5).

3-4 C79000-G7076-C566-01
Addressing
Pointers A pointer identifies the location of a variable. A pointer contains an address

instead of a value. When assigning an actual parameter for the parameter
type “Pointer”, you provide the memory address. With STEP 7, you can enter
the pointer either in the pointer format or simply as an address (for example
M 50.0). The following example illustrates the pointer format for accessing
data starting at M 50.0.
P#M50.0
Working with If you are working with an instruction whose address identifier indicates a
Words or Double memory area of your programmable controller and a data object that is either
Words as the Data a word or double word in size, remember that the memory location is always
Object referenced as a byte address. This byte address is the smallest byte number or
the number of the high byte within the word or double word. The address in
the instruction shown in Figure 3-2, for example, references four successive
bytes in the memory area M starting at byte 10 (MB10) through to byte 13
(MB13).
Instruction: L MD10
Address identifier Byte address
Figure 3-2 Example of a Memory Location Referenced as a Byte Address
Figure 3-3 shows data objects with the following sizes:

Double word: memory double word MD10
Word: memory word MW10, MW11 and MW12
Byte: memory bytes MB10, MB11, MB12 and MB13
If you use absolute addresses that are a word or double word long, make sure
that you avoid any overlapping byte assignments.
MW10 MW12
MB10 MB11 MB12 MB13
MW11
MD10
Figure 3-3 Referencing a Memory Location as a Byte Address

C79000-G7076-C566-01 3-5
Addressing

3-6 C79000-G7076-C566-01
Bit Logic Instructions 4
4.2 AND Logic Operation 4-3
4.3 OR Logic Operation 4-4
4.4 AND-before-OR Logic Operation and OR-before-AND 4-5
Logic Operation
4.5 Exclusive OR Logic Operation 4-6
4.6 Insert Binary Input 4-7
4.7 Negate Binary Input 4-8
4.8 Assign 4-9
4.9 Midline Output 4-10
4.10 Save RLO to BR Memory 4-11
4.11 Set Output 4-12
4.12 Reset Output 4-13
4.13 Set Counter Value 4-14
4.14 Up Counter Instruction 4-16
4.15 Down Counter Instruction 4-17
4.16 Pulse Timer Instruction 4-18
4.17 Extended Pulse Timer Instruction 4-20
4.18 On-Delay Timer Instruction 4-22
4.19 Retentive On-Delay Timer Instruction 4-24
4.20 Off-Delay Timer Instruction 4-26
4.21 Positive RLO Edge Detection 4-28
4.22 Negative RLO Edge Detection 4-29
4.23 Address Positive Edge Detection 4-30
4.24 Address Negative Edge Detection 4-31
4.25 Set_Reset Flip Flop 4-32
4.26 Reset_Set Flip Flop 4-33

C79000-G7076-C566-01 4-1
Bit Logic Instructions
4.1 Overview
Explanation Bit logic instructions work with two digits, 1 and 0. These two digits form
the base of a number system called the binary system. The two digits 1 and 0
are called binary digits or simply bits. In conjunction with AND, OR, XOR
and outputs, a 1 stands for logical YES and a 0 for logical NO.
The bit logic instructions interpret the signal states 1 and 0 and combine
them according to the rules of Boolean logic. These combinations produce a
result of 1 or 0 known as the result of logic operation (RLO, see Section 2.2).
The logic operations triggered by the bit logic instructions execute a variety
of functions.
Functions Bit logic instructions are available for the following functions:
AND, OR, and XOR: these instructions check the signal state and
produce a result that is either copied to the RLO bit or combined with it.
With AND logic operations, the result of the signal state check is
combined according to the AND truth table (see Table 2-7). With OR
logic operations, the result of the signal state check is combined
according to the OR truth table (see Table 2-8), with exclusive OR logic
operations, according to the exclusive OR truth table (see Table 2-9).
Assign and Midline Output: these instructions assign the RLO or store it
temporarily.
The following instructions react to an RLO of 1:
– Set Output and Reset Output
– Set_Reset Flip Flop and Reset_Set Flip Flop
Some instructions react to a rising or falling edge so that you can execute
the following functions:
– Increment or decrement the value of a counter
– Start a timer
– Produce an output of 1
The remaining instructions affect the RLO directly in the following ways:
– Negate the RLO
– Save the RLO in the binary result bit of the status word
In this chapter, the counter and timer instructions are shown in the
international and SIMATIC forms.

4-2 C79000-G7076-C566-01
4.2 AND Logic Operation
Description With the AND instruction, you can check the signal states of two or more
specified addresses at the inputs of an AND box.
If the signal state of all addresses is 1, the condition is satisfied and the
instruction provides the result 1. If the signal state of an address is 0, the
condition is not satisfied and the instruction produces the result 0.
If the AND instruction is the first instruction in a string of logic operations, it
saves the result of its signal state check in the RLO bit.
Every AND instruction that is not the first instruction in the string of logic
operations, combines the result of its signal state check with the value stored
in the RLO bit. These values are combined according to the AND truth table.
Table 4-1 AND Box and Parameters
FBD Box Parameters Data Type Memory Area Description

<address> BOOL I, Q, M, T, C, D, L The address indicates the bit whose
<address> & TIMER signal state will be checked.
<address>
COUNTER
&
I0.0 Q4.0
Output Q4.0 is set when the signal state is 1 at input
I0.1 = I0.0 AND I0.1.
Status Word Bits

writes – – – – – x x x 1
Figure 4-1 AND Logic Operation

C79000-G7076-C566-01 4-3
4.3 OR Logic Operation
Description With the OR instruction, you can check the signal states of two or more
specified addresses at the inputs of an OR box.
If the signal state of one of the addresses is 1, the condition is satisfied and
the instruction produces the result 1. If the signal state of all addresses is 0,
the condition is not satisfied and the instruction produces the result 0.
If the OR instruction is the first instruction in a string of logic operations, it
saves the result of its signal state check in the RLO bit.
Each OR instruction that is not the first instruction in the string of logic
operations combines the result of its signal state check with the value stored
in the RLO bit. These values are combined according to the OR truth table.
Table 4-2 OR Box and Parameters

<address> BOOL I, Q, M, T, C, D, L The address specifies the bit whose
<address> >=1 TIMER signal state will be checked
<address> COUNTER
I0.0 >=1
Q4.0 Output Q4.0 is set when the signal state is 1 at input I0.0 OR at input
I0.1 = I0.1.
Status Word Bits

writes – – – – – x x x 1
Figure 4-2 OR Logic Operation

4-4 C79000-G7076-C566-01
4.4 AND-before-OR Logic Operation and OR-before-AND Logic

Operation
Description With the AND-before-OR instruction, you can check the result of a signal
state according to the OR truth table.
With an AND-before-OR logic operation the signal state is 1 when at least
one AND logic operation is satisfied.
I0.0 &
The signal state is 1 at output Q3.1 when
I0.1 >=1 at least one AND logic operation is satisfied.
& The signal state is 0 at output Q3.1 when

I0.2
Q3.1 no AND logic operation is satisfied.
I0.3 =
Status Word Bits

writes – – – – – x x x 1
Figure 4-3 AND-before-OR Logic Operation
Description With the OR-before-AND instruction, you can check the result of a signal
state check according to the AND truth table.
With an OR-before-AND logic operation the signal state is 1 when all OR
logic operations are satisfied.
I1.0 >=1
The signal state is 1 at output Q3.1 when
I1.1 & both OR logic operations are satisfied.
>=1 The signal state is 0 at output Q3.1 when

I1.2
Q3.1 at least one OR logic operation is not satisfied.
I1.3 =
Status Word Bits

writes – – – – – x x x 1
Figure 4-4 OR-before-AND Logic Operation

C79000-G7076-C566-01 4-5
4.5 Exclusive OR Logic Operation
Description With the Exclusive OR instruction, you can check the result of a signal state
check according to the Exclusive OR truth table.
With an Exclusive OR logic operation, the signal state is 1 when the signal
state of one of the two specified addresses is 1.
Table 4-3 Exclusive OR Box and Parameters

<address> XOR TIMER signal state will be checked.
<address> COUNTER
XOR The signal state is 1 at output Q3.1 when the signal state is 1 at
I0.0 Q3.1 either input I0.0 OR at input I0.2 (exclusively, in other
I0.2 = words not at both).
Status Word Bits

writes – – – – – x x x 1
Figure 4-5 Exclusive OR Logic Operation

4-6 C79000-G7076-C566-01
4.6 Insert Binary Input
Description The Insert Binary Input instruction inserts a further binary input to an AND,
OR, or XOR box.
Table 4-4 Binary Input Element and Parameters
FBD Element Parameters Data Type Memory Area Description

<address> TIMER signal state will be checked
COUNTER
I1.0 & Output Q4.0 is 1 when the signal state at

I1.1 Q4.0 I1.0 AND I1.1 AND I1.2 is 1.
I1.2 =
Status Word Bits

writes – – – – – – 1 x –
Figure 4-6 Insert Binary Input

C79000-G7076-C566-01 4-7
4.7 Negate Binary Input
Description The Negate Binary Input instruction negates the RLO.

When you negate the result of logic operation, you must remember certain
rules:
If the result of logic operation at the first input of an AND or OR box is
negated, there is no nesting.
If the result of logic operation is negated but not at the first input of an
OR box, the entire binary logic operation before the input is included in
the OR logic operation.
If the result of logic operation is negated but not at the first input of a
AND box, the entire binary logic operation before the input is included in
the AND logic operation.
Table 4-5 Negate Binary Input Element
FBD Element Parameters Data Type Memory Area Description

None – – –
Output Q4.0 is 1 when:

I1.0 &
I1.1 the signal state at I1.0 AND I1.1 is NOT 1
&
AND the signal state at I1.2 AND I1.3 is NOT 1
I1.2 & OR the signal state at I1.4 is NOT 1.
I1.3 >=1
Q4.0
I1.4 =
Status Word Bits

writes – – – – – – 1 x –
Figure 4-7 Negate Binary Input

4-8 C79000-G7076-C566-01
4.8 Assign
Description The Assign instruction produces the result of logic operation. The box at the
end of a logic operation has the signal 1 or 0 according to the following
criteria:
The output has the signal 1 when the conditions of the logic operation
before the output box are satisfied
The output has the signal 0 when the conditions of the logic operation
before the output box are not satisfied.
The FBD logic operation assigns the signal state to the output that is
addressed by the instruction (to achieve the same effect, the signal state of
the RLO bit could also be assigned to the address). If the conditions of the
FBD logic operations are satisfied, the signal state at the output box is 1.
Otherwise the signal state is 0. The Assign instruction is influenced by the
Master Control Relay (MCR).
For more detailed information about the functions of the MCR, refer to
Section 16.4.
You can only place the Assign box at the right-hand end of the string of logic
operations. You can, however, use several Assign boxes.
You can create a negated assignment with the Negate Input instruction.
Table 4-6 Assign Box and Parameters

<address> BOOL I, Q, M, D, L The address specifies the bit to which
<address>
the signal state of the string of logic
= operations is assigned.
I0.0 & The signal state at output Q4.0 is 1 when the signal
state is 1 at inputs I0.0 AND I0.1, OR I0.2 is 0.
I0.1 >=1
Q4.0
I0.2 =
Status Word Bits

writes – – – – – 0 x – 0
Figure 4-8 Assign

C79000-G7076-C566-01 4-9
4.9 Midline Output
Description The Midline Output instruction is an intermediate element that buffers the
RLO. More precisely, this element buffers the bit logic operation of the last
branch to be opened before the Midline Output.
The Midline Output instruction is influenced by the Master Control Relay
(MCR). For more information about the MCR functions, see Section 16.4.
You can create a negated Midline Output by negating the input of the
Midline Output.
Table 4-7 Midline Output Box and Parameters

<address> <address> BOOL I, Q, M, D, L1 The address specifies the bit to
# which the RLO will be assigned.
1 With the Connector instruction you can only use an address in the L memory area if you declare the address in
VAR_TEMP; you cannot use the L memory area for absolute addresses.
I1.0 & M0.0

I1.1 # &
I1.2 & M1.1

I1.3 # >=1
M2.2 DB5.DBX3.2 Q4.0

I1.4 # # =
The Midline Outputs buffer the following results of the logic operations:
M0.0 buffers the negated I1.0 & M1.1 the negated I1.2 &
RLO of I1.1 RLO of I1.3
DB5.DBX3.2 the negated RLO of the entire

M2.2 the RLO of I1.4 # bit logic operation in bit 2 of the 3rd bytes in DB 5.
Status Word Bits

writes – – – – – 0 x – 1
Figure 4-9 Midline Output

4-10 C79000-G7076-C566-01
4.10 Save RLO to BR Memory
Description The Save RLO to BR Memory instruction saves the RLO in the BR bit of the
status word. The first check bit FC is not reset.
For this reason, if there is an AND logic operation in the next network, the
state of the BR bit is included in the logic operation.
Using the “Save RLO to BR Memory” instruction in conjunction with
checking the BR bit in the same block or on subordinate blocks is not
recommended, because the BR bit can be modified by many instructions
occurring inbetween. It is advisable to use the SAVE instruction before
exiting a block, since the ENO output (=BR bit) is then set to the value of the
RLO bit and you can then check for errors in the block.
With the “Save RLO to BR Memory” instruction, the RLO of a network can
form part of a logic operation in a subordinate block. The CALL instruction
in the calling block resets the first check bit.
Table 4-8 Save RLO to BR Memory Box and Parameters
SAVE None – – –
I1.2 & The result of logic operation (RLO) is written to the BR bit.
I1.3 SAVE
Status Word Bits

writes x – – – – – – – –
Figure 4-10 Save RLO to BR Memory

C79000-G7076-C566-01 4-11
4.11 Set Output
Description The Set Output instruction is only executed when the RLO is 1. If the RLO is
1, this instruction sets the specified address to 1. If the RLO is 0, the
instruction does not affect the specified address which remains unchanged.
The Set Output instruction is influenced by the Master Control Relay (MCR).
For more detailed information about the MCR, refer to Section 16.4.
Table 4-9 Set Output Box and Parameters
<address> <address> BOOL I, Q, M, D, L The address specifies which bit will

be set.
S
The signal state at output Q4.0 is set to 1 only when:
I0.0 & The signal state is 1 at inputs I0.0 AND I0.1

I0.1 >=1 Q4.0
OR the signal state at input I0.2 is 0.
I0.2 S If the RLO of the branch is 0, the signal state of Q4.0 is
not changed.
Status Word Bits

writes – – – – – 0 x – 0
Figure 4-11 Set Output

4-12 C79000-G7076-C566-01
4.12 Reset Output
Description The Reset Output instruction is only executed when the RLO is 1. If the RLO
is 1, this instruction resets the specified address to 0. If the RLO is 0, the
instruction does not affect the specified address which remains unchanged.
The Reset Output instruction is influenced by the Master Control Relay
(MCR). For more detailed information about the MCR, refer to Section 16.4.
Table 4-10 Reset Output Box and Parameters

<address> <address> BOOL I, Q, M, T, C, D, L The address specifies which bit will
TIMER be reset.
R
COUNTER
The signal state at output Q4.0 is reset to 0 only when:

I0.0 & The signal state is 1 at inputs I0.0 AND I0.1
I0.1 >=1 Q4.0 OR the signal state at input I0.2 is 0.
I0.2 R If the RLO of the branch is 0, the signal state at output
Q4.0 is unchanged.
Status Word Bits

writes – – – – – 0 x – 0
Figure 4-12 Reset Output

C79000-G7076-C566-01 4-13
4.13 Set Counter Value
Description With the Set Counter Value instruction, you assign a default value to the
counter you have specified. This instruction is executed only when there is a
rising edge at the RLO (change from 0 to 1 in the RLO).
You can only place the Set Counter Value box at the right-hand end of the
string of logic operations. You can, however, use several Set Counter Value
boxes.
Table 4-11 Set Counter Value Box and Parameters, with SIMATIC Mnemonics
FBD Box Parameters Data Type Memory Description

Area
Counter COUNTER Z Address1 specifies the number of the
<address1> number counter that will be assigned a preset
SZ value.
ZW WORD E, A, M, D, L The value that is preset (address2)
or constant can be in the range between 0 and
<address2> ZW 999. If you enter a constant, the
characters, C# must precede the
value indicating the BCD format, for
example C#100.
Table 4-12 Set Counter Value Box and Parameters with International Mnemonics

Area
Counter COUNTER C Address1 specifies the number of the
<address1> number counter that will be assigned a preset
SC value.
CV WORD I, Q, M, D, L The value that is preset (address2)
or constant can be in the range between 0 and
<address2> CV 999. If you enter a constant, the
characters, C# must precede the
value indicating the BCD format, for
example C#100.

4-14 C79000-G7076-C566-01
C5 The counter C5 has the value 100 preset when the signal
SC state of I0.0 changes from 0 to 1 (rising edge in the RLO).
C# specifies that you are entering a value in BCD format.
I0.0
If there is no rising edge, the value of counter C5 is not
C#100 CV changed.
Status Word Bits

writes – – – – – 0 – – 0
Figure 4-13 Set Counter Value

C79000-G7076-C566-01 4-15
4.14 Up Counter Instruction
Description The Up Counter instruction increments the value of a specified counter by 1

when there is a rising edge at the RLO (change from 0 to 1) and the value of
the counter is less than 999. If there is no rising edge at the RLO, or the
counter has already reached the value 999, it is not incremented.
The Set Counter Value instruction sets the value of the counter (see
Section 4.13).
You can only place the Up Counter box at the right-hand end of the string of
logic operations. You can, however, use several Up Counter boxes.
Table 4-13 Up Counter Boxes and Parameters with SIMATIC and International Mnemonics
FBD Boxes Parameters Data Type Memory Area Description

<address> Counter COUNTER Z The address specifies the number of
ZV number the counter that will be incremented.
<address>
C
CU
C10 If the signal state of I0.0 changes from 0 to 1 (rising edge

CU in the RLO), the value of the counter C10 is incremented
by 1 (unless the value of C10 is 999).
I0.0
If there is no rising edge, the value of C10 remains
unchanged.
Status Word Bits

writes – – – – – 0 – – 0
Figure 4-14 Up Counter

4-16 C79000-G7076-C566-01
4.15 Down Counter Instruction
Description The Down Counter instruction decrements the value of a specified counter by
1 when there is a rising edge at the RLO (change from 0 to 1) and the value
of the counter is higher than 0. If there is no rising edge at the RLO, or if the
counter has already reached the value 0, the value of the counter is not
decremented.
The Set Counter Value instruction sets the value of the counter (see
Section 4.13).
You can only place the Down Counter box at the right-hand end of the string
of logic operations. You can, however, use more than one Down Counter
boxes.
Table 4-14 Down Counter Boxes and Parameters with SIMATIC and International Mnemonics
FBD Boxes Parameters Data Type Memory Area Description

<address> Counter COUNTER Z The address specifies the number of
ZR number the counter to be decremented.
<address>
C
CD
If the signal state of input I0.0 changes from 0 to 1 (rising

C10 edge at the RLO), the value of counter C10 is decremented
CD by 1 (unless the value of C10 is already 0).
I0.0 If there is no rising edge, the value of C10 is not changed.
Status Word Bits

writes – – – – – 0 – – 0
Figure 4-15 Down Counter

C79000-G7076-C566-01 4-17
4.16 Pulse Timer Instruction
Description The Pulse Timer instruction starts a timer with a specified value when there
is a rising edge at the RLO (change from 0 to 1). As long as the RLO is
positive, the timer continues to run for the specified time. A signal state
check for 1 produces 1 as long as the timer is running. If the RLO changes
from 1 to 0 before the time has expired, the timer is stopped. In this case, a
signal state check for 1 produces a result of 0.
The time units used for timers are d (days), h (hours), m (minutes), s
(seconds) and ms (milliseconds).
For more detailed information about the memory area and the components of
a timer, refer to Section 5.1.
You can only place the Pulse Timer box at the right-hand end of the string of
logic operations. You can, however, use more than one Pulse Timer box.
Table 4-15 Pulse Timer Box and Parameters with SIMATIC Mnemonics

<address> Timer TIMER T The address specifies the
SI number number of the timer to be
started.
<time TW S5TIME E, A, M, D, L or Time value (S5TIME format)

TW constant
value>
Table 4-16 Pulse Timer Box and Parameters with International Mnemonics

SP number number of the timer to be
started.
<time TV S5TIME I, Q, M, D, L or Time value (S5TIME format)

value> TV constant

4-18 C79000-G7076-C566-01
Network 1: If the signal state of input I0.0 changes from 0 to 1 (rising edge at
T5 the RLO), timer T5 is started. As long as the signal state is 1, the
SP timer continues to run for the specified time of 2 seconds. If the
signal state at I0.0 changes from 1 to 0 before this time has
I0.0
expired, the timer is stopped.
As long as the timer is running, the signal state at output Q4.0 is 1.
S5T#2s TV
Examples of timer values:
S5T#2s = 2 seconds
Network 2:
Q4.0 S5T#12m_18s = 12 minutes and 18 seconds
T5 =
Status Word Bits

writes – – – – – 0 – – 0
Figure 4-16 Pulse Timer

C79000-G7076-C566-01 4-19
4.17 Extended Pulse Timer Instruction
Description The Extended Pulse Timer instruction starts a timer with a specified value if
there is a rising edge at the RLO (change from 0 to 1). The timer continues to
run for the specified time even if the RLO changes to 0 before this time has
expired. A signal state check for 1 produces 1 as long as the timer is running.
The timer is restarted with the specified time if the RLO changes from 0 to 1
while the timer is running.
For more detailed information about the memory area and the components of
a timer, refer to Section 5.1.
You can only place the Extended Pulse Timer box at the right-hand end of the
string of logic operations. You can, however, use more than one Extended
Pulse Timer box.
Table 4-17 Extended Pulse Timer Box and Parameters with SIMATIC Mnemonics

SV number number of the timer to be
started.

value> TW constant
Table 4-18 Extended Pulse Timer Box and Parameters with International Mnemonics

SE number number of the timer to be
started.

value> TV constant

4-20 C79000-G7076-C566-01
Network 1: If the signal state of input I0.0 changes from 0 to 1 (rising edge at
T5 the RLO), timer T5 is started. The timer continues to run without
SE being influenced by a falling edge at the RLO. If the signal state of
I0.0 input I0.0 changes from 0 to 1 before the specified time has
expired, the timer is retriggered.
S5T#2s TV
As long as the timer is running, the signal state at output Q4.0 is 1.

Network 2:
Q4.0
T5 =
Status Word Bits

writes – – – – – 0 – – 0
Figure 4-17 Extended Pulse Timer

C79000-G7076-C566-01 4-21
4.18 On-Delay Timer Instruction
Description The On-Delay Timer instruction starts a specified timer when there is a rising
edge at the RLO (change from 0 to 1). A signal state check for 1 produces 1
when the specified time has expired without an error occurring and the RLO
is still 1. If the RLO changes from 1 to 0 while the timer is running, the timer
is stopped. In this case, a signal state check for 1 always produces the result
0.
For more detailed information about the address of a timer in memory and
the components of a timer, refer to Section 5.1.
You can only place the On-Delay Timer box at the right-hand end of the
string of logic operations. You can, however, use more than one On-Delay
Timer box.
Table 4-19 On-Delay Timer Box and Parameters with SIMATIC Mnemonics

SE number number of the timer to be
started.

TW constant
value>
Table 4-20 On-Delay Timer Box and Parameters with International Mnemonics

SD number number of the timer to be
started.

TV constant
value>

4-22 C79000-G7076-C566-01
Network 1:
T5 If the signal state of input I0.0 changes from 0 to 1
SD (rising edge at the RLO), timer T5 is started. When the
time expires, and the signal state is still 1, output Q4.0
I0.0
has the value 1. If the signal state changes from 1 to 0,
the timer is stopped.
S5T#2s TV
Network 2:
Q4.0
T5 =
Status Word Bits

writes – – – – – 0 – – 0
Figure 4-18 On-Delay Timer

C79000-G7076-C566-01 4-23
4.19 Retentive On-Delay Timer Instruction
Description The Retentive On-Delay Timer instruction starts the specified timer when
there is a rising edge at the RLO (change from 0 to 1). The timer continues to
run for the specified time if the RLO changes to 0 before the time has
expired. A signal state check for 1 produces the result 1 regardless of the
RLO if the time has expired. If the RLO changes from 0 to 1 while the timer
is running, the timer is restarted with the specified value.
Fore more detailed information about the address of a timer in memory and
You can only place the Retentive On-Delay Timer box at the right-hand end
of the string of logic operations. You can, however, use more than one
Retentive On-Delay Timer box.
Table 4-21 Retentive On-Delay Timer Box and Parameters with SIMATIC Mnemonics

number number of the timer to be
SS
started.

TW constant
value>
Table 4-22 On-Delay Timer Box and Parameters with International Mnemonics

SS number number of the timer to be
started.

TV constant
value>

4-24 C79000-G7076-C566-01
Network 1:
T5 If the signal state of input I0.0 changes from 0 to 1 (rising
edge at the RLO), timer T5 is started. The timer continues to
SS
run regardless of whether the signal state at I0.0 changes
I0.0 from 1 to 0. If the signal state changes from 0 to 1 before the
time has expired, the timer is retriggered.
S5T#2s TV Output Q4.0 has the value 1 when the time has expired.
Network 2:
Q4.0
T5 =
Status Word Bits

writes – – – – – 0 – – 0
Figure 4-19 Retentive On-Delay Timer

C79000-G7076-C566-01 4-25
4.20 Off-Delay Timer Instruction
Description The Off-Delay Timer instruction starts the specified timer when the RLO has
a falling edge (change from 1 to 0). A signal state check for 1 produces 1
when the RLO is 1 or when the timer is running. The timer is reset when the
RLO changes from 0 to 1 while the timer is running. The time is only
restarted when the RLO changes from 1 to 0.
For more detailed information about the address of a timer in memory and
You can only place the Off-Delay Timer box at the right-hand end of the
string of logic operations. You can, however, use more than one Off-Delay
Timer box.
Table 4-23 Off-Delay Timer Box and Parameters with SIMATIC Mnemonics

SA
started.

TW constant
value>
Table 4-24 Off-Delay Timer Box and Parameters with International Mnemonics

SF
started.

TV constant
value>

4-26 C79000-G7076-C566-01
Network 1:
T5 The timer is started when the signal state at I0.0 changes from
SF 1 to 0.
I0.0
S5T#2s
TV If the signal state changes from 0 to 1, the timer is reset.
The signal state at output Q4.0 is 1, when the signal state at

Network 2:
Q4.0 input I0.0 is 1 or the timer is running.
T5 =
Status Word Bits

writes – – – – – 0 – – 0
Figure 4-20 Off-Delay Timer

C79000-G7076-C566-01 4-27
4.21 Positive RLO Edge Detection
Description The Positive RLO Edge Detection instruction detects a change from 0 to 1
(rising edge) at the specified address and indicates this with an RLO of 1
after the instruction. The current signal state at the RLO is compared with the
signal state of the address (the edge memory bit). If the signal state of the
address is 0 and the RLO is 1 before the instruction, the RLO will be 1
(pulse) after the instruction, in all other cases the RLO is 0. The RLO prior to
the instruction is stored in the address.
Table 4-25 Positive RLO Edge Detection Box and Parameter

<address> <address> BOOL I, Q, M, D, L The address specifies which edge
memory bit will store the previous
P RLO.
I1.0 M0.0 The edge memory bit M3.3 stores the

&
P signal state of the previous RLO.
I1.1 &
M1.1
I1.2 &
N >=1
I1.3
M2.2 M3.3 Q4.0
&
I1.4 P N =
Status Word Bits

writes – – – – – 0 x x 1
Figure 4-21 Positive RLO Edge Detection

4-28 C79000-G7076-C566-01
4.22 Negative RLO Edge Detection
Description The Negative RLO Edge Detection instruction detects a change from 1 to 0
(falling edge) at the specified address and indicates this by setting the RLO to
1 after the instruction. The current signal state of the RLO is compared with
the signal state of the address (the edge memory bit). If the signal state of the
address is 1 and the RLO prior to the instruction was 0, the RLO is 1 (pulse)
after the instruction, in all other cases it is 0. The RLO prior to the instruction
is stored in the address.
Table 4-26 Negative RLO Edge Detection Box and Parameter

<address> <address> BOOL I, Q, M, D, L The address specifies which edge
memory bit will store the previous
N
RLO.
I1.0 M0.0
& The edge memory bit M3.3 stores the
I1.1 P & signal state of the previous RLO.
M1.1
I1.2 &
N >=1
I1.3
M2.2 M3.3 Q4.0
&
I1.4 P N =
Status Word Bits

writes – – – – – 0 x x 1
Figure 4-22 Negative RLO Edge Detection

C79000-G7076-C566-01 4-29
4.23 Address Positive Edge Detection
Description The Address Positive Edge Detection instruction compares the signal state of
<address1> with the signal state of the previous signal check that is stored in
the parameter M_BIT. If there has been a change from 0 to 1, output Q has
the value 1, in all other cases it has the value 0.
Table 4-27 Address Positive Edge Detection Box and Parameters

<address1> <address1> BOOL I, Q, M, D, L Signal to be checked for a positive
POS (rising) edge.
M_BIT BOOL Q, M, D The M_BIT address specifies the
edge memory bit used to store the
M_BIT Q previous signal state of POS. You
should only use the process image
input area I for the M_BIT when
no input module is already using
this address.
Q BOOL I, Q, M, D, L One-shot output.
I0.3
POS
there is a rising edge at input I0.3
AND the signal state is 1 at input I0.4.
&
M0.0 M_BIT Q
Q4.0
I0.4 =
Status Word Bits

writes x – – – – 0 1 x 1
Figure 4-23 Address Positive Edge Detection

4-30 C79000-G7076-C566-01
4.24 Address Negative Edge Detection
Description The Address Negative Edge Detection instruction compares the signal state of
<address1> with the signal state of the previous check that is stored in the
M_BIT parameter. If a change from 1 to 0 occurred, output Q has the value
1, in all other situations it has the value 0.
Table 4-28 Address Negative Edge Detection Box and Parameters

<address1> <address1> BOOL I, Q, M, D, L Signal to be checked for a
NEG negative (falling) edge
change.
M_BIT BOOL Q, M, D The M_BIT address
M_BIT Q specifies the edge memory
bit in which the previous
signal state of NEG is
stored. Only use the
process input image I
memory area for the
M_BIT when no input
module is already using
this address.
Q BOOL I, Q, M, D, L One-shot output.
I0.3
NEG
there is a falling edge at input I0.3
AND the signal state at input I0.4 is 1.
&
M0.0 M_BIT Q
Q4.0
I0.4 =
Status Word Bits

writes x – – – – 0 1 x 1
Figure 4-24 Address Negative Edge Detection

C79000-G7076-C566-01 4-31
4.25 Set_Reset Flip Flop
Description The Set_Reset Flip Flop instruction executes Set (S) or Reset (R) instructions
only when the RLO is 1. An RLO of 0 has no effect on these instructions, the
address specified in the instruction remains unchanged.
Set_Reset Flip Flop is set when the signal state at input S is 1 and the signal
state at input R is 0. If input S is 0 and input R is 1, the flip flop is reset. If
the RLO at both inputs is 1 the flip flop is reset.
The Set_Reset Flip Flop instruction is influenced by the Master Control
Relay (MCR). For more detailed information about how the MCR functions,
refer to Section 16.4.
Table 4-29 Set_Reset Flip Flop Box and Parameters

SR be set or reset.
S S BOOL I, Q, M, D, L, T, C Set instruction enabled

R BOOL I, Q, M, D, L, T, C Reset instruction enabled
R Q
Q BOOL I, Q, M, D, L Signal state of <address>
If I0.0 is 1 and I0.1 is 0, memory bit M0.0

M0.0 is set and Q4.0 is 1.
&
I0.0 SR If I0.0 is 0 and I0.1 is 1, the memory bit
I0.1 S M0.0 is reset and Q4.0 is 0.
If both signal state are 0, there is no
& Q4.0 change. If both signal states are 1, the
I0.0
R Q = reset instruction dominates due to the
I0.1
order of the instructions.
M0.0 is reset and Q 4.0 is 0.
Status Word Bits

writes – – – – – x x x 1
Figure 4-25 Set_Reset Flip Flop

4-32 C79000-G7076-C566-01
4.26 Reset_Set Flip Flop
Description The Reset_Set Flip Flop instruction executes instructions such as Set (S) or
Reset (R) only when the RLO is 1. An RLO of 0 does not affect these
instructions, the address specified in the instruction is not changed.
Reset_Set Flip Flop is reset when the signal state at input R is 1 and the
signal state at input S is 0. If input R is 0 and input S is 1, the flip flop is set.
If the RLO at both inputs is 1, the flip flop is set.
The Reset_Set Flip Flop instruction is affected by the Master Control Relay
(MCR). For more detailed information about the way in which the MCR
functions, refer to Section 16.4.
Table 4-30 Reset_Set Flip Flop Box and Parameters

RS be set or reset.
R
S BOOL I, Q, M, D, L, T, C Reset instruction enabled
S Q R BOOL I, Q, M, D, L, T, C Set instruction enabled
Q BOOL I, Q, M, D, L Signal state of <address>
If I0.0 is 1 and I0.1 is 0, the memory bit M0.0

M0.0 is reset and output Q4.0 is 0. If I0.0 is 0 and
& I0.1 is 1, the memory bit M0.0 is set and
I0.0 RS output Q4.0 is 1.
I0.1 R
& If both signal states are 0, there is no change.

Q4.0
I0.0 If both signal states are 1, the Set instruction
I0.1 S Q = dominates due to the order of the
instructions. M 0.0 is set and Q4.0 is 1.
Status Word Bits

writes – – – – – x x x 1
Figure 4-26 Reset_Set Flip Flop

C79000-G7076-C566-01 4-33

4-34 C79000-G7076-C566-01
Timer Instructions 5
Overview 5.1 Memory Areas and Components of a Timer 5-2
5.2 Choosing the Right Timer 5-4
5.3 Pulse S5 Timer 5-5
5.4 Extended Pulse S5 Timer 5-7
5.5 On-Delay S5 Timer 5-9
5.6 Retentive On-Delay S5 Timer 5-11
5.7 Off-Delay S5 Timer 5-13

C79000-G7076-C566-01 5-1
Timer Instructions
5.1 Memory Areas and Components of a Timer
Memory Area Timers have an area reserved for them in the memory of your CPU. This
memory area reserves one 16-bit word for each timer address. When you
program in FBD, 256 timers are supported. Please refer to your CPU’s
technical information to check the number of timer words available.
The following functions access the timer memory area:
Timer instructions
Updating of timer words by the clock timing. In the RUN mode, this CPU
function decrements a given time value by one unit at the interval
specified by the time base until the time value is zero.
Time Value Bits 0 through 9 of the timer word contain the time value in binary code. The
time value specifies a number of units. When the timer is updated, the time
value is decremented by one unit at intervals specified by the time base. The
time value is decremented until it is equal to zero.
You can load a predefined time value with the following syntax.
S5T#aH_bbM_ccS_dddMS
– where: a = hours, bb = minutes, cc = seconds and ddd = milliseconds
– The time base is selected automatically, and the value is rounded
down to the next lower number with that time base.
The maximum time value you can enter is 9,990 seconds, or 2H_46M_30S.
Time Base Bits 12 and 13 of the timer word contain the time base in binary code. The
time base defines the interval at which the time value is decremented by one
unit (see Table 5-1 and Figure 5-1). The smallest time base is 10 ms; the
largest is 10 s.
Table 5-1 Time Base and Binary Code
Time Base Binary Code for the Time Base

10 ms 00
100 ms 01
1s 10
10 s 11

5-2 C79000-G7076-C566-01
Timer Instructions
Because time values are saved at only one time interval, values that are not
exact multiples of a time interval are truncated. Values with a resolution too
high for the required range are rounded down to within the required range but
not to the desired resolution. The following table shows the possible
resolutions and the corresponding ranges.
Table 5-2 Resolution and Ranges of the Time Base
Resolution Time Base

0.01 seconds 10MS to 9S_990MS
0.1 seconds 100MS to 1M_39S_900MS
1 second 1S to 16M_39S
10 seconds 10S to 2HR_46M_30S
Bit Configuration When a timer is started, the contents of the timer cell are used as the time
in the Timer Cell value. Bits 0 through 11 of the timer cell contain the time value in binary
coded decimal format (BCD format: each group of four bits contains the
binary code for one decimal value). Bits 12 and 13 contain the time base in
binary code (see Table 5-2). Figure 5-1 shows the contents of the timer cell
loaded with timer value 127 with a time base of 1 second.
15... ...8 7... ...0

x x 1 0 0 0 0 1 0 0 1 0 0 1 1 1
1 2 7
Time base Time value in BCD (0 to 999)

1 second
Irrelevant: These bits are ignored when the timer is started.
Figure 5-1 Contents of the Timer Cell for Timer Value 127, Time Base 1 Second
Reading the Time Each timer box provides two outputs, BI and BCD, for which you can specify
and the Time Base a word location. The BI output provides the time value in binary format, the
time base is not displayed. The BCD output provides the time base and the
time value in binary coded decimal (BCD) format.

C79000-G7076-C566-01 5-3
Timer Instructions
5.2 Choosing the Right Timer
The following figure provides an overview of the five types of timers

described in this chapter. This overview is intended to help you choose the
right timer for your timing job.
Input signal I0.0
Output signal Q4.0 S_PULSE

(Pulse timer) t
The maximum time that the output signal remains at 1 is the
same as the programmed time value t. The output signal
stays at 1 for a shorter period if the input signal changes to 0.
Output signal Q4.0 S_PEXT

(Extended pulse t
timer)
The output signal remains at 1 for the programmed length of
time, regardless of how long the input signal stays at 1.
Output signal Q4.0 S_ODT

(On-delay timer) t
The output signal changes to 1 only when the programmed

time has elapsed and the input signal is still 1.
Output signal Q4.0 S_ODTS

(Retentive t
on-delay timer)
The output signal changes from 0 to 1 only when the
programmed time has elapsed, regardless of how long the
input signal stays at 1.
Output signal Q4.0 S_OFFDT

(Off-delay timer) t
The output signal changes to 1 when the input signal changes
to 1 or while the timer is running. The time is started when the
input signal changes from 1 to 0.
Figure 5-2 Choosing the Right Timer

5-4 C79000-G7076-C566-01
Timer Instructions
5.3 Pulse S5 Timer
Description The Pulse S5 Timer instruction starts a specified timer if there is a rising edge
(a change in signal state from 0 to 1) at the Start (S) input. A signal change is
always necessary to start a timer. The timer continues to run for the time
specified at the Time Value (TV) input until the programmed time elapses, as
long as the signal state at input TV is 1. While the timer is running, a signal
state check for 1 at output Q produces a result of 1. If there is a change from
1 to 0 at the S input before the time has elapsed, the timer is stopped. Then a
signal state check for 1 at output Q produces a result of 0.
While the timer is running, a change from 0 to 1 at the Reset (R) input of the
timer resets the timer. This change also resets the time and the time base to
zero. A signal state of 1 at the R input of the timer has no effect if the timer
is not running.
The current time value can be scanned at outputs BI and BCD. The time
value at BI is in binary format; at BCD it is in binary coded decimal format.
Table 5-3 Pulse S5 Timer Box and Parameters with SIMATIC Mnemonics

Nr. TIMER T Timer identification number. The range
depends on the CPU.
T–Nr.
T Nr.
S BOOL E, A, M, D, L, T, Z Start input
S IMPULS
S_IMPULS
TW S5TIME E, A, M, D, L or Preset time value (range 0 to 9999)
S DUAL constant
TW DEZ R BOOL E, A, M, D, L, T, Z Reset input
R DUAL WORD E, A, M, D, L Time remaining (value in integer format)

Q
DEZ WORD E, A, M, D, L Time remaining (value in BCD format)
Q BOOL E, A, M, D, L Status of the timer
Table 5-4 Pulse S5 Timer Box and Parameters with International Mnemonics

no. TIMER T Timer identification number. The range
depends on the CPU.
T no.
S BOOL I, Q, M, D, L, T, C Start input
S PULSE
S_PULSE
TV S5TIME I, Q, M, D, L or Preset time value (range 0 to 9999)
S BI constant
TV BCD R BOOL I, Q, M, D, L, T, C Reset input
R Q BI WORD I, Q, M, D, L Time remaining (value in integer format)

BCD WORD I, Q, M, D, L Time remaining (value in BCD format)
Q BOOL I, Q, M, D, L Status of the timer

C79000-G7076-C566-01 5-5
Timer Instructions
Example Figure 5-3 illustrates the Pulse S5 Timer instruction, describes the status word
bits, and shows the characteristics of the instruction.
If the signal state of input I0.0 changes from 0 to 1 (if

there is a rising edge in the RLO), timer T5 is started.
T5 The timer continues to run with the specified time of
two seconds (2s) as long as input I0.0 is 1. If the
S_PULSE
signal state of input I0.0 changes from 1 to 0 before
I0.0 S BI the time elapses, the timer is stopped. If the signal
state of input I0.1 changes from 0 to 1 while the timer
is running, the timer is reset. The signal state of
S5T# 2s TV BCD output Q4.0 is 1 as long as the timer is running.
Q4.0
I0.1 R Q = Examples of other preset time values:
Available units: h (hours), m (minutes), s (seconds),
ms (milliseconds)
S5T#4s ––> 4 seconds

S5T#1h_15m ––> 1 hour and 15 minutes
S5T#2h_46m_30s––>2 hours, 46 minutes, and
30 seconds
Status Word Bits

writes – – – – – x x x 1
Timing Diagram
–– t –– –– t –– –– t ––
RLO at input S
RLO at input R
Timer running
RLO at output Q
Negated RLO at
output Q
t = programmed time
Figure 5-3 Pulse S5 Timer

5-6 C79000-G7076-C566-01
Timer Instructions
5.4 Extended Pulse S5 Timer
Description The Extended Pulse S5 Timer instruction starts a specified timer if there is a
rising edge (change in signal state from 0 to 1) at the Start (S) input. A signal
change is always necessary to start a timer. The timer continues to run for the
time specified at the Time Value (TV) input, even if the signal state at the S
input changes to 0 before the time has elapsed. A signal state check for 1 at
output Q produces a result of 1 as long as the timer is running. The timer is
restarted with the specified time if the signal state at input S changes from 0
to 1 while the timer is running.
A change from 0 to 1 at the Reset (R) input of the timer while the timer is
running resets the timer. This change also resets the time and the time base to
zero.
The current time value can be scanned at the outputs BI and BCD. The time
Table 5-5 Extended Pulse S5 Timer Box and Parameters with SIMATIC Mnemonics

Timer identification number. The range
Nr. TIMER T
T Nr. depends on the CPU.
S_VIMP
_ S BOOL E, A, M, D, L, T, Z Start input
E, A, M, D, L or
S DUAL TW S5TIME Preset time value (range 0 to 9999)
constant
TW DEZ R BOOL E, A, M, D, L, T, Z Reset input
R Q DUAL WORD E, A, M, D, L Time remaining (value in integer format)

Table 5-6 Extended Pulse S5 Timer Box and Parameters with International Mnemonics

T no. depends on the CPU.
S_PEXT S BOOL I, Q, M, D, L, T, C Start input
S BI TV S5TIME I, Q, M, D, L or Preset time value (range 0 to 9999)
constant

C79000-G7076-C566-01 5-7
Timer Instructions
Example Figure 5-4 illustrates the Extended Pulse S5 Timer instruction, describes the
status word bits, and shows the characteristics of the instruction.
T5 If the signal state of input I0.0 changes from 0 to 1

(rising edge in the RLO), timer T5 is started. The
S_PEXT timer continues to run for the specified time of two
I0.0 S BI seconds (2s) regardless of a falling edge at input S. If
the signal state of input I0.0 changes from 0 to 1
before the time has elapsed, the timer is restarted. If
S5T# 2s TV BCD the signal state of input I0.1 changes from 0 to 1
Q4.0 while the timer is running, the timer is reset. The
I0.1 R Q = signal state of output Q4.0 is 1 as long as the timer is
running.
Status Word Bits

writes – – – – – x x x 1
Timing Diagram
–– t –– –– t –– –– t –– –– t ––
RLO at input S
RLO at input R
Timer running
RLO at output Q
Negated RLO at
output Q
t = programmed time
Figure 5-4 Extended Pulse S5 Timer

5-8 C79000-G7076-C566-01
Timer Instructions
5.5 On-Delay S5 Timer
Description The On-Delay S5 Timer instruction starts a specified timer if there is a rising
edge (change in signal state from 0 to 1) at the Start (S) input. A signal
change is always necessary to start a timer. The timer continues to run for the
time specified at the Time Value (TV) input as long as the signal state at
input S is 1. A signal state check for 1 at output Q produces a result of 1
when the time has elapsed without error and when the signal state at input S
is still 1. When the signal state at input S changes from 1 to 0 while the timer
is running, the timer is stopped. In this case, a signal state check for 1 at
output Q always produces the result 0.
running resets the timer. This change also resets the time and the time base to
zero. The timer is also reset if the signal state is 1 at the R input while the
timer is not running.
Table 5-7 On-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics

T–Nr. depends on the CPU.
S_EVERZ S BOOL E, A, M, D, L, T, Z Start input
S DUAL TW S5TIME E, A, M, D, L or Preset time value (range 0 – 9999)
constant
TW DEZ
R BOOL E, A, M, D, L, T, Z Reset input
Table 5-8 On-Delay S5 Timer Box and Parameters with International Mnemonics

S_ODT S BOOL I, Q, M, D, L, T, C Start input
S BI TV S5TIME I, Q, M, D, L or Preset time value (range 0 – 9999)
constant

C79000-G7076-C566-01 5-9
Timer Instructions
Example Figure 5-5 illustrates the On-Delay S5 Timer instruction, describes the bits in
the status word and shows the characteristics of the instruction.
If the signal state of input I0.0 changes from 0 to 1

T5
(rising edge in the RLO), timer T5 is started. If the
S_ODT specified time of two seconds (2s) elapses and
I0.0 S BI the signal state of input I0.0 is still 1, the signal
state of output Q4.0 is 1. If the signal state of
input I0.0 changes from 1 to 0, the timer is
S5T# 2s TV BCD stopped and output Q4.0 is 0. If the signal state of
input I0.1 changes from 0 to 1 while the timer is
Q4.0
I0.1 R Q = running, the timer is restarted.
Status Word Bits

writes – – – – – x x x 1
Timing Diagram
–– t –– –– t –– –– t ––
RLO at input S
RLO at input R
Timer running
RLO at output Q
Negated RLO at
output Q
t = programmed time
Figure 5-5 On-Delay S5 Timer

5-10 C79000-G7076-C566-01
Timer Instructions
5.6 Retentive On-Delay S5 Timer
Description The Retentive On-Delay S5 Timer instruction starts a specified timer if there
is a rising edge (change in signal state from 0 to 1) at the Start (S) input. A
signal change is always necessary to start a timer. The timer continues to run
for the time specified at the Time Value (TV) input, even if the signal state at
input S changes to 0 before the timer has expired. A signal state check for 1
at output Q produces a result of 1 when the time has elapsed, regardless of
the signal state at input S when the reset input (R) remains at 0. The timer is
restarted with the specified time if the signal state at input S changes from 0
to 1 while the timer is running.
A change from 0 to 1 at the Reset (R) input of the timer resets the timer
regardless of the RLO at the S input.
Table 5-9 Retentive On-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics

S SEVERZ
S_SEVERZ S BOOL E, A, M, D, L, T, Z Start input
constant
TW DEZ
R Q
DUAL WORD E, A, M, D, L Time remaining (value in integer format)
Table 5-10 Retentive On-Delay S5 Timer Box and Parameters with International Mnemonics

S ODTS
S_ODTS S BOOL I, Q, M, D, L, T, C Start input
constant
TV BCD
R BOOL I, Q, M, D, L, T, C Reset input
R Q
BI WORD I, Q, M, D, L Time remaining (value in integer format)

C79000-G7076-C566-01 5-11
Timer Instructions
Example Figure 5-6 illustrates the Retentive On-Delay S5 Timer instruction, describes
the status word bits, and shows the characteristics of the instruction.
If the signal state of input I0.0 changes from 0 to

T5 1 (rising edge in the RLO), timer T5 is started.
S_ODTS The timer continues to run regardless of a signal
BI change at input I0.0 from1 to 0. If the signal
I0.0 S
state of input I0.0 changes from 0 to 1 before
the time has elapsed, the timer is restarted. If
S5T# 2s TV BCD the signal state of input I0.1 changes from 0 to 1
while the timer is running, the timer is restarted.
Q4.0 The signal state of output Q4.0 is 1 if the time
I0.1 R Q = has elapsed and the signal state at I 0.1
remains 0.
Status Word Bits

writes – – – – – x x x 1
Timing Diagram
–– t –– –– t –– –– t –– –t–
RLO at input S
RLO at input R
Timer running
RLO at output Q
Negated RLO at
output Q
t = programmed time
Figure 5-6 Retentive On-Delay S5 Timer

5-12 C79000-G7076-C566-01
Timer Instructions
5.7 Off-Delay S5 Timer
Description The Off-Delay S5 Timer instruction starts a specified timer if there is a falling
edge (change in signal state from 1 to 0) at the Start (S) input. A signal
change is always necessary to start a timer. The result of a signal state check
for 1 at output Q is 1 when the signal state at the S input is 1 or when the
timer is running. The timer is reset when the signal state at input S changes
from 0 to 1 while the timer is running. The timer is not restarted until the
signal state at input S changes again from 1 to 0.
running resets the timer.
The actual time value can be scanned at the outputs BI and BCD. The time
Table 5-11 Off-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics

S_AVERZ S BOOL E, A, M, D, L, T, Z Start input
constant
TW DEZ
Table 5-12 Off-Delay S5 Timer Box and Parameters with International Mnemonics

S_OFFDT S BOOL I, Q, M, D, L, T, C Start input
constant
TV BCD

C79000-G7076-C566-01 5-13
Timer Instructions
Example Figure 5-7 illustrates the Off-Delay S5 Timer instruction, describes the status
word bits, and shows the characteristics of the instruction.
T5
S_OFFDT
BI If the signal state at input I0.0 changes from 1 to 0,
I0.0 S
the timer is started. Output Q4.0 is 1 when I0.0 is 1 or
the timer is running. If the signal state at I0.1 changes
S5T# 2s TV BCD from 0 to 1, while the timer is running, the timer is
reset.
Q4.0
I0.1 R Q =
Status Word Bits

writes – – – – – x x x 1
Timing Diagram
–– t –– –– t –– –– t –– –– t ––
RLO at input S
RLO at input R
Timer running
RLO at output Q
Negated RLO at
output Q
t = programmed time
Figure 5-7 Off-Delay S5 Timer

5-14 C79000-G7076-C566-01
Counter Instructions 6
Overview 6.1 Memory Address and Components of a Counter 6-2
6.2 Up-Down Counter 6-3
6.3 Up Counter 6-5
6.4 Down Counter 6-7

C79000-G7076-C566-01 6-1
Counter Instructions
6.1 Memory Address and Components of a Counter
Memory Area Counters have an area reserved for them in the memory of your CPU. This
memory area reserves one 16-bit word for each counter address. When you
program in FBD, 256 counters are supported.
The counter instructions are the only functions that can access the counter
memory area.
Count Value Bits 0 through 9 of the counter word contain the count value in binary code.
The count value is taken from the accumulator and entered in the counter
word when a counter is set. The range of the count value is 0 to 999. You can
increment/decrement the count value within this range using the Up-Down
Counter, Up Counter, and Down Counter instructions.
Bit Configuration A counter is set to a required value by loading a number between 0 and 999
in the Counter as the count value, for example 127, in the following format:
C# 127
The C# stands for binary coded decimal format (BCD format: each group of
four bits contains the binary code for one decimal value).
Bits 0 through 11 of the counter contain the count value in binary coded
decimal format . Figure 6-1 shows the contents of the counter after you have
loaded the count value 127 and the contents of the counter cell after the
counter has been set.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 0 0 1 1 1
irrelevant 1 2 7
Count value in BCD (0 to 999)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 1 1 1 1 1
irrelevant Binary count value
Figure 6-1 Contents of the Counter Cell after the Counter has been Set with Count
Value 127

6-2 C79000-G7076-C566-01
6.2 Up-Down Counter
Description A rising edge (change in signal state from 0 to 1) at input S of the Up-Down
Counter instruction sets the counter with the value at the Preset Value (PV)
input. The counter is incremented by 1 if the signal state at input CU changes
from 0 to 1 (rising edge) and the value of the counter is less than 999. The
counter is decremented by 1 if the signal state at input CD changes from 0 to
1 (rising edge) and the value of the counter is higher than 0. If there is a
rising edge at both count inputs, both operations are executed and the count
remains the same. The counter is reset if there is a rising edge at input R.
Resetting the counter sets the count value to 0.
A signal state check for 1 at output Q produces a result of 1 when the count is
greater than 0; the check produces a result of 0 when the count is equal to 0.
Table 6-1 Up-Down Counter Box and Parameters with SIMATIC Mnemonics

Nr. COUNTER Z Counter identification number. The
range depends on the CPU.
Z-Nr
Z-Nr.
ZV BOOL E, A, M, D, L ZV input: Up Counter
ZAEHLER
ZV ZR BOOL E, A, M, D, L ZR input: Down Counter
ZR S BOOL E, A, M, D, L, T, Z Input for presetting the counter
S DUAL ZW WORD E, A, M, D, L Count value in the range between 0

or constant and 999 or
ZW DEZ
Q Count value entered as C#<value> in
R
BCD format
DUAL WORD E, A, M, D, L Current count value (integer format)
DEZ WORD E, A, M, D, L Current count value (BCD format)
Q BOOL E, A, M, D, L Status of the counter

C79000-G7076-C566-01 6-3
Table 6-2 Up-Down Counter Box and Parameters with International Mnemonics

no. COUNTER C Counter identification number. The
C no. CU BOOL I, Q, M, D, L CU input: Up Counter
S CUD
S_CUD CD BOOL I, Q, M, D, L CD input: Down Counter
CU S BOOL I, Q, M, D, L, C Input for presetting the counter
CD PV WORD I, Q, M, D, L Count value in the range between 0
S CV or and 999
PV CV_BCD constant or
R Q Count value entered as C#<value> in
BCD format
R BOOL I, Q, M, D, L, C Reset input
CV WORD I, Q, M, D, L Current count value (integer format)
CV_BCD WORD I, Q, M, D, L Current count value (BCD format)
Q BOOL I, Q, M, D, L Status of the counter
C10
S_CUD A change in signal state from 0 to 1 at
input I0.2 sets counter C10 with the value
I0.0 CU
55. If the signal state of input I0.0
changes from 0 to 1, the value of counter
I0.1 CD C10 is incremented by 1, except when
the value of counter C10 is already 999.
If input I0.1 changes from 0 to 1, counter
I0.2 S CV
C10 is decremented by 1, except when
the value of counter C10 is already 0. If
C#55 PV CV_BCD I0.3 changes from 0 to 1, the value of
Q4.0 C10 is set to 0.
I0.3 R Q = Q4.0 is 1, when C 10 is not equal to 0.
Status Word Bits

writes – – – – – x x x 1
Figure 6-2 Up-Down Counter

6-4 C79000-G7076-C566-01
6.3 Up Counter
Description A rising edge (change in signal state from 0 to 1) at input S of the Up

Counter instruction sets the counter with the value at the Preset Value (PV)
input. With a rising edge at input CU, the count value is incremented by 1
when the count value is less than 999. The counter is reset by a rising edge at
input R. Resetting the counter sets the count value to 0.
greater than 0. The check produces a result of 0 when the count is equal to 0.
Table 6-3 Up Counter Box and Parameters with SIMATIC Mnemonics
FBD Box Parameter Data Type Memory Area Description

ZV BOOL E, A, M, D, L ZV input: Up Counter
Z-Nr.
Z Nr
S BOOL E, A, M, D, L, T, Z Input for presetting the counter
Z VORW
Z_VORW
ZW WORD E, A, M, D, L Count value in the range between 0
ZV
and 999
S DUAL or or
constant Count value entered as C#<value> in
ZW DEZ BCD format
R Q R BOOL E, A, M, D, L, T, Z Reset input

Table 6-4 Up Counter Box and Parameters with International Mnemonics

C no. range depends on the CPU.
S_CU
S CU CU BOOL I, Q, M, D, L CU input: Up Counter
CU
S BOOL I, Q, M, D, L, T, C Input for presetting the counter
S CV PV WORD I, Q, M, D, L Count value in the range between 0
and 999
PV CV_BCD or or
R Q constant Count value entered as C#<value> in
BCD format

C79000-G7076-C566-01 6-5
C10
S_CU
I0.0 CU A change in signal state from 0 to 1 at

input I0.2 sets counter C10 with the value
901. If the signal state of I0.0 changes
I0.2 S CV from 0 to 1, the value of counter C10 is
incremented by 1, unless the value of
C10 is equal to 999. If I0.3 changes from
C#901 PV CV_BCD
0 to 1, the value of C 10 is set to 0. The
signal state of output Q 4.0 is 1 if C10 is
Q4.0
not equal to 0.
I0.3 R Q =
Status Word Bits

writes – – – – – x x x 1
Figure 6-3 Up Counter

6-6 C79000-G7076-C566-01
6.4 Down Counter
Description A rising edge (change in signal state from 0 to 1) at input S of the Down
Counter instruction sets the counter with the value at the Preset Value input
(PV). With a rising edge at input CD, the counter is decremented by 1 when
the count value is greater than 0. The counter is reset by rising edge at input
R.
greater than 0; the check produces a result of 0 when the count is equal to 0.
Table 6-5 Down Counter Box and Parameters with SIMATIC Mnemonics

Z-Nr. range depends on the CPU.
Z RUECK
Z_RUECK ZR BOOL E, A, M, D, L ZR input: Down Counter
ZR S BOOL E, A, M, D, L, T, Z Input for presetting the counter
S DUAL ZW WORD E, A, M, D, L Count value in the range between 0

and 999
ZW DEZ
or or
BCD format
Table 6-6 Down Counter Box and Parameters with International Mnemonics

C no. range depends on the CPU.
S_CD
S CD CD BOOL I, Q, M, D, L CD input: Down Counter
CD S BOOL I, Q, M, D, L, T, C Input for presetting the counter
S CV PV WORD I, Q, M, D, L Count value in the range between 0

and 999
PV CV_BCD
or or
BCD format

C79000-G7076-C566-01 6-7
Z10
S_CD
A change in signal state from 0 to 1 at input I0.2

I0.0 CD sets counter C10 with the value 89. If the signal
state of input I0.0 changes from 0 to 1, the value
I0.2 S CV of counter C10 is decreased by 1, unless the
value of counter C 10 is equal to 0. The signal
state of output Q 4.0 is 1 if counter C10 is not
C#901 PV BCD equal to 0. If I0.3 changes from 0 to 1, the value
Q4.0 of C 10 is set to 0.
I0.3 R Q =
Status Word Bits

writes – – – – – x x x 1
Figure 6-4 Down Counter

6-8 C79000-G7076-C566-01
Integer Math Instructions 7
Overview 7.1 Add Integer 7-2
7.2 Add Double Integer 7-3
7.3 Subtract Integer 7-4
7.4 Subtract Double Integer 7-5
7.5 Multiply Integer 7-6
7.6 Multiply Double Integer 7-7
7.7 Divide Integer 7-8
7.8 Divide Double Integer 7-9
7.9 Return Fraction Double Integer 7-10
7.10 Evaluating the Bits of the Status Word with Integer Math 7-11
Instructions

C79000-G7076-C566-01 7-1
Integer Math Instructions
7.1 Add Integer
Description A signal state of 1 at the Enable (EN) input activates the Add Integer
instruction. This instruction adds inputs IN1 and IN2. The result can be
scanned at O. If the result is outside the permissible range for an integer, the
OV and OS bit of the status word are 1 and the ENO is 0.
Table 7-1 Add Integer Box and Parameters

EN BOOL I, Q, M, D, L, T, C Enable input
ADD_II
ADD IN1 INT I, Q, M, D, L First value for addition
EN or constant
IN1 OUT IN2 INT I, Q, M, D, L Second value for addition
or constant
IN2 ENO
OUT INT I, Q, M, D, L Result of addition
ENO BOOL I, Q, M, D, L Enable output
A signal state of 1 at input I 0.0 activates the

ADD_I
ADD_I box. The result of the addition MW0 +
I 0.0 EN MW2 is entered in memory word MW10. If
MW0 IN1 OUT MW10 the result is outside the permitted range for
Q 4.0 an integer or the signal state of input I 0.0 is
ENO 0, output Q 4.0 is set to 0 and the instruction
MW2 IN2 =
is not executed.
Status Word Bits
Instruction is executed (EN = 1):

writes x x x x x 0 x x 1
Figure 7-1 Add Integer

7-2 C79000-G7076-C566-01
7.2 Add Double Integer
Description A signal state of 1 at the Enable (EN) input activates the Add Double Integer
scanned at O. If the result is outside the permissible range for a double
integer, the OV and the OS bit of the status word are 1 and the ENO is 0.
Table 7-2 Add Double Integer Box and Parameters

ADD_DI
ADD DI IN1 DINT I, Q, M, D, L or First value for addition
EN constant
IN1 OUT IN2 DINT I, Q, M, D, L or Second value for addition
constant
IN2 ENO
OUT DINT I, Q, M, D, L Result of addition

ADD_DI ADD_DI box. The result of the addition MD0 +
I 0.0 EN MD4 is entered in memory double word
MD10. If the result is outside the permitted
MD0 IN1 OUT MD10
range for a double integer or the signal state
Q 4.0 of input I 0.0 is 0, output Q 4.0 is set to 0 and
MD4 IN2 ENO = the instruction is not executed.
Status Word Bits

Figure 7-2 Add Double Integer

C79000-G7076-C566-01 7-3
7.3 Subtract Integer
Description A signal state of 1 at the Enable (EN) input activates the Subtract Integer
instruction. This instruction subtracts input IN2 from IN1. The result can be
scanned at O. If the result is outside the permitted range for an integer, the
OV and the OS bit of the status word are 1 and the ENO is 0.
Table 7-3 Subtract Integer Box and Parameters

SUB_II
SUB IN1 INT I, Q, M, D, L or Minuend (value from which second value
EN constant is subtracted)
IN1 OUT IN2 INT I, Q, M, D, L or Subtrahend (value subtracted from the
constant first value)
IN2 ENO
OUT INT I, Q, M, D, L Result of subtraction
SUB_I A signal state of 1 at input I 0.0 activates the

SUB_I box. The result of the subtraction MW0
I 0.0 EN
– MW2 is entered in memory word MW10. If
MW0 IN1 OUT MW10 the result is outside the permitted range for an
Q 4.0 integer or the signal state of input I 0.0 is 0,
output Q 4.0 is set to 0 and the instruction is
MW2 IN2 ENO = not executed.
Status Word Bits

Figure 7-3 Subtract Integer

7-4 C79000-G7076-C566-01
7.4 Subtract Double Integer
Description A signal state of 1 at the Enable (EN) input activates the Subtract Double
Integer instruction. This instruction subtracts input IN2 from IN1. The result
can be scanned at O. If the result is outside the permitted range for a double
Table 7-4 Subtract Double Integer Box and Parameters

SUB_DI
SUB DI IN1 DINT I, Q, M, D, L or Minuend (value from which second
EN constant value is subtracted)
IN1 OUT IN2 DINT I, Q, M, D, L or Subtrahend (value subtracted from
IN2 ENO constant the first value)
OUT DINT I, Q, M, D, L Result of subtraction

SUB_DI SUB_DI box. The result of the subtraction
I 0.0 EN MD0 – MD4 is entered in memory double word
MD10 MD10. If the result is outside the permitted
MD0 IN1 OUT
range for a double integer or the signal state of
Q 4.0
input I 0.0 is 0, output Q 4.0 is set to 0 and the
MD4 IN2 ENO =
instruction is not executed.
Status Word Bits

Figure 7-4 Subtract Double Integer

C79000-G7076-C566-01 7-5
7.5 Multiply Integer
Description A signal state of 1 at the Enable (EN) input activates the Multiply Integer
instruction. This instruction multiplies input IN1 by IN2. The result is a
32-bit integer that can be scanned at O. If the result is outside the permitted
range for a 16-bit integer, the OV and the OS bit of the status word are 1 and
the ENO is 0.
Table 7-5 Multiply Integer Box and Parameters

MUL_II
MUL IN1 INT I, Q, M, D, L or Multiplicand (value that is multiplied
EN constant by the second value)
IN1 OUT IN2 INT I, Q, M, D, L or Multiplier (value by which the first
constant value is multiplied)
IN2 ENO
OUT DINT I, Q, M, D, L Result of the multiplication

MUL_I MUL_I box. The result of the multiplication
I 0.0 EN MW0 x MW2 is entered in memory double word
MW0 IN1 OUT MD10 range for a 16-bit integer or the signal state of
Q 4.0 input I 0.0 is 0, output Q 4.0 is set to 0 and the
MW2 IN2 ENO = instruction is not executed.
Status Word Bits

Figure 7-5 Multiply Integer

7-6 C79000-G7076-C566-01
7.6 Multiply Double Integer
Description A signal state of 1 at the Enable (EN) input activates the Multiply Double
Integer instruction. This instruction multiplies inputs IN1 and IN2. The result
can be scanned at O. If the result is outside the permitted range for a double
Table 7-6 Multiply Double Integer Box and Parameters

MUL_DI
MUL DI IN1 DINT I, Q, M, D, L or Multiplicand (value that is multiplied
EN constant by the second value)
IN1 OUT IN2 DINT I, Q, M, D, L or Multiplier (value by which the first
IN2 ENO constant value is multiplied)
OUT DINT I, Q, M, D, L Result of the multiplication

MUL_DI MUL_DI box. The result of the multiplication
I 0.0 EN MD0 x MD4 is entered in memory double word
MD0 IN1 OUT MD10 range for a double integer or the signal state of
Q 4.0 input I 0.0 is 0, output Q 4.0 is set to 0 and the
MD4 IN2 ENO = instruction is not executed.
Status Word Bits

Figure 7-6 Multiply Double Integer

C79000-G7076-C566-01 7-7
7.7 Divide Integer
Description A signal state of 1 at the Enable (EN) input activates the Divide Integer
instruction. This instruction divides input IN1 by IN2. The integer quotient
(truncated result) can be scanned at O. The remainder cannot be scanned. If
the quotient is outside the permitted range for an integer, the OV and the OS
bit of the status word are 1 and the ENO is 0.
Table 7-7 Divide Integer Box and Parameters

DIV I
DIV_I IN1 INT I, Q, M, D, L or Dividend
EN constant
IN1 OUT IN2 INT I, Q, M, D, L or Divisor
IN2 constant
ENO
OUT INT I, Q, M, D, L Result of division

DIV_I DIV_I box. The quotient of dividing MW0 by
I 0.0 EN MW2 is entered in memory word MW10. If the
quotient is outside the permitted range for an
MW0 IN1 OUT MW10 integer or the signal state of input I 0.0 is 0,
Q 4.0 output Q 4.0 is set to 0 and the instruction is
MW2 IN2 ENO = not executed.
Status Word Bits

Figure 7-7 Divide Integer

7-8 C79000-G7076-C566-01
7.8 Divide Double Integer
Description A signal state of 1 at the Enable (EN) input activates the Divide Double
Integer instruction. This instruction divides input IN1 by IN2. The quotient
(truncated result) can be scanned at O. The Divide Double Integer instruction
stores the quotient as a single 32-bit value in DINT format. This instruction
does not produce a remainder. If the quotient is outside the permitted range
for a double integer, the OV and the OS bit of the status word are 1 and the
ENO is 0.
Table 7-8 Divide Double Integer Box and Parameters

DIV_DI
DIV DI IN1 DINT I, Q, M, D, L or Dividend
EN constant
IN1 OUT IN2 DINT I, Q, M, D, L or Divisor
IN2 ENO constant
OUT DINT I, Q, M, D, L Result of division
DIV_DI A signal state of 1 at input I 0.0 activates the

I 0.0 EN DIV_DI box. The quotient of dividing MD0 by
MD4 is entered in memory double word
MD0 IN1 OUT MD10 MD10. If the quotient is outside the permitted
range for a double integer or the signal state
Q 4.0
of input I 0.0 is 0, output Q 4.0 is set to 0 and
MD4 IN2 ENO =
the instruction is not executed.
Status Word Bits

Figure 7-8 Divide Double Integer

C79000-G7076-C566-01 7-9
7.9 Return Fraction Double Integer
Description A signal state of 1 at the Enable (EN) input activates the Return Fraction
Double Integer instruction. This instruction divides input IN1 by IN2. The
remainder (fraction) can be scanned at O. If the result is outside the permitted
range for a double integer, the OV and the OS bit of the status word are 1 and
the ENO is 0.
Table 7-9 Return Fraction Double Integer Box and Parameters

MOD IN1 DINT I, Q, M, D, L or Dividend
EN constant
IN1 OUT IN2 DINT I, Q, M, D, L or Divisor
IN2 ENO constant
OUT DINT I, Q, M, D, L Remainder

MOD MOD box. The remainder (fraction) of
I 0.0 EN dividing MD0 by MD4 is stored in memory
double word MD10. If the result is outside
MD0 IN1 OUT MD10 the permitted range for a double integer or
Q 4.0 the signal state of input I 0.0 is 0, output Q
MD4 IN2 ENO = 4.0 is set to 0 and the instruction is not
executed.
Status Word Bits

Figure 7-9 Return Fraction Double Integer

7-10 C79000-G7076-C566-01
7.10 Evaluating the Bits of the Status Word with Integer Math
Instructions
Description The integer math instructions influence the following bits in the status word:
CC1 and CC0
OV
OS
A dash (-) in the table means that the bit is not affected by the result of the
instruction.
Table 7-10 Signal State of the Status Word Bits (Result in Valid Range)
Valid Range of the Result Status Word Bits
Integers (16 and 32 bits) CC1 CC0 OV OS
0 (zero) 0 0 0 -
16 bits: -32 768 result 0 (negative number)
0 1 0 -
32 bits: -2 147 483 648 result 0 (negative number)
16 bits: 32 767 result 0 (positive number)
1 0 0 -
32 bits: 2 147 483 647 result 0 (positive number)
Table 7-11 Signal State of the Status Word Bits (Result not in Valid Range)
Invalid Range for the Result Status Word Bits
Integers (16 and 32 bits) CC1 CC0 OV OS
16 bits: result 32 767 (positive number)
1 0 1 1
32 bits: result 2 147 483 647 (positive number)
16 bits: result -32 768 (negative number)
0 1 1 1
32 bits: result -2 147 483 648 (negative number)
Table 7-12 Signal State of the Status Word Bits (Math Instructions with Integers
(32 Bits) +D, /D and MOD)
Operation Status Word Bits
CC1 CC0 OV OS
+D: result = -4 294 967 296 0 0 1 1
/D or MOD: division by 0 1 1 1 1

C79000-G7076-C566-01 7-11

7-12 C79000-G7076-C566-01
Floating-Point Math Instructions 8
8.2 Add Real 8-3
8.3 Subtract Real 8-4
8.4 Multiply Real 8-5
8.5 Divide Real 8-6
8.6 Evaluating the Bits of the Status Word with Floating-Point 8-7
Instructions
8.7 Forming the Absolute Value of a Floating-Point Number 8-8
8.8 Forming the Square (SQR) of a Floating-Point Number 8-9
8.9 Forming the Square Root (SQRT) of a Floating-Point 8-10
Number
8.10 Forming the Natural Logarithm of a Floating-Point Number 8-11
8.11 Forming the Exponential Value of a Floating-Point Number 8-12
8.12 Forming Trigonometric Functions of Angles as 8-13
Floating-Point Numbers

C79000-G7076-C566-01 8-1
Floating-Point Math Instructions
8.1 Overview
You can use the floating-point math instructions to perform the following
math operations using two 32-bit IEEE floating-point numbers:
Add
Subtract
Multiply
Divide
The IEEE 32-bit floating-point numbers belong to the data type known as
REAL. Using floating-point math, you can carry out the following operations
with one 32-bit IEEE floating-point number:
Form the absolute value (ABS) of a floating-point number
Form the square (SQR) or square root (SQRT) of a floating-point number
Form the natural logarithm (LN) of a floating-point number
Form the exponential value of a floating-point number (EXP) to
base e (= 2.71828...)
Form the following trigonometric functions of an angle, represented as a
32-bit floating-point number:
– Form the sine of a floating-point number (SIN) and form the arc sine
of a floating-point number (ASIN)
– Form the cosine of a floating-point number (COS) and form the arc
cosine of a floating-point number (ACOS)
– Form the tangent of a floating-point number (TAN) and form the arc
tangent of a floating-point number (ATAN)

8-2 C79000-G7076-C566-01
8.2 Add Real
Description A signal state of 1 at the Enable input (EN) activates the Add Real
scanned at output OUT. If either of the inputs or the result is not a
floating-point number, the OV bit and OS bit are set to 1 and ENO is set to 0.
For more detailed information about evaluating the bits in the status word,
Table 8-1 Add Real Box and Parameters

ADD_R
ADD R
IN1 REAL I, Q, M, D, L or First number to be added
EN
constant
IN1 OUT
IN2 REAL I, Q, M, D,or Second number to be added
IN2 ENO constant L
OUT REAL I, Q, M, D, L Result of addition
A signal state of 1 at input I0.0 activates the

ADD_R ADD_R box. The result of the addition MD0
I0.0 EN + MD4 is entered in memory double word
MD10. If either of the inputs or the result is
MD0 IN1 OUT MD10
not a floating-point number and if the signal
Q4.0 state of I0.0 is 0, output Q4.0 is set to 0 and
Status Word Bits

Figure 8-1 Add Real

C79000-G7076-C566-01 8-3
8.3 Subtract Real
Description A signal state of 1 at the Enable input (EN) activates the Subtract Real
instruction. This instruction subtracts input IN2 from IN1. The result can be
floating-point number, the OV bit and the OS bit are set to 1 and ENO is set
to 0.
Table 8-2 Subtract Real Box and Parameters

SUB_R
SUB R
IN1 REAL I, Q, M, D, L or Minuend (from which the second
EN
constant value is subtracted)
IN1 OUT
IN2 REAL I, Q, M, D, L or Subtrahend (that is subtracted
IN2 ENO constant from the first value)
OUT REAL I, Q, M, D, L Result of subtraction

SUB_R SUB_R box. The result of the subtraction
I0.0 EN MD0 – MD4 is entered in memory double
word MD10. If either of the inputs or the
MD0 IN1 OUT MD10 result is not a floating-point number and if
Q4.0 the signal state of I0.0 is 0, output Q4.0 is
MD4 IN2 ENO = set to 0 and the instruction is not executed.
Status Word Bits

Figure 8-2 Subtract Real

8-4 C79000-G7076-C566-01
8.4 Multiply Real
Description A signal state of 1 at the Enable input (EN) activates the Multiply Real
instruction. This instruction multiplies input IN1 by IN2. The result can be
to 0.
Table 8-3 Multiply Real Box and Parameters

MUL_R
MUL R
IN1 REAL I, Q, M, D, L or Multiplicand (value to be
EN
constant multiplied)
IN1 OUT
IN2 REAL I, Q, M, D, L or Multiplier (value by which first
IN2 ENO constant value is multiplied)
OUT REAL I, Q, M, D, L Result of multiplication

MUL_R
MUL_R box. The result of the multiplication
I0.0 EN
MD0 x MD4 is entered in memory double
MD0 IN1 OUT word MD10. If either of the inputs or the
MD10
result is not a floating-point number and if the
Q4.0 signal state of I0.0 is 0, output Q4.0 is set to
MD4 IN2 ENO =
0 and the instruction is not executed.
Status Word Bits

Figure 8-3 Multiply Real

C79000-G7076-C566-01 8-5
8.5 Divide Real
Description A signal state of 1 at the Enable input (EN) activates the Divide Real
instruction. This instruction divides input IN1 by IN2. The result can be
to 0.
Table 8-4 Divide Real Box and Parameters

DIV_R
DIV R
IN1 REAL I, Q, M, D, L or Dividend (value to be divided by
EN constant second value)
IN1 OUT IN2 REAL I, Q, M, D, L or Divisor (value by which first
IN2 ENO constant value is divided)
OUT REAL I, Q, M, D, L Result of division

DIV_R DIV_R box. The result of dividing MD0 by
I0.0 EN MD4 is entered in memory double word
MD10. If either of the inputs or the result is
MD0 IN1 OUT MD10 not a floating-point number and if the signal
Q4.0 state of I0.0 is 0, output Q4.0 is set to 0 and
Status Word Bits

Figure 8-4 Divide Real

8-6 C79000-G7076-C566-01
8.6 Evaluating the Bits of the Status Word with Floating-Point

Instructions
Description Floating-point instructions affect the following bits in the status word:
CC1 and CC0
OV
OS
A dash (–) in the table means that the bit is not affected by the result of the
instruction.
Table 8-5 Signal State of the Status Word Bits for Results of Instructions with
Floating-Point Numbers (Result in the Valid Range)
Valid Range for Result Status Word Bits

Instruction with Floating-Point Numbers (32 CC1 CC0 OV OS
Bits)
+0, –0 (zero) 0 0 0 –
–3.402823E+38 < result < –1.175494E–38 0 1 0 –
(negative number)
+1.175494E–38 < result < 3.402823E+38 1 0 0 –
(positive number)
Table 8-6 Signal State of the Status Word Bits for Results of Instructions with
Floating-Point Numbers (Result outside the Valid Range)
Invalid Range for Result Status Word Bits

Instruction with Floating-Point Numbers (32 CC1 CC0 OV OS
Bits)
–1.175494E–38 < result < – 1.401298E–45 0 0 1 1
(negative number) below minimum
+1.401298E–45 < result < +1.175494E–38 0 0 1 1
(positive number) below minimum
result < –3.402823E+38 0 1 1 1
(negative number) above maximum
result > 3.402823E+38 1 0 1 1
(positive number) above maximum
result < –3.402823E+38 1 1 1 1
or result > +3.402823E+38
not a floating-point number

C79000-G7076-C566-01 8-7
8.7 Forming the Absolute Value of a Floating-Point Number
Description With the Form the Absolute Value of a Floating-Point Number instruction,
you can form the absolute value of floating-point number.
Table 8-7 ABS Box and Parameters

ABS
IN REAL I, Q, M, D, L or Input value: floating-point number
EN OUT constant
IN ENO OUT REAL I, Q, M, D, L Output value: absolute value of the

floating-point number
If I0.0 = 1, the absolute value of MD8 is

output at MD12.
ABS
MD8 = +6.234 x 10–3 results in
I0.0 EN OUT MD12
MD12 = 6.234 x 10–3.
Q4.0
MD8 IN ENO = Output Q4.0 is 0 if the conversion is not
executed (ENO = EN = 0).
Status Word Bits

writes X – – – – 0 X X 1
Figure 8-5 Forming the Absolute Value of a Floating-Point Number

8-8 C79000-G7076-C566-01
8.8 Forming the Square (SQR) of a Floating-Point Number
Description With the Form the Square of a Floating-Point Number instruction, you can
square a floating-point number. If either of the inputs or the result is not a
Parameter Table 8-8 shows the SQR box and describes the parameters.
Table 8-8 SQR Box and Parameters
FBD Box Parameters Data Memory Area Description

Type
IN REAL I, Q, M, D, L or Number
SQR constant
EN OUT
OUT REAL I, Q, M, D, L Square of the
number
IN ENO

SQR SQR box. The result of SQR (MD0) is
entered in the memory double word MD10. If
I0.0 EN OUT MD10 MD0 is less than 0 or if either of the inputs or
Q4.0 the result is not a floating-point number and if
MD0 IN ENO = the signal state of I0.0 is 0, output Q4.0 is set
to 0.
Status Word Bits

Figure 8-6 Forming the Square of a Floating-Point Number

C79000-G7076-C566-01 8-9
8.9 Forming the Square Root (SQRT) of a Floating-Point Number
Description With the Form the Square Root of a Floating-Point Number instruction, you
can extract the square root of a floating-point number. This instruction
returns a positive result, if the value at the address is greater than “0”. If
either of the inputs or the result is not a floating-point number, the OV bit
and OS bit are set to 1 and ENO is set to 0.
Parameter Table 8-9 shows the SQRT box and describes the parameters.
Table 8-9 SQRT Box and Parameters

Type
SQRT IN REAL I, Q, M, D, L or Number
EN OUT constant
OUT REAL I, Q, M, D, L Square root of
IN ENO the number

SQRT SQRT box. The result of SQRT (MD0) is
entered in memory double word MD10. If
I0.0 EN OUT MD10 MD0 is less than 0 or if either of the inputs or
Q4.0 the result is not a floating-point number and if
MD0 IN ENO = the signal state of I0.0 is 0, output Q4.0 is set
to 0.
Status Word Bits

Figure 8-7 Forming the Square Root of a Floating-Point Number

8-10 C79000-G7076-C566-01
8.10 Forming the Natural Logarithm of a Floating-Point Number
Description With the Form the Natural Logarithm of a Floating-Point Number

instruction, you can form the natural logarithm of a floating-point number. If
either of the inputs or the result is not a floating-point number, the OV bit
and OS bit are set to 1 and ENO is set to 0.
Table 8-10 LN Box and Parameters

Type
IN REAL I, Q, M, D, L or Number
LN
constant
EN OUT
OUT REAL I, Q, M, D, L Natural
IN ENO logarithm of the
number

LN LN box. The result of LN (MD0) is entered in
memory double word MD10. If MD0 is less
I0.0 EN OUT MD10 than 0 or if either of the inputs or the result is
Q4.0 not a floating-point number and if the signal
MD0 IN ENO = state of I0.0 is 0, output Q4.0 is set to 0.
Status Word Bits

Figure 8-8 Forming the Natural Logarithm of a Floating-Point Number

C79000-G7076-C566-01 8-11
8.11 Forming the Exponential Value of a Floating-Point Number
Description With the Form the Exponential Value of a Floating-Point Number

instruction, you can form the exponential value of a floating-point number to
base e (= 2.71828...). If either of the inputs or the result is not a
Table 8-11 EXP Box and Parameters

Type
EXP IN REAL I, Q, M, D, L or Number

constant
EN OUT
OUT REAL I, Q, M, D, L Exponent of
IN ENO the number

EXP EXP box. The result of EXP (MD0) is entered
in memory double word MD10. If either of the
I0.0 EN OUT MD10 inputs or the result is not a floating-point
Q4.0 number and if the signal state of E 0.0 is 0,
MD0 IN ENO = output Q4.0 is set to 0.
Status Word Bits

Figure 8-9 Forming the Exponential Value of a Floating-Point Number

8-12 C79000-G7076-C566-01
8.12 Forming Trigonometric Functions of Angles as Floating-Point

Numbers
Description With the following instructions, you can form trigonometric functions of
angles represented as 32-bit IEEE floating-point numbers.
Instruction Meaning
SIN Form the sine of a floating-point number of an angle specified in
radians.
ASIN Form the arc sine of a floating-point number . The result is an angle
specified in radians. The value is in the following range:
/ 2 arc sine + / 2, where = 3.14...
COS Form the cosine of a floating-point number of an angle specified in
radians.
ACOS Form the arc cosine of a floating-point number . The result is an angle
0 arc cosine + , where = 3.14...
TAN Form the tangent of a floating-point number of an angle specified in
radians.
ATAN Form the arc tangent of a floating-point number . The result is an angle
/ 2 arc tangent + / 2, where = 3.14...
Parameter Tables 8-12 through 8-17 show the SIN, ASIN, COS, ACOS, TAN and ATAN
boxes and describe the parameters.
Table 8-12 SIN Box and Parameters

Type
SIN IN REAL I, Q, M, D, L or Number

EN OUT constant
OUT REAL I, Q, M, D, L Sine of the

IN ENO number

C79000-G7076-C566-01 8-13
Table 8-13 ASIN Box and Parameters

Type
ASIN IN REAL I, Q, M, D, L or Number
EN OUT constant
OUT REAL I, Q, M, D, L Arc sine of the
IN ENO number
Table 8-14 COS Box and Parameters

Type
COS IN REAL I, Q, M, D, L or Number
EN OUT constant
OUT REAL I, Q, M, D, L Cosine of the
IN ENO
number
Table 8-15 ACOS Box and Parameters

Type
ACOS IN REAL I, Q, M, D, L or Number
EN OUT constant
OUT REAL I, Q, M, D, L Arc cosine of
IN ENO the number
Table 8-16 TAN Box and Parameters

Type
TAN IN REAL I, Q, M, D, L or Number

constant
EN OUT
OUT REAL I, Q, M, D, L Tangent of the
IN ENO number

8-14 C79000-G7076-C566-01
Table 8-17 ATAN Box and Parameters

Type
ATAN IN REAL I, Q, M, D, L or Number

constant
EN OUT
OUT REAL I, Q, M, D, L Arc tangent of
IN ENO the number

SIN SIN box. The result of SIN (MD0) is entered in
memory double word MD10. If either of the
I0.0 EN OUT MD10 inputs or the result is not a floating-point
Q4.0
number and if the signal state of I0.0 is 0,
MD0 IN ENO = output Q4.0 is set to 0.
Status Word Bits

Figure 8-10 Forming the Sine of a Floating-Point Number

C79000-G7076-C566-01 8-15

8-16 C79000-G7076-C566-01
Comparison Instructions 9
Overview 9.1 Compare Integer 9-2
9.2 Compare Double Integer 9-3
9.3 Compare Real 9-4

C79000-G7076-C566-01 9-1
Comparison Instructions
9.1 Compare Integer
Description The Compare Integer instruction compares two values on the basis of 16-bit
floating-point numbers. This instruction compares inputs IN1 and IN2
according to the type of comparison you select from the list box. The
following table lists the available types of comparison.
If the comparison is true, the result of logic operation (RLO) of the
comparison is 1. Otherwise, it is 0. You cannot negate the comparison result
itself, but you can achieve the same effect as negation by using the opposite
compare function.
Table 9-1 Types of Comparison for Integers
Type of Comparison Relational Operator

IN1 is equal to IN2. ==
IN1 is not equal to IN2. <>
IN1 is greater than IN2. >
IN1 is less than IN2. <
IN1 is greater than or equal to IN2. >=
IN1 is less than or equal to IN2. <=
Table 9-2 Compare Integer Box and Parameters (Example using Equal)

I, Q, M, D, L or
CMP IN1 INT First value to compare
constant
== I
I, Q, M, D, L or
IN1 IN2 INT Second value to compare
constant
IN2
Box output BOOL I, Q, M, D, L Result of comparison
Q4.0 is set when:
CMP MW0 is equal to MW2 AND the signal state

& is 1 at input I0.0
== I
MW0 IN1 I0.0 Q4.0
MW2 IN2 S
Status Word Bits
Comparison is true:
writes x x x 0 – 0 1 x 1
Figure 9-1 Compare Integer

9-2 C79000-G7076-C566-01
9.2 Compare Double Integer
Description The Compare Double Integer instruction compares two values on the basis of
32-bit floating-point numbers. This instruction compares inputs IN1 and IN2
compare function.
Table 9-3 Types of Comparison for Double Integers

Table 9-4 Compare Double Integer Box and Parameters (Example using Not Equal)

I, Q, M, D, L or
CMP IN1 DINT First value to compare
constant
<> D
I, Q, M, D, L or
IN1 IN2 DINT Second value to compare
constant
IN2
CMP Q4.0 is set when:

<> D &
MD0 is not equal to MD4
MD0 IN1 I0.0
Q4.0 AND the signal state at
MD4 IN2 S at input I0.0 is 1
Status Word Bits

Comparison is true:
writes – x x 0 – 0 x x 1
Figure 9-2 Compare Double Integer

C79000-G7076-C566-01 9-3
9.3 Compare Real
Description The Compare Real instruction compares two values on the basis of
floating-point numbers. This instruction compares inputs IN1 and IN2
compare function.
Table 9-5 Types of Comparison for Floating-Point Numbers

Table 9-6 Compare Real Box and Parameters (Example using Less Than)

I, Q, M, D, L or
CMP IN1 REAL First value to compare
constant
<R
I, Q, M, D, L or
IN1 IN2 REAL Second value to compare
constant
IN2
CMP Q4.0 is set when:

&
<R MD0 is less than MD4
I0.0
MD0 IN1 Q4.0 AND the signal state at
MD4 IN2 S input I0.0 is 1
Status Word Bits

Comparison is true:
writes – x x x x 0 x x 1
Figure 9-3 Compare Real

9-4 C79000-G7076-C566-01
Move and Conversion Instructions 10
Overview 10.1 Assign Value 10-2
10.2 BCD to Integer 10-3
10.3 Integer to BCD 10-4
10.4 Integer to Double Integer 10-5
10.5 BCD to Double Integer 10-6
10.6 Double Integer to BCD 10-7
10.7 Double Integer to Real 10-8
10.8 Ones Complement Integer 10-9
10.9 Ones Complement Double Integer 10-10
10.10 Twos Complement Integer 10-11
10.11 Twos Complement Double Integer 10-12
10.12 Negate Real Number 10-13
10.13 Round to Double Integer 10-14
10.14 Truncate Double Integer Part 10-15
10.15 Ceiling 10-16
10.16 Floor 10-17

C79000-G7076-C566-01 10-1
Move and Conversion Instructions
10.1 Assign Value
Description With the Assign Value instruction, you can assign specific values to variables.
The value specified at the IN input is copied to the address specified at the
OUT output. ENO has the same signal state as EN.
With the MOVE box, the Assign Value instruction can copy all data types
with lengths of 8, 16, or 32 bits. User-defined data types such as arrays or
structures must be be copied with the system function SFC20 “BLKMOV”
(see the Reference Manual /235/).
The Assign Value instruction is affected by the Master Control Relay (MCR).
For more information on how the MCR functions, see Section 16.5.
Table 10-1 Assign Value Box and Parameters

IN All data types with a I, Q, M, D, L or Source value
MOVE
length of 8, 16 or constant
EN OUT 32 bits
OUT All data types with a I, Q, M, D, L Destination address
IN ENO length of 8, 16 or
32 bits
MOVE The instruction is executed, when input I0.0 is

1. The content of MW10 is copied to data word
I0.0 12 of the open DB.
EN OUT DBW12
Q4.0
MW10 = If the instruction is executed, Q4.0 is set to 1.
IN ENO
Status Word Bits

writes 1 – – – – 0 1 1 1
Figure 10-1 Assign Value
Assigning Values For information about integrated system functions that can be used as move
to Variables instructions and that can assign a specific value to a variable or can copy
variables of varying types, refer to the Reference Manual /235/.

10-2 C79000-G7076-C566-01
10.2 BCD to Integer
Description The BCD to Integer instruction reads the content of the input parameter IN as
a three-digit number in binary coded decimal format (BCD, 999) and
converts this number to an integer value. The output parameter OUT contains
the result.
ENO always has the same signal state as EN.
If any of the individual decimal numbers in the BCD number is in the invalid
range between 10 and 15, a BCD error occurs when the conversion is
attempted, causing the following reaction:
The CPU changes to the STOP mode. “BCD conversion error” is entered
in the diagnostic buffer with event ID number 2521.
If OB121 is programmed, it is called.
For more detailed information about programming OB121, refer to the
Reference Manual /235/.
Table 10-2 BCD to Integer Box and Parameters

BCD I
BCD_I
IN WORD I, Q, M, D, L or Number in BCD format
EN OUT constant
IN ENO
OUT INT I, Q, M, D, L Integer value of the BCD number
The conversion is executed if the signal

BCD_I state of I0.0 is 1. The content of memory
word MW10 is read as a three-digit
I0.0 EN OUT MW12 number in BCD format and converted to
Q4.0 an integer. The result is stored in memory
ENO = word MW12. If the conversion is executed,
MW10 IN
the signal state of output Q4.0 is 1 (ENO =
EN).
Status Word Bits

writes 1 – – – – 0 1 1 1
Figure 10-2 BCD to Integer

C79000-G7076-C566-01 10-3
10.3 Integer to BCD
Description The Integer to BCD instruction reads the content of the input parameter IN as
an integer value and converts this value to a three-digit number in binary
coded decimal format (BCD, 999). The output parameter OUT contains
the result. If an overflow occurs, ENO is set to 0.
Table 10-3 Integer to BCD Box and Parameters

I BCD
I_BCD
IN INT I, Q, M, D,or Integer
EN OUT constant L
IN ENO OUT WORD I, Q, M, D, L BCD value of the integer

state of I0.0 is 1. The content of memory
I_BCD word MW10 is read as an integer and
converted to a three-digit number in BCD
I0.0 EN OUT MW12 format. The result is stored in memory
Q4.0 word MW12. If an overflow occurs, the
MW10 IN ENO = signal state of output Q4.0 is 0. If the
signal state at input EN is 0 (meaning
that the conversion is not executed), the
signal state of output Q4.0 is also 0.
Status Word Bits

writes x – – x x 0 x x 1
Figure 10-3 Integer to BCD

10-4 C79000-G7076-C566-01
10.4 Integer to Double Integer
Description The Integer to Double Integer instruction reads the content of the input
parameter IN as an integer and converts the integer to a double integer. The
output parameter OUT contains the result. ENO always has the same signal
state as EN.
Table 10-4 Integer to Double Integer Box and Parameters

II_DI
DI
EN OUT IN INT I, Q, M, D, L or Value to be converted
constant
IN ENO
OUT DINT I, Q, M, D, L Result

I_DI state of I0.0 is 1. The content of memory
word MW10 is read as an integer and
I0.0 EN OUT MD12 converted to a double integer. The result is
Q4.0 stored in memory double word MD12. If the
MW10 IN ENO = conversion is executed, the signal state of
output Q4.0 is 1 (ENO = EN).
Status Word Bits

writes 1 – – – – 0 1 1 1
Figure 10-4 Integer to Double Integer

C79000-G7076-C566-01 10-5
10.5 BCD to Double Integer
Description The BCD to Double Integer instruction reads the content of the input
parameter IN as a seven-digit number in binary coded decimal format (BCD,
9,999,999) and converts this number to a double integer value. The output
parameter OUT contains the result.
ENO always has the same signal state as EN.
If any of the individual decimal numbers in the BCD number is in the invalid
range between 10 and 15, a BCD error occurs when the conversion is
attempted, causing the following reaction:
The CPU changes to the STOP mode. “BCD conversion error” is entered
in the diagnostic buffer with event ID number 2521.
If OB121 is programmed, it is called.
For more detailed information about programming OB121, refer to the
Reference Manual /235/.
Table 10-5 BCD to Double Integer Box and Parameters

BCD DI
BCD_DI
IN DWORD I, Q, M, D, L or Number in BCD format
EN OUT constant
IN ENO OUT DINT I, Q, M, D, L Double integer value of the BCD
number

BCD_DI state of I0.0 is 1. The content of memory
double word MD8 is read as a seven-digit
I0.0 EN OUT MD12 number in BCD format and converted to a
Q4.0 double integer. The result is stored in MD12.
MD8 IN ENO = If the conversion is executed, the signal
state of output Q4.0 is 1 (ENO = EN).
Status Word Bits

writes 1 – – – – 0 1 1 1
Figure 10-5 BCD to Double Integer

10-6 C79000-G7076-C566-01
10.6 Double Integer to BCD
Description The Double Integer to BCD instruction instruction reads the content of the
input parameter IN as a double integer value and converts this value to a
seven-digit number in BCD format ( 9 999 999). The output parameter
OUT contains the result. If an overflow occurs, ENO is set to 0.
Table 10-6 Double Integer to BCD Box and Parameters

DI BCD
DI_BCD
IN DINT I, Q, M, D, L or Double integer
EN OUT constant
IN ENO OUT DWORD I, Q, M, D, L BCD value of the double integer

DI_BCD double word MD8 is read as a double
integer and converted to a seven-digit
I0.0 EN OUT MD12 number in BCD format. The result is stored
Q4.0 in MD12. If an overflow occurs, the signal
MD8 IN ENO = state of output Q4.0 is 0. If the signal state at
input EN is 0 (meaning that the conversion is
not executed), the signal state of output
Q4.0 is also 0.
Status Word Bits

Figure 10-6 Double Integer to BCD

C79000-G7076-C566-01 10-7
10.7 Double Integer to Real
Description The Double Integer to Real instruction reads the content of the input
parameter IN as a double integer value and converts this value to a real
number. The output parameter OUT contains the result. ENO always has the
same signal state as EN.
Table 10-7 Double Integer to Real Box and Parameters

DI R
DI_R
IN DINT I, Q, M, D, L or Value to be converted
EN OUT constant
IN ENO
OUT REAL I, Q, M, D, L Result

state of I0.0 is 1. The contents of memory
DI_R
double word MD8 is read as an integer
and converted to a real number. The result
I0.0 EN OUT MD12 is stored in memory double word MD12. If
Q4.0
the conversion is not executed, the signal
MD8 IN ENO =
state of output Q4.0 is 0 (ENO=EN).
Status Word Bits

writes 1 – – – – 0 1 1 1
Figure 10-7 Double Integer to Real

10-8 C79000-G7076-C566-01
10.8 Ones Complement Integer
Description The Ones Complement Integer instruction reads the content of the input
parameter IN and performs the Boolean word logic instruction Exclusive Or
Word (see Section 11.6) masked by FFFFH, so that the value of every bit is
inverted. The output parameter OUT contains the result. ENO always has the
Table 10-8 Ones Complement Integer Box and Parameters

INV I
INV_I
IN INT I, Q, M, D, L or Input value
EN OUT constant
IN ENO OUT INT I, Q, M, D, L Ones complement of the integer

INV_I state of I0.0 is 1. The value of every bit in
MW8 is inverted.
MW8 = 01000001 10000001 →
I0.0 EN OUT MW10 MW10 = 10111110 01111110
Q4.0 The conversion is not executed when the
MW8 IN ENO = signal state of I0.0 is 0 and Q4.0 is 0 (ENO
= EN).
Status Word Bits

writes 1 – – – – 0 1 1 1
Figure 10-8 Ones Complement Integer

C79000-G7076-C566-01 10-9
10.9 Ones Complement Double Integer
Description The Ones Complement Double Integer instruction reads the content of the
input parameter IN and performs the Boolean word logic operation Exclusive
Or Word (see Section 11.6) masked by FFFF FFFFH, so that the value of
every bit is inverted. The output parameter OUT contains the result. ENO
always has the same signal state as EN.
Table 10-9 Ones Complement Double Integer Box and Parameters

INV DI
INV_DI
IN DINT I, Q, M, D, L or Input value
EN OUT
constant
IN ENO
OUT DINT I, Q, M, D, L Ones complement of the double
integer
The conversion is executed if the signal state of

I0.0 is 1. The value of every bit of memory double
INV_DI
word MD8 is inverted:
I0.0 EN OUT MD12 MD8 = F0FF FFF0 → MD12 = 0F00 000F
Q4.0
MD8 IN ENO = The conversion is not executed when I0.0 is 0 and
Q4.0 is 0 (ENO = EN).
Status Word Bits

writes 1 – – – – 0 1 1 1
Figure 10-9 Ones Complement Double Integer

10-10 C79000-G7076-C566-01
10.10 Twos Complement Integer
Description The Twos Complement Integer instruction reads the content of the input
parameter IN and changes the sign (for example, from a positive value to a
negative value). The output parameter OUT contains the result. The signal
state of EN is and ENO is always the same except when the signal state of
EN is 1 and an overflow occurs. In this case, the signal state of ENO is 0.
Table 10-10 Twos Complement Integer Box and Parameters

NEG I
NEG_I
IN INT I, Q, M, D, L or Input value
EN OUT constant
IN ENO OUT INT I, Q, M, D, L Twos complement of the integer
The conversion is executed if the signal state

of I0.0 is 1. The value of memory word MW8
is output at OUT to memory word MW10 with
NEG_I the opposite sign:
I0.0 EN OUT MW10
Example:MW8 = +10 → MW10 = – 10
Q4.0
MW8 IN ENO = If the signal state of EN is 1 and an overflow
occurs, ENO is 0 and the signal state of Q4.0
is 0. If the conversion is not executed,
Q4.0 is 0 (ENO = EN).
Status Word Bits

Figure 10-10 Twos Complement Integer

C79000-G7076-C566-01 10-11
10.11 Twos Complement Double Integer
Description The Twos Complement Double Integer instruction reads the content of the
input parameter IN and changes the sign (for example, from a positive value
to a negative value). The output parameter OUT contains the result. The
signal state of EN is and ENO is always the same except when the signal
state of EN is 1 and an overflow occurs. In this case, the signal state of ENO
is 0.
Table 10-11 Twos Complement Double Integer Box and Parameters

NEG DI
NEG_DI
IN DINT I, Q, M, D, L or Input value
EN OUT constant
IN ENO OUT DINT I, Q, M, D, L Twos complement of the double
integer
The conversion is executed if the signal state of I0.0

is 1. The value of memory double word MD8 is
NEG_DI output at OUT to memory double word MD10 with
the opposite sign:
I0.0 EN OUT MD12
Q4.0 Example:MD8 = +60 000 → MW10 = – 60 000
MD8 IN ENO =
If the signal state of EN is 1 and an overflow occurs,
ENO is 0 and the signal state of Q4.0 is 0. If the
conversion is not executed, Q4.0 is 0 (ENO = EN).
Status Word Bits

Figure 10-11 Twos Complement Double Integer

10-12 C79000-G7076-C566-01
10.12 Negate Real Number
Description The Negate Real Number instruction reads the content of the input parameter
IN and inverts the sign bit (the instruction changes the sign of the number. for
example, from 0 for plus to 1 for minus). The bits of the exponent and
mantissa remain the same. The output parameter OUT provides the result.
ENO always has the same signal state as EN except when the signal state of
EN is 1 and an overflow occurs. In this case, the signal state of ENO is 0.
Table 10-12 Negate Real Number Box and Parameters

NEG R
NEG_R
IN REAL I, Q, M, D, L or Input value
EN OUT
constant
IN ENO OUT REAL I, Q, M, D, L The result is the negated input value.
The conversion is executed if the signal state of

I0.0 is 1. The value of memory double word MD8
NEG_R is output at OUT to memory double word MD12
with the opposite sign as shown in the following
I0.0 EN OUT MD12 example:
Q4.0
MD8 IN ENO = MD8 = + 6.234 x 10–3 → MD12 = – 6.234 x 10–3
If the conversion is not executed, the signal state

of output Q4.0 is 0 (ENO = EN).
Status Word Bits

writes x – – – – 0 x x 1
Figure 10-12 Negate Real Number

C79000-G7076-C566-01 10-13
10.13 Round to Double Integer
Description The Round to Double Integer instruction reads the content of the input
parameter IN as a real number and converts this number to a double integer.
The result is the nearest integer and is contained in output parameter OUT. If
the fraction is x.5, the number is rounded to the even number (for example:
2.5 –> 2, 1.5 –> 2). If an overflow occurs, ENO is set to 0. If the input value
is not a real number, the OV bit and the OS bit have the value 1 and ENO has
the value 0.
Table 10-13 Round to Double Integer Box and Parameters

ROUND
IN REAL I, Q, M, D, L or Value to be rounded
EN OUT constant
IN ENO OUT DINT I, Q, M, D, L IN rounded to the next double
integer
The conversion is executed if I0.0 is 1. The

content of memory double word MD8 is read
as a real number and converted to a double
ROUND integer. The result of this round-to-nearest
I0.0 EN OUT MD12 function is stored in memory double word
MD12. If an overflow occurs, the signal state
Q4.0
of output Q4.0 is 0. If the signal state at input
MD8 IN ENO = EN is 0 (meaning that the conversion is not
executed), the signal state of output Q4.0 is
also 0.
Status Word Bits

Figure 10-13 Round to Double Integer

10-14 C79000-G7076-C566-01
10.14 Truncate Double Integer Part
Description The Truncate Double Integer Part instruction reads the content of the input
parameter IN as a real number and converts this number to a double integer
(for example 1.5 becomes 1). The result is the integer component of the real
number). The output parameter OUT contains the result. If an overflow
occurs, ENO is set to 0. If the input value is not a real number, the OV bit
and the OS bit have the value 1 and ENO has the value 0.
Table 10-14 Truncate Double Integer Part Box and Parameters

TRUNC
IN REAL I, Q, M, D, L or Value to be truncated
EN OUT constant
IN ENO OUT DINT I, Q, M, D, L Integer component of IN

double word MD8 is read as a real number
TRUNC and converted to a double integer
according to the “round to zero principle”.
I0.0 EN OUT MD12 The integer component is the result and is
Q4.0 stored in memory double word MD12. If an
MD8 IN ENO = overflow occurs, the signal state of output
Q4.0 is 0. If the signal state at input EN is 0
(meaning that the conversion is not
executed), the signal state of output Q4.0 is
also 0.
Status Word Bits

Figure 10-14 Truncate Double Integer Part

C79000-G7076-C566-01 10-15
10.15 Ceiling
Description The Ceiling instruction reads the content of the input parameter IN as a real
number and converts this number to a double integer (for example: +1.2 –>
+2; –1.5 –> –1). The result is the lowest integer which is greater than or
equal to the specified real number. The output parameter OUT contains the
result. If an overflow occurs, ENO is 0. If the input value is not a real
number, the OV bit and the OS bit have the value 1 and ENO has the value 0.
Table 10-15 Ceiling Box and Parameters

CEIL
IN REAL I, Q, M, D, L or Value to be converted
EN OUT constant
IN ENO OUT DINT I, Q, M, D, L Result
The conversion is executed if I0.0 is 1.The

content of memory double word MD8 is read as
CEIL a real number and converted to a double
integer by rounding to the next higher (or equal)
I0.0 EN OUT MD12 whole number. The result is stored in memory
Q4.0 double word MD12. If an overflow occurs, the
MD8 IN ENO = signal state of output Q4.0 is 0. If the signal
state at input EN is 0 (meaning that the
conversion is not executed), the signal state of
output Q4.0 is also 0.
Status Word Bits

Figure 10-15 Ceiling

10-16 C79000-G7076-C566-01
10.16 Floor
Description The Floor instruction reads the content of the input parameter IN as a real
number and converts this number to a double integer. The result is the
highest integer which is lower than or equal to the specified real number. The
output parameter OUT contains the result. If an overflow occurs, ENO is set
to 0. If the input value is not a real number, the OV bit and the OS bit have
the value 1 and ENO has the value 0.
Table 10-16 Floor Box and Parameters

FLOOR
IN REAL I, Q, M, D, L or Value to be converted
EN OUT constant
IN ENO OUT DINT I, Q, M, D, L Result
The conversion is executed if I0.0 is 1. The

content of memory double word MD8 is read as
FLOOR a real number and converted to a double
integer by rounding to the next lower (or equal)
I0.0 EN OUT MD12 whole number. The result is stored in memory
Q4.0 double word MD12. If an overflow occurs, the
MD8 IN ENO signal state of output Q4.0 is 0. If the signal
=
state at input EN is 0 (meaning that the
conversion is not executed), the signal state of
output Q4.0 is also 0.
Status Word Bits

Figure 10-16 Floor

C79000-G7076-C566-01 10-17

10-18 C79000-G7076-C566-01
Word Logic Instructions 11
11.2 (Word) AND Word 11-3
11.3 (Word) AND Double Word 11-4
11.4 (Word) OR Word 11-5
11.5 (Word) OR Double Word 11-6
11.6 (Word) Exclusive OR Word 11-7
11.7 (Word) Exclusive OR Double Word 11-8

C79000-G7076-C566-01 11-1
Word Logic Instructions
11.1 Overview
What Are Word logic instructions compare pairs of words (16 bits) and double words
Word Logic (32 bits) bit by bit, according to Boolean logic. The following instructions
Instructions? are available for performing word logic operations:
(Word) AND Word: This instruction combines two words bit by bit,
according to the AND truth table.
(Word) AND Double Word: This instruction combines two double words
bit by bit, according to the AND truth table.
(Word) OR Word: This instruction combines two words bit by bit,
according to the OR truth table.
(Word) OR Double Word: This instruction combines two double words bit
by bit, according to the OR truth table.
(Word) Exclusive OR Word: This instruction combines two words bit by
bit, according to the Exclusive OR truth table.
(Word) Exclusive OR Double Word: This instruction combines two
double words bit by bit, according to the Exclusive OR truth table.

11-2 C79000-G7076-C566-01
11.2 (Word) AND Word
Description The (Word) AND Word instruction is activated by signal state 1 at the Enable
input (EN) and combines the two digital values at inputs IN1 and IN2 bit by
bit according to the AND truth table. The values are interpreted as pure bit
patterns. The result can be scanned at output OUT. ENO has the same signal
state as EN.
The value of the result at output OUT relative to 0 affects the CC1 bit of the
status word as follows:
If the result at output OUT is not equal to 0, the CC1 bit of the status
word is set to 1 .
If the result at output OUT is 0, the CC1 bit of the status word is set to 0.
Table 11-1 (Word) AND Word Box and Parameters

WAND W
WAND_W IN1 WORD I, Q, M, D, L or First value of the logic operation
EN constant
IN1 OUT IN2 WORD I, Q, M, D, L or Second value of the logic operation
IN2 constant
ENO
OUT WORD I, Q, M, D, L Result of the logic operation
The instruction is activated when the

signal state of I0.0 is 1. Only bits 0 to 3
WAND_W are relevant, all other bits of MW0 are
I0.0 EN masked.
IN1 = 0101010101010101
MW0 IN1 OUT MW2 IN2 = 0000000000001111
Q4.0
OUT = 0000000000000101
2# 0000000000001111 IN2 ENO =
Q4.0 is 1 if the instruction is executed.
Status Word Bits

writes 1 x 0 0 – x 1 1 1
Figure 11-1 (Word) AND Word

C79000-G7076-C566-01 11-3
11.3 (Word) AND Double Word
Description The (Word) AND Double Word instruction is activated by signal state 1 at the
Enable input (EN) and combines the two digital values at inputs IN1 and IN2
bit by bit according to the AND truth table. The values are interpreted as
pure bit patterns. The result can be scanned at output OUT. ENO has the
word is set to 1 .
Table 11-2 (Word) AND Double Word Box and Parameters

WAND_DW
WAND DW IN1 DWORD I, Q, M, D, L or First value of the logic operation
EN constant
IN1 OUT IN2 DWORD I, Q, M, D, L or Second value of the logic operation
constant
IN2 ENO
OUT DWORD I, Q, M, D, L Result of the logic operation
The instruction is activated when I0.0 is 1. Only bits 0

WAND_DW to 11 are relevant, all other bits of MD4 are masked.
I0.0 EN IN1 = 0101010101010101 0101010101010101
IN2 = 0000000000000000 0000111111111111
MD0 IN1 OUT MD4 OUT = 0000000000000000 0000010101010101
Q4.0
DW#16#FFF IN2 ENO = Q4.0 is 1 if the instruction is executed.
Status Word Bits

writes 1 x 0 0 – x 1 1 1
Figure 11-2 (Word) AND Double Word

11-4 C79000-G7076-C566-01
11.4 (Word) OR Word
Description The (Word) OR Word instruction is activated by signal state 1 at the Enable
input (EN) and combines the two digital values at inputs IN1 and IN2 bit by
bit according to the OR truth table. The values are interpreted as pure bit
patterns. The result can be scanned at output OUT. ENO has the same signal
state as EN.
word is set to 1 .
Table 11-3 (Word) OR Word Box and Parameters

WOR W
WOR_W IN1 WORD I, Q, M, D, L or First value of the logic operation
EN constant
IN1 OUT IN2 WORD I, Q, M, D,or Second value of the logic operation
IN2 ENO constant L
The instruction is activated when I0.0 is 1. The

bits in MW0 and in the constant are ORed and
bits 0 to 3 set to 1, all other bits of MW0 are
WOR_W entered unchanged in MW2
I0.0 EN
IN1 = 0101010101010101
MW0 IN1 OUT MW2 IN2 = 0000000000001111
Q4.0
2#0000000000001111 IN2 OUT = 0101010101011111
ENO =
Status Word Bits

writes 1 x 0 0 – x 1 1 1
Figure 11-3 (Word) OR Word

C79000-G7076-C566-01 11-5
11.5 (Word) OR Double Word
Description The (Word) OR Double Word instruction is activated by signal state 1 at the
bit by bit according to the OR truth table. The values are interpreted as pure
bit patterns. The result can be scanned at output OUT. ENO has the same
signal state as EN.
word is set to 1 .
Table 11-4 (Word) OR Double Word Box and Parameters

WOR DW
WOR_DW IN1 DWORD I, Q, M, D, L or First value of the logic operation
EN constant
IN2 constant
ENO
The instruction is activated when I0.0 is 1. The bits in

MD0 and in the constant are ORed and bits 0 to 11
WOR_DW set to 1, all other bits of MD0 are entered unchanged
in MD4
I0.0 EN
IN1 = 0101010101010101 0101010101010101
MD0 IN1 OUT MD4 IN2 = 0000000000000000 0000111111111111
Q4.0 OUT = 0101010101010101 0101111111111111
DW#16#FFF IN2 ENO =
Status Word Bits

writes 1 x 0 0 – x 1 1 1
Figure 11-4 (Word) OR Double Word

11-6 C79000-G7076-C566-01
11.6 (Word) Exclusive OR Word
Description The (Word) Exclusive OR Word instruction is activated by signal state 1 at the
bit by bit according to the EXCLUSIVE OR truth table. The values are
interpreted as pure bit patterns. The result can be scanned at output OUT.
ENO has the same signal state as EN.
The value of the result at output OUT relative to 0 affects the CC1 bit in the
If the result at output OUT is not equal to 0, the CC1 bit in the status
word is set to 1.
If the result at output OUT is 0, the CC1 bit in the status word is set to 0.
Table 11-5 (Word) Exclusive OR Word Box and Parameters

WXOR_W
WXOR W IN1 WORD I, Q, M, D, L or First value of the logic operation
EN constant
IN1 OUT IN2 WORD I, Q, M, D, L or Second value of the logic operation
IN2 ENO constant
The instruction is activated when input I0.0

WXOR_W is 1.
I0.0 EN
IN1 = 0101010101010101
MW0 IN1 OUT MW2 IN2 = 0000000000001111
Q4.0 OUT = 0101010101011010
2#0000000000001111 IN2 ENO =
Status Word Bits

writes 1 x 0 0 – x 1 1 1
Figure 11-5 (Word) Exclusive OR Word

C79000-G7076-C566-01 11-7
11.7 (Word) Exclusive OR Double Word
Description The (Word) Exclusive OR Double Word instruction is activated by signal state
1 at the Enable input (EN) and combines the two digital values at inputs IN1
and IN2 bit by bit according to the EXCLUSIVE OR truth table. The values
are interpreted as pure bit patterns. The result can be scanned at output OUT.
ENO has the same signal state as EN.
The value of the result at output OUT relative to 0 affects the CC1 bit in the
If the result at output OUT is not equal to 0, the CC1 bit in the status
word is set to 1.
If the result at output OUT is 0, the CC1 bit in the status word is set to 0.
Table 11-6 (Word) Exclusive OR Double Word Box and Parameters

WXOR DW
WXOR_DW IN1 DWORD I, Q, M, D, L or First value of the logic operation
EN constant
IN2 ENO constant
The instruction is activated when input I0.0 is 1.

WXOR_DW
I0.0 EN IN1 = 0101010101010101 0101010101010101
IN2 = 0000000000000000 0000111111111111
MD0 IN1 OUT MD4 OUT = 0101010101010101 0101101010101010
Q4.0
DW#16#FFF IN2 ENO = Q4.0 is 1 if the instruction is executed.
Status Word Bits

writes 1 x 0 0 – x 1 1 1
Figure 11-6 (Word) Exclusive OR Double Word

11-8 C79000-G7076-C566-01
Shift and Rotate Instructions 12
Overview 12.1 Shift Instructions 12-2
12.2 Rotate Instructions 12-10

C79000-G7076-C566-01 12-1
Shift and Rotate Instructions
12.1 Shift Instructions
Description You can use the Shift instructions to move the contents of input IN bit by bit
to the left or the right (see Section 2.3). Shifting n bits to the left multiplies
the contents of input IN by 2 to the power n (2n); shifting n bits to the right
divides the contents of input IN by 2 to the power n (2n). For example, if you
shift the binary equivalent of the decimal value 3 to the left by 3 bits, you
obtain the binary equivalent of the decimal value 24. If you shift the binary
equivalent of the decimal value 16 to the right by 2 bits, you obtain the
binary equivalent of the decimal value 4.
The number that you supply for input parameter N indicates the number of
bits by which the value is shifted. The bit places that are vacated by the Shift
instruction are either padded with zeros or with the signal state of the sign bit
(0 stands for positive and 1 stands for negative). The signal state of the bit
that is shifted last is loaded into the CC1 bit of the status word (see
Section 2.3). The CC0 and OV bits of the status word are reset to 0. You can
use jump instructions to evaluate the CC1 bit.
The following Shift instructions are available:
Shift Left Word, Shift Left Double Word
Shift Right Word, Shift Right Double Word
Shift Right Integer, Shift Right Double Integer
Shift Left Word A signal state of 1 at the Enable input (EN) activates the Shift Left Word
instruction. This instruction shifts bits 0 to 15 of input IN bit by bit to the
left.
Input N specifies the number of bits by which to shift the value. If N is
higher than 16, the command writes 0 to output OUT and sets the CC0 and
OV bits of the status word to 0. The bit positions at the right are padded with
zeros. The result of the shift operation can be scanned at output OUT.
The operation triggered by this instruction always resets the CC0 and OV bits
of the status word to 0 if the value of N is not equal to 0. ENO has the same
signal state as EN.

12-2 C79000-G7076-C566-01
Parameters: 15... ...8 7... ...0

IN 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1
N 6 places
OUT 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0
These six bits The vacated places

are lost. are padded with
zeros.
Figure 12-1 Shifting the Bits of Input IN Six Bits to the Left
Table 12-1 Shift Left Word Box and Parameters

EN BOOL I, Q, M, L, D, T, C Enable input
SHL_W IN WORD I, Q, M, L, D Value to be shifted
EN N WORD I, Q, M, L, D Number of bit positions by which
IN OUT the value will be shifted
N OUT WORD I, Q, M, L, D Result of the shift instruction

ENO
ENO BOOL I, Q, M, L, D Enable output
The instruction is activated if the signal

state of I0.0 is 1.
SHL_W
I0.0 EN Memory word MW0 is shifted to the left by
the number of bits specified in memory
MW0 IN OUT MW4
Q4.0 word MW2.
MW2 N ENO S
The result is entered in memory word
MW4.
Status Word Bits

writes x x x x – x x x 1
Figure 12-2 Shift Left Word

C79000-G7076-C566-01 12-3
Shift Left Double A signal state of 1 at the Enable input (EN) activates the Shift Left Double
Word Word instruction. This instruction shifts bits 0 to 31 of input IN bit by bit to
the left. Input N specifies the number of bits by which the value will be
shifted. If N is greater than 32, the command writes 0 to output OUT and sets
the CC0 and OV bits of the status word to 0. The vacated bit positions at the
right are padded with zeros. The result of the shift operation can be scanned
at output OUT.
of the status word to 0 if the value of N is not equal to 0. ENO has the same
signal state as EN.
Table 12-2 Shift Left Double Word Box and Parameters

SHL_DW
SHL DW
EN IN DWORD I, Q, M, L, D Value to be shifted
N WORD I, Q, M, L, D Number of bit positions by which
IN OUT
the value will be shifted
N ENO OUT DWORD I, Q, M, L, D Result of the shift instruction

state of I0.0 is 1.
SHL_DW
Memory double word MD0 is shifted to
I0.0 EN the left by the number of bits specified
in memory word MW4.
MD0 IN OUT MD10
Q4.0
MW4 N The result is entered in memory
ENO S
double word MD10.
Status Word Bits

Figure 12-3 Shift Left Double Word

12-4 C79000-G7076-C566-01
Shift Right Word A signal state of 1 at the Enable input (EN) activates the Shift Right Word
right. Bits 16 to 31 are not affected. Input N specifies the number of bits by
which the value will be shifted. If N is greater than 16, the command writes 0
to output OUT and resets the CC0 and OV bits of the status word to 0. The
vacated bit positions at the left are padded with zeros. The result of the shift
operation can be scanned at output OUT.
of the status word to 0 if N is not equal to zero. ENO has the same signal
state as EN.
Table 12-3 Shift Right Word Box and Parameters

SHR_W
SHR W
IN WORD I, Q, M, L, D Value to be shifted
EN
N ENO OUT WORD I, Q, M, L, D Result of the shift instruction

state of I0.0 is 1.
SHR_W
I0.0 EN Memory word MW0 is shifted to the right
by the number of bits specified in memory
MW0 IN OUT MW4 word MW2.
Q4.0
MW2 N ENO S
The result is entered in memory word
MW4.
Status Word Bits

Figure 12-4 Shift Right Word

C79000-G7076-C566-01 12-5
Shift Right Double A signal state of 1 at the Enable input (EN) activates the Shift Right Double
Word Word instruction. This instruction shifts bits 0 to 31 of input IN bit by bit to
the right. Input N specifies the number of bits by which the value will be
shifted. If N is higher than 32, the command writes 0 to output OUT and
resets the CC0 and OV bits of the status word to 0. The vacated bit positions
at the left are padded with zeros. The result of the shift operation can be
scanned at output OUT.
state as EN.
Parameters: 31... ...16 15... ...0

IN 1111 1111 0101 0101 1010 1010 1111 1111
N 3 places
OUT 0001 1111 1110 1010 1011 0101 0101 1111 111
The vacated bit

positions are padded These three
with zeros. bits are lost.
Figure 12-5 Shifting Bits of Input IN Three Bits to the Right
Table 12-4 Shift Right Double Word Box and Parameters

SHR_DW
SHR DW
IN DWORD I, Q, M, L, D Value to be shifted
EN
N ENO OUT DWORD I, Q, M, L, D Result of the shift instruction

12-6 C79000-G7076-C566-01

state of I0.0 is 1.
SHR_DW
Memory double word MD0 is shifted to
I0.0 EN the right by the number of bits specified
in memory word MW4.
MD0 IN OUT MD10
Q4.0
MW4 N ENO S The result is entered in MD10.
Status Word Bits

Figure 12-6 Shift Right Double Word
Shift Right Integer A signal state of 1 at the Enable input (EN) activates the Shift Right Integer
right. Input N specifies the number of bits by which the value will be shifted.
If N is higher than 16, the command behaves as if N were 16. The bit
positions at the left are padded according to the signal state of bit 15 (the sign
of an integer number). They are filled with zeros if the number is positive,
and with ones if it is negative. The result of the shift operation can be
scanned at output OUT.
state as EN.
Parameters: 15... ...8 7... ...0
IN 1 0 1 0 1 1 1 1 0 0 0 0 1 0 1 0
N Sign bit 4 places
OUT 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 1 0 1 0
The vacated bit

positions are padded
with the signal state of These four bits
the sign bit. are lost.
Figure 12-7 Shifting Bits of Input IN Four Bits to the Right with Sign

C79000-G7076-C566-01 12-7
Table 12-5 Shift Right Integer Box and Parameters

SHR_II
SHR
IN INT I, Q, M, L, D Value to be shifted
EN
N ENO OUT INT I, Q, M, L, D Result of the shift instruction

state of I0.0 is 1.
SHR_I
Memory word MW0 is shifted to the right
I0.0 EN by the number of bits specified in memory
word MW2.
MW0 IN OUT MW4 Q4.0
MW2 N ENO S The result is entered in memory word
MW4.
Status Word Bits

Figure 12-8 Shift Right Integer

12-8 C79000-G7076-C566-01
Shift Right Double A signal state of 1 at the Enable input (EN) activates the Shift Right Double
Integer Integer instruction. This instruction shifts the entire contents of input IN bit
by bit to the right. Input N specifies the number of bits by which the value
will be shifted. If N is higher than 32, the command behaves as if N were 32.
The bit positions at the left are padded according to the signal state of bit 31
(the sign of a double integer number). They are filled with zeros if the
number is positive, and with ones if it is negative. The result of the shift
operation can be scanned at output OUT.
state as EN.
Table 12-6 Shift Right Double Integer Box and Parameters

SHR_DI IN DINT I, Q, M, L, D Value to be shifted
EN N WORD I, Q, M, L, D Number of bit positions by which
N ENO OUT DINT I, Q, M, L, D Result of the shift instruction

state of I0.0 is 1.
SHR_DI Memory double word MD0 is shifted to

I0.0 EN the right by the number of bits specified
in memory word MW4.
MD0 IN OUT MD10
Q4.0
The result is entered in memory double
MW4 N ENO S word MD10.
Status Word Bits

Figure 12-9 Shift Right Double Integer

C79000-G7076-C566-01 12-9
12.2 Rotate Instructions
Description You can use the Rotate instructions to rotate the entire contents of input IN
bit by bit to the left or to the right. The vacated bit positions are filled with
the signal states of the bits that are shifted out of input IN.
The number that you specify for input parameter N is the number of bits by
which the value will be rotated.
Depending on the instruction, rotation uses the CC1 bit of the status word
(see Section 2.3). The CC0 bit of the status word is reset to 0.
The following Rotate instructions are available:
Rotate Left Double Word
Rotate Right Double Word
Rotate Left Double A signal state of 1 at the Enable input (EN) activates the Rotate Left Double
Word Word instruction. This instruction rotates the entire contents of input IN bit
by bit to the left. Input N specifies the number of bits by which to rotate. If N
is higher than 32, the double word is rotated ((N–1) modulo 32) +1) places.
The bit positions at the right are filled with the signal states of the bits
rotated. The result of the rotate operation can be scanned at output OUT.
state as EN.
Parameters: 31... ...16 15... ...0
IN 1111 0000 1010 1010 0000 1111 0000 1111
N 3 places
OUT 111 1000 0101 0101 0000 0111 1000 0111 1111
The signal states of the three

bits that are shifted out are These three bits are lost.
inserted in the vacated
positions.
Figure 12-10 Rotating Bits of Input IN Three Bits to the Left

12-10 C79000-G7076-C566-01
Table 12-7 Rotate Left Double Word Box and Parameters

ROL_DW
ROL DW IN DWORD I, Q, M, L, D Value to be rotated
EN
IN OUT the value will be rotated
N ENO OUT DWORD I, Q, M, L, D Result of the rotate instruction

state of I0.0 is 1.
ROL_DW
Memory double word MD0 is rotated to the
I0.0 EN left by the number of bits specified in
memory word MW4.
MD0 IN OUT MD10
Q4.0
MW4 N ENO The result is entered in memory double
S
word MD10.
Status Word Bits

Figure 12-11 Rotate Left Double Word
Rotate Right A signal state of 1 at the Enable input (EN) activates the Rotate Right Double
Double Word Word instruction. This instruction rotates the entire contents of input IN bit
by bit to the right. Input N specifies the number of bits by which the value
will be rotated. The value of N can be between 0 and 31. If N is higher than
32, the double word is rotated ((N–1) modulo 32) +1) places. The bit
positions at the left are filled with the signal states of the bits rotated. The
result of the rotate operation can be scanned at output OUT.
state as EN.

C79000-G7076-C566-01 12-11
Parameters: 31... ...16 15... ...0
IN 1010 1010 0000 1111 0000 1111 0101 0101
N 3 places
OUT 1011 0101 0100 0001 1110 0001 1110 1010 101
The signal states of

the three bits that are
shifted out are inserted
in the vacated places.
Figure 12-12 Rotating Bits of Input IN Three Bits to the Right
Table 12-8 Rotate Right Double Word Box and Parameters

ROR_DW
ROR DW IN DWORD I, Q, M, L, D Value to be rotated
EN
IN OUT the value will be rotated
N ENO OUT DWORD I, Q, M, L, D Result of the rotate instruction


state of I0.0 is 1.
ROR_DW
Memory double word MD0 is rotated to
I0.0 EN the right by the number of bits specified in
MD0 IN OUT memory word MW4.
MD10
Q4.0
MW4 N ENO S The result is entered in memory double
word MD10.
Status Word Bits

Figure 12-13 Rotate Right Double Word

12-12 C79000-G7076-C566-01
Data Block Instructions 13
Overview 13.1 Open Data Block 13-2

C79000-G7076-C566-01 13-1
Data Block Instructions
13.1 Open Data Block
Description You can use the Open Data Block instruction to open an existing data block
as a shared data block (DB) or instance data block (DI). The number of the
data block is transferred to the DB or DI register. The subsequent DB and DI
commands access the corresponding blocks depending on the register
contents.
Table 13-1 Open Data Block Box and Parameters with SIMATIC Mnemonics

<DB number> or Number of the BLOCK_DB DB, DI Number of the DB or DI;
<DI number> DB or DI Range depends on the
AUF CPU.
Table 13-2 Open Data Block Box and Parameters with International Mnemonics

<DB number> or Number of the BLOCK_DB DB, DI Number of the DB or DI;
<DI number> DB or DI Range depends on the
OPN CPU.
Network 1
DB10 is the currently opened data block. The
DB10 scan at DBX0.0 therefore refers to bit 0 of
OPN data byte 0 of data block DB10. The signal
state of this bit is assigned to output Q 4.0.
Network 2
Q 4.0
DBX 0.0 =
Status Word Bits

writes – – – – – – – – –
The instruction does not change the bits in the status word.
Figure 13-1 Open Data Block

13-2 C79000-G7076-C566-01
Jump Instructions 14
14.2 Unconditional Jump in a Block 14-3
14.3 Conditional Jump in a Block 14-4
14.4 Jump-If-Not 14-5
14.5 Jump Label 14-6

C79000-G7076-C566-01 14-1
Jump Instructions
14.1 Overview
Jump Label as The address of a Jump instruction is a label. A label consists of a maximum
Address of four characters. The first character must be a letter; the other characters
can be letters or numbers (for example, SEG3). The jump label indicates the
destination to which you want the program to jump.
You enter the label above the jump box (see Figure 14-1).
Jump Label as The destination label must be at the beginning of a network. You enter the
Destination destination label at the beginning of the network by selecting LABEL from
the FBD list box. An empty box appears. In the box, you type the name of
the label (see Figure 14-1).
Network1
SEG3
JMP
Network 2
Q4.0
I0.1 =
.
.
.
Network X
SEG3
Q4.1
I0.4 R
Figure 14-1 Jump Label as Address and Destination

14-2 C79000-G7076-C566-01
Jump Instructions
14.2 Unconditional Jump in a Block
Description The Unconditional Jump in a Block instruction corresponds to a “go to label”

instruction. None of the instructions between the jump operation and the
label is executed.
You can use this instruction in all logic blocks, for example in organization
blocks (OBs), function blocks (FBs) and functions (FCs).
There must not be any logic operation before the Unconditional Jump in a
Block box.
Table 14-1 Unconditional Jump in a Block Box and Parameters

Name of a jump – – The address specifies the label to
<address> label which the program will jump
JMP unconditionally.
Network 1
CAS1
JMP The jump is always executed. None of the instructions between
??.?
the jump instruction and the label is executed.
.
.
.
Network X
CAS1
Q4.1
I0.4 R
Status Word Bits

writes – – – – – – – – –
The instruction does not change the bits in the status word.
Figure 14-2 Unconditional Jump: Jump to Label

C79000-G7076-C566-01 14-3
Jump Instructions
14.3 Conditional Jump in a Block
Description The Conditional Jump in a Block instruction corresponds to a “go to label”

instruction if the RLO is 1. The FBD element “Unconditional Jump” is also
used for this operation, however it is made conditional by the preceding logic
operation. The conditional jump is only executed when the result of this logic
operation is 1. None of the instructions between the jump operation and the
label is executed.
Table 14-2 Conditional Jump in a Block Box and Parameters

Name of a – – The address specifies the label to
<address> jump label which the program will jump if the
JMP RLO is 1.
Network 1
CAS1
I0.0 JMP
If the signal state of input I0.0 is 1, the jump to label CAS1
is executed. The instruction to reset output Q4.0 is not
executed, even if the signal state of input I0.3 is 1.
Network 2
Q4.0
I0.3 R
Network 3
CAS1
Q4.1
I0.4 R
Status Word Bits

writes – – – – – 0 1 1 0
Figure 14-3 Conditional Jump: Jump in the Block If 1

14-4 C79000-G7076-C566-01
Jump Instructions
14.4 Jump-If-Not
Description The Jump-If-Not instruction corresponds to a “go to label” instruction that is

executed if the RLO is 0.
Table 14-3 Jump-If-Not Box and Parameters

Name of a jump – – The address specifies the label to
<address> label which the program will jump if the
JMPN RLO is 0.
Network 1
CAS1
I0.0 JMPN If the signal state of input I0.0 is 0, the jump to label CAS1
is executed. The instruction to reset output Q4.0 is not
executed, even if the signal state of input I0.3 is 1.
Network 2
None of the instructions between the jump operation and
Q4.0
the label is executed.
I0.3 R
Network 3
CAS1
Q4.1
I0.4 R
Status Word Bits

writes – – – – – 0 1 1 0
Figure 14-4 Jump-If-Not

C79000-G7076-C566-01 14-5
Jump Instructions
14.5 Jump Label
Description The jump label is the identifier for the destination of a jump instruction. A
jump label must exist for every jump or jump-if-not instruction (JMP or
JMPN).
Format Description
4 characters: first character must be a letter
LABEL remaining characters can be letters or numbers
Network 1
CAS1
I0.0 JMP If I0.0 = 1, the jump to label CAS1 is executed.
Due to the jump, the operation “Reset output” at Q 4.0 is not

Network 2 executed even if I0.3 = 1.
Q4.0
I0.3 R
Network 3
CAS1
Q4.1
I0.4 R
Figure 14-5 Jump Label

14-6 C79000-G7076-C566-01
Status Bit Instructions 15
15.2 Exception Bit Binary Result 15-3
15.3 Result Bits 15-4
15.4 Exception Bit Unordered 15-6
15.5 Exception Bit Overflow 15-7
15.6 Exception Bit Overflow Stored 15-8

C79000-G7076-C566-01 15-1
Status Bit Instructions
15.1 Overview
Description The status bit instructions are bit logic instructions (see Chapter 4) that work
with the bits of the status word (see Section 2.3). Each of these instructions
reacts to one of the following conditions that is indicated by one or more bits
of the status word:
The binary result bit is set (has a signal state of 1).
The result of a math function is relative to 0 in one of the following ways:
– Greater than 0 (>0)
– Less than 0 (<0)
– Greater than or equal to 0 (>=0)
– Less than or equal to 0 (<=0)
– Equal to 0 (==0)
– Not equal to 0 (<>0)
The result of a math function is unordered (invalid).
A math function produced an overflow.
In an AND operation, the status bit instructions combine the result of their
signal state checks with the previous result of logic operation according to
the And truth table (see Section 2.2 and Table 2-7). In an OR operation, the
OR truth table is used (see Section 2.2 and Table 2-8).
In this section, the Exception Bit Binary Result element, which checks the
signal state of the BR (Binary Result) bit of the status word, is shown in its
international and SIMATIC form.
Status Word The status word is a register in the memory of your CPU that contains bits
that you can reference in the address of bit and word logic instructions.
Figure 15-1 shows the structure of the status word. For more information on
the individual bits of the status word, see Section 2.3.
215... ...29 28 27 26 25 24 23 22 21 20
Figure 15-1 Structure of the Status Word
Parameters The FBD elements described in the following sections do not have any
selectable parameters.

15-2 C79000-G7076-C566-01
15.2 Exception Bit Binary Result
Description You can use the Exception Bit Binary Result instruction to check the signal
state of the BR bit (Binary Result) of the status word (see Section 2.3). In an
AND operation, the result of the check is combined with the previous RLO
according to the AND truth table (see Section 2.2 and Table 2-7). In an OR
operation, the OR truth table is used (see Section 2.2 and Table 2-8).
FBD Box Figure 15-2 shows the Exception Bit Binary Result box with SIMATIC and
international short names.
SIMATIC element International element
BIE BR
Figure 15-2 Exception Bit Binary Result Box
I0.0 >=1 Output Q4.0 is set if the signal state at input

I0.0 is 1 OR the signal state at input I0.2 is 0,
I0.2 & and, in addition to this RLO, the signal state
Q4.0 of the BR bit is 1.
BR S
Figure 15-3 Exception Bit Binary Result

C79000-G7076-C566-01 15-3
15.3 Result Bits
Description You can use the Result Bit instructions to determine the relationship of the
result of a math function to zero, in other words, whether the result is >0, <0,
>=0, <=0, ==0, or <>0 (see Table 15-1). The condition code bits of the status
word (CC 1 and CC 0, see Section 2.3) are evaluated. If the comparison
condition indicated in the address is fulfilled, the result of this signal state
check is 1.
In an AND operation, this instruction combines the result of its check with
the previous result of logic operation (RLO) according to the AND truth table
(see Section 2.2 and Table 2-7). In an OR operation, this instruction
combines the result of its check with the previous RLO according to the OR
truth table (see Section 2.2 and Table 2-8).
Table 15-1 Result Bits Boxes
FBD Element Description

The Result Bit instruction for greater than 0 determines whether or not the result of a
>0 math instruction is greater than 0. It checks the combination in the condition code bits
CC1 and CC0 in the status word to determine the relationship of a result to 0.
The Result Bit instruction for less than 0 determines whether or not the result of a math
<0 instruction is less than 0. It checks the combination in the condition code bits CC1 and
CC0 in the status word to determine the relationship of a result to 0.
The Result Bit instruction for greater than or equal to 0 determines whether or not the
>=0 result of a math instruction greater than or equal to 0. It checks the combination in the
condition code bits CC1 and CC0 in the status word to determine the relationship of a
result to 0.
The Result Bit instruction for less than or equal to 0 determines whether or not the result
<=0 of a math instruction is less than or equal to 0. It checks the combination in the condition
code bits CC1 and CC0 in the status word to determine the relationship of a result to 0.
The Result Bit instruction for equal to 0 determines whether or not the result of a math
== 0 instruction is equal to 0. It checks the combination in the condition code bits CC1 and
CC0 in the status word to determine the relationship of a result to 0.
The Result Bit instruction for not equal to 0 determines whether or not the result of a
<>0 math instruction is not equal to 0. It checks the combination in the condition code bits
CC1 and CC0 in the status word to determine the relationship of a result to 0.

15-4 C79000-G7076-C566-01
1) If the signal state at input I0.0 is 1, the SUB_I box

SUB_I is activated. If the value of input word IW0 is
greater than the value of input word IW2, the
I0.0 EN result of the math function IW0 – IW2 is greater
IW0 IN1 OUT MW10 than 0.
IW2 IN2 ENO & If the signal state of EN is 1 (activated) and an

Q4.0 error occurs while the instruction is being
>0 executed, the signal state of ENO is 0.
S
1) Output Q4.0 is set if the function is executed
correctly and the result is less than or equal to 0.
2) If the signal state of input I0.0 is 0 (not activated),
the signal state of both EN and ENO is 0.
SUB_I
I0.0 EN 2) Output Q4.0 is set if the function is executed
IW0 IN1 OUT MW10 correctly and the result is less than or equal to 0.
If the signal state of input I0.0 is 0 (not activated),
IW2 IN2 ENO & the signal state of both EN and ENO is 0.
Q4.0
≤0 S
Status Word Bits

writes – – – – – x x x 1
Figure 15-4 Result Bit for Greater than 0 and Negated Result Bit for Greater than 0

C79000-G7076-C566-01 15-5
15.4 Exception Bit Unordered
Description You can use the Exception Bit Unordered instruction to check whether or not
the result of a floating-point math function is unordered (in other words,
whether one of the values in the math function is not a valid floating-point
number). The condition code bits of the status word (CC 1 and CC 0, see
Section 2.3) are evaluated. If the result of the math function is unordered
(UO) the signal state check produces a result of 1. If the combination in CC 1
and CC 0 does not indicate unordered, the result of the signal state check is
0.
the previous result of logic operation (RLO, see Section 2.3) according to the
AND truth table (see Section 2.2 and Table 2-7). In an OR operation, the OR
truth table is used (see Section 2.2 and Table 2-8).
FBD Box
UO
Figure 15-5 Exception Bit Unordered Box
Network 1: If the signal state at input I0.0 is 1, the DIV_R

box is activated. If the value of either input
DIV_R double word ID0 or ID4 is not a valid
floating-point number, the floating-point math
I0.0 EN function is unordered.
ID0 IN1 OUT MD10 If the signal state of EN is 1 (activated) and
Q4.1 an error occurs while the instruction is being
ID4 IN2 ENO S executed, the signal state of ENO is 0.
Output Q4.0 is set if the function DIV_R is

Network 2: executed, but one of the values in the math
function is not a valid floating-point number. If
UO Q4.0 the signal state of input I0.0 is 0 (not
S activated), the signal state of both EN and
ENO is 0.
Figure 15-6 Exception Bit Unordered

15-6 C79000-G7076-C566-01
15.5 Exception Bit Overflow
Description You can use the Exception Bit Overflow instruction to detect an overflow
(OV) in the last math function. If, after the system executes a math function,
the result is outside the permitted negative range or outside the permitted
positive range, the OV bit in the status word (see Section 2.3) is set. The
instruction checks the signal state of this bit. This bit is reset if the math
functions were free of errors
the previous result of logic operation according to the AND truth table (see
Section 2.2 and Table 2-7). In an OR operation, the OR truth table is used
(see Section 2.2 and Table 2-8).
FBD Box
OV
Figure 15-7 Exception Bit Overflow Box
If the signal state at input I0.0 is 1, the SUB_I box is

Network 1: activated. If the result of the math function input word IW0
minus input word IW2 is outside the permitted range for an
SUB_I integer, the OV bit in the status word is set.
I0.0 EN
The result of a signal state check at OV is 1. Output Q4.0
IW0 IN1 OUT MW10 is set if the check at OV is 1 and the RLO of network 2 is 1
(if the RLO prior to output Q4.0 is 1).
IW2 IN2 ENO
If the signal state of input I0.0 is 0 (not activated), the
signal state of both EN and ENO is 0. If the signal state of
EN is 1 (activated) and the result of the math function is
Network 2: out of range, the signal state of ENO is 0.
I0.1 &
I0.2 >=1
I0.3 M 3.3
Network 3:
Q4.0
OV S
Figure 15-8 Exception Bit Overflow

C79000-G7076-C566-01 15-7
15.6 Exception Bit Overflow Stored
Description You can use the Exception Bit Overflow Stored instruction to recognize a
previous overflow (overflow stored, OS) in a math function. If, after the
system executes a math function, the result is outside the permitted negative
range or outside the permitted positive range, the OS bit in the status word
(see Section 2.3) is set. The instruction checks the signal state of this bit.
Unlike the OV (overflow) bit, the OS bit remains set even if later math
functions were executed free of errors (see Section 15.5).
the previous result of logic operation according to the AND truth table (see
Section 2.2 and Table 2-7). In an OR operation, the OR truth table is used
(see Section 2.2 and Table 2-8).
FBD Box
OS
Figure 15-9 Exception Bit Overflow Stored Box

15-8 C79000-G7076-C566-01
Network 1:
MUL_I If the signal state at input I0.0 is 1, the MUL_I box is

activated. If the signal state at input I0.1 is 1, the ADD_I box
I0.0 EN is activated. If the result of one of the math functions is
outside the permissible range for an integer, the OS bit in the
IW0 IN1 OUT MD8
status word is set.
IW2 IN2 ENO
The result of a signal state check at OS is 1 and output Q4.0
is set.
Network 2: Network 1: if the signal state of input I0.0 is 0 (not activated),

the signal state of both EN and ENO is 0. If the signal state of
ADD_I EN is 1 (activated) and the result of the math function is out
of range, the signal state of ENO is 0.
I0.1 EN
IW0 IN1 OUT MW12 Network 2: if the signal state of input I0.1 is 0 (not activated),
the signal state of both EN and ENO is 0. If the signal state of
IW2 IN2 ENO EN is 1 (activated) and the result of the math function is out
of range, the signal state of ENO is 0.
Network 3:
OS Q4.0
S
Figure 15-10 Exception Bit Overflow Stored

C79000-G7076-C566-01 15-9

15-10 C79000-G7076-C566-01
Program Control Instructions 16
Overview 16.1 Calling an FC/SFC without Parameters 16-2
16.2 Calling an FB, FC, SFB, SFC, and Multiple Instances 16-4
16.3 Return 16-7
16.4 Master Control Relay Instructions 16-8
16.5 Master Control Relay Activate/Deactivate 16-10
16.6 Master Control Relay On/Off 16-13

C79000-G7076-C566-01 16-1
Program Control Instructions
16.1 Calling an FC/SFC without Parameters
Description With the Call FC/SFC without Parameters instruction, you can call a
function (FC) or a system function (SFC) that has no parameters. The call is
conditional or unconditional depending on the preceding logic operation (see
the example).
In the code section of a function (FC), you cannot specify any parameter of
the type BLOCK_FC as the address for a conditional call. You can, however,
specify a parameter of the type BLOCK_FC as the address in a function
block (FB).
A conditional call is executed only if the RLO is 1. If a conditional call is not
executed, the RLO after the call instruction is 0. If the instruction is
executed, the following functions are performed:
The address required to return to the calling block is saved.
The data block registers are saved (data block and instance data block).
The previous local data area is replaced by the current local data area.
The MA bit (active MCR bit) is written to the block stack (BSTACK).
The new local data area is created for the called FC or SFC.
Program execution is then continued in the called block.
For more detailed information about transferring parameters, refer to the
STEP 7 Online Help.
Table 16-1 Calling an FC/SFC without Parameters Box

Area
Number of the FC or SFC (for example FC10 or
SFC59). The SFCs that are available depend on
<Number> your CPU.
Number BLOCK_FC –
CALL A conditional call with a parameter of the data
type BLOCK_FC as the address is only possible
in an FB and not in an FC.

16-2 C79000-G7076-C566-01
DB10
OPN
MCRA
FC10
CALL
Q4.0
I0.0 =
MCRD
FC11
I0.1 CALL
If the unconditional call for FC10 is executed, the CALL instruction performs the following
functions:
Saves the address required to return to the current FB.
Saves the selectors for DB10 and for the instance data block of the FB.
Pushes the MA bit, set to 1 in the MCRA instruction, to the block stack (BSTACK) and
resets this bit to 0 for the called FC10
Program execution continues in FC10. If you want to use the MCR function in FC10, you must
reactivate it there. When FC10 is completed, program execution returns to the calling FB. The
MA bit is restored. DB10 and the instance data block of the user-defined FB are the current
DBs again, regardless of which DBs were used by FC10.
After the return jump from FC10, the signal state of input I0.0 is assigned to output Q4.0. The
call for FC11 is a conditional call. It is executed only if the signal state of input I0.1 is 1. If the call
is executed, the function is the same as for calling FC10.
Status Word Bits
Unconditional call BR CC1 CC0 OV OS OR STA RLO FC

writes – – – – 0 0 1 – 0
Conditional call
writes – – – – 0 0 1 1 0
Figure 16-1 Calling an FC/SFC without Parameters

C79000-G7076-C566-01 16-3
16.2 Calling an FB, FC, SFB, SFC, and Multiple Instances
Description You can call function blocks (FBs), functions (FCs), system function blocks
(SFBs), and system functions (SFCs), and multiple instances by selecting
them from the “Program Elements” list box. They are at the end of the list of
instruction families under the following names:
FB Blocks
FC Blocks
SFB Blocks
SFC Blocks
Multiple Instances
Libraries
When you select one of these blocks, a box appears on your screen with the
number or symbolic name of the function or function block and the
parameters that belong to it.
The block that you call must have been compiled and must already exist in
your program file, in the library, or on the CPU.
If the call FB, FC, SFB, SFC, and multiple instances instruction is executed,
it performs the following functions:
It saves the address required to return to the calling block.
It saves both data block registers (data block and instance data block).
It replaces the previous local data area with the current local data area.
It shifts the MA bit (active MCR bit) to the block stack (BSTACK).
It creates the new local data area for the called FC or SFC.
Note
When the DB and DI registers are saved, it is possible that they do not point
to the data blocks that you opened. Because of the copy mechanisms for
transferring parameters, especially where function blocks are concerned, the
compiler sometimes overwrites the DB register. See the STEP 7 Online Help
for more details.
Execution of the program then continues in the called block.

16-4 C79000-G7076-C566-01
Enable Output The Enable output (ENO) of an FBD box corresponds to the BR bit of the
status word (see Section 2.3). When you write a function block or function
that you want to call from FBD regardless of whether you write the FB or FC
in STL, LAD or FBD, keep in mind the BR bit. You save the RLO in the BR
bit with the SAVE instruction according to the following criteria:
Save an RLO of 1 in the BR bit when the FB or FC is executed without
error.
Save an RLO of 0 in the BR bit when an error occurs in the execution of
the FB or FC.
You should program these instructions at the end of the FB or FC so that
these are the last instructions that are executed in the block.
Warning
! Unintentionally resetting the BR bit to 0
When writing FBs and FCs in FBD, if you do not handle the BR bit as
described above, one FB or FC may overwrite the BR bit of another FB
or FC.
To avoid this problem, store the RLO at the end of each FB or FC as
described above.
Effect of the Call Figure 16-2 shows the effects of a conditional and an unconditional call of a
on the Bits of the block on the bits of the status word (see Section 2.3).
Status Word

Conditional: writes x – – – 0 0 1 x x
Unconditional: writes – – – – 0 0 x x x
Figure 16-2 Effect of a Block Call on the Bits of the Status Word

C79000-G7076-C566-01 16-5
Parameters The parameters that have been defined in the VAR section of the block will
be displayed in the FBD box. Supplying parameters differs depending on the
type of block as follows:
For a function (FC), you must supply actual parameters for all of the
formal parameters.
The entry of actual parameters is optional with function blocks (FBs).
You must, however, attach an instance data block (instance DB) to the
FB. If an actual parameter has not been attached to a formal parameter,
the FB works with the values that exist in its instance DB.
With multiple instances, you do not need to specify the instance DB since
the box that is called has already been assigned the DB number (for more
information about declaring multiple instances, refer to STEP 7 Online
Help
For structured IN/OUT parameters and parameters of the types “Pointer” and
“Array”, you must make an actual parameter available (at least during the
first call).
Every actual parameter that you make available when calling a function
block must have the same data type as its formal parameter.
For information on how to program a function or how to work with its
parameters, see the STEP 7 Online Help.
Table 16-2 shows a box for calling FBs, FCs, SFBs, SFCs and describes the
parameters common to the box for all these blocks. The block number
appears automatically at the top of the block (number of the FB, FC, SFB, or
SFC, for example, FC10).
Table 16-2 Box and Parameters for Calling FBs, FCs, SFBs, SFCs
DB no. Data block number. This

DB no. BLOCK_DB – information is only necessary for
Block no. calling FBs.
EN
IN OUT EN BOOL I, Q, M, D, L, T, C Enable input
IN/OUT ENO
DB13
Calls FB10 (using
FB10 instance DB13)
Actual addresses, EN ENO
The value of this parameter is
the values of which I 1.0 Start Run M2.1
copied from DB13 into M 2.1 after
are copied into I 1.1 Stop processing FB10.
instance data block
DB13 before MW20 Length
processing FB10.
Formal parameters of the FB
Figure 16-3 Call FB as Box

16-6 C79000-G7076-C566-01
16.3 Return
Description You can use the Return instruction to exit blocks. You can exit a block
conditionally.
Table 16-3 Box Return
RET None – – –
I0.0 RET If the signal state of input I0.0 is 1, the block is

exited.
Status Word Bits
Conditional Return (Return if RLO = 1)

writes – – – – 0 0 1 1 0
Figure 16-4 Return

C79000-G7076-C566-01 16-7
16.4 Master Control Relay Instructions
Definition of the The Master Control Relay (MCR, see also Section 16.5) is used to activate
Master Control and deactivate signal flow. A deactivated signal flow corresponds to an
Relay instruction sequence that writes a zero value instead of the calculated value,
or to an instruction sequence that leaves the existing memory value
unchanged. Operations triggered by the instructions shown in Table 16-4 are
dependent on the MCR.
The Assign and Midline Output instructions write a 0 to the memory if the
MCR is 0. The Set Output and Reset Output instructions leave the existing
value unchanged (see Table 16-5).
Table 16-4 Instructions Influenced by an MCR Zone
FBD Box Description Section in This Manual
# Midline Output 4.9
= Assign 4.8
S Set Output 4.11
R Reset Output 4.12
Set_Reset Flip Flop 4.25

SR
Set_Reset Flip Flop 4.26

RS
Assign a Value 10.1

MOVE
Table 16-5 Instructions Dependent on MCR and How They React to Its Signal State
Signal State of Assign, Midline Output Set or Reset Output Assign a Value
MCR
= S R
MOVE
# SR RS
0 Writes 0 Does not write Writes 0
(Imitates a relay that falls to its (Imitates a latching relay that (Imitates a component that
quiet state when power is remains in its current state produces a value of 0 when
turned off) when power is turned off) power is turned off)
1 Normal execution Normal execution Normal execution

16-8 C79000-G7076-C566-01
Important Notes on Using MCR Functions
Take care with blocks in which the Master Control Relay was activated with
MCRA:
If the MCR is deactivated, the value 0 is written by all assignments in
program segments between (MCR<) and (MCR>)!
The MCR is deactivated if the RLO was =0 before an MCR< instruction.
Danger
! PLC in STOP or undefined runtime characteristics!
The compiler also uses write access to local data behind the temporary varia-
bles defined in VAR_TEMP for calculating addresses. This means the follo-
wing command sequences will set the PLC to STOP or lead to undefined
runtime characteristics:
Formal parameter access
Access to components of complex FC parameters of the type STRUCT,
UDT, ARRAY, STRING
Access to components of complex FB parameters of the type STRUCT,
UDT, ARRAY, STRING from the IN_OUT area in a version 2 block.
Access to parameters of a version 2 function block if its address is
greater than 8180.0.
Access in a version 2 function block to a parameter of the type
BLOCK_DB opens DB0. Any subsequent data access sets the CPU to
STOP. T 0, C 0, FC0, or FB0 are also always used for TIMER,
COUNTER, BLOCK_FC, and BLOCK_FB.
Parameter passing
Calls in which parameters are transferred.
KOP/FUP
T branches and midline outputs in Ladder or FBD starting with RLO = 0.
Remedy
Free the above commands from their dependence on the MCR:
1. Deactivate the Master Control Relay using the Master Control Relay
Deactivate instruction before the statement or network in question.
2. Activate the Master Control Relay again using the Master Control Relay
Activate instruction after the statement or network in question.

C79000-G7076-C566-01 16-9
16.5 Master Control Relay Activate/Deactivate
MCR Activate With the Activate Master Control Relay, instruction, you make subsequent
commands dependent on the MCR. After entering this command, you can
program the MCR zones with these instructions (see Section 16.6). When
your program activates an MCR area, all MCR actions depend on the content
of the MCR stack (see Figure B-4).
Table 16-6 Master Control Relay Activate Box
MCRA None – – Activates the MCR function
MCR Deactivate With the Deactivate Master Control Relay instruction, subsequent commands
are no longer dependent on the MCR. After this instruction, you cannot
program any more MCR zones. When your program deactivates an MCR
area, the MCR is always energized irrespective of the entries in the MCR
stack.
Table 16-7 Master Control Relay Deactivate Box
MCRD None – – Deactivates the MCR function
The MCR stack and the bit that controls its dependency (the MA bit) relate to
individual levels and must be saved and fetched every time you change the
sequence level. They are preset at the beginning of every sequence level
(MCR input bits 1 to 8 are set to 1, the MCR stack pointer is set to 0 and the
MA bit is set to 0).
The MCR stack is transferred from block to block and the MA bit is saved
and set to 0 every time a block is called. It is fetched back at the end of the
block.
The MCR can be implemented in such a way that it optimizes the run time of
code-generating CPUs. The reason for this is that the dependency of the
MCR is not passed on by the block; it must be explicitly activated by an
MCR instruction. A code-generating CPU recognizes this instruction and
generates the additional code necessary for the evaluation of the MCR stack
until it recognizes an MCR instruction or reaches the end of the block. With
instructions outside the MCRA/MCRD range, there is no increase of the run
time.
The instructions MCRA and MCRD must always be used in pairs within your
program.

16-10 C79000-G7076-C566-01
ÀÀÀÀÀÀÀ
OB1
ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ FBx

ÀÀÀÀÀÀ FCy
ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀ

ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ ÀÀÀÀÀÀ
ÀÀÀÀÀÀÀ ÀÀÀÀÀÀ
ÀÀÀÀÀÀÀ
MCRA
ÀÀÀÀÀÀÀ MCRA
MCRA
ÀÀÀÀÀÀÀ
ÀÀÀÀÀÀÀ
MCRD Call FCy
ÀÀÀÀÀÀÀ ÀÀÀÀÀÀÀ
Call FBx
MCRD
ÀÀÀÀÀÀÀ MCRA
BEU
BEU
Operations not dependent on the MCR bit
Operations dependent on the MCR bit
BEU BEU is an STL instruction.

You will find more details in the STL Manual /232/
Figure 16-5 Activating and Deactivating an MCR Area
The operations programmed between MCRA and MCRD depend on the

signal state of the MCR bit. Operations programmed outside an
MCRA-MCRD sequence do not depend on the signal state of the MCR bit. If
an MCRD instruction is missing, the operations programmed between the
instructions MCRA and BEU depend on the MCR bit.

C79000-G7076-C566-01 16-11
MCRA
I0.0 MCR<
Q4.0
I0.3 S
Q4.1
I0.4 =
MCR>
MCRD
The MCRA instruction activates the MCR function until the next MCRD. The instructions
between MCR< and MCR> are processed dependent on the MA bit (here I0.0):
If the signal state of input I0.0 is 1:

– Output Q4.0 is set to 1 if the signal state of input I0.3 is 1.
– Output Q4.0 remains unchanged if the signal state of input I0.3 is 0.
– The signal state of input I0.4 is assigned to output Q4.1.
If the signal state of input I0.0 is 0:
– Output Q4.0 remains unchanged regardless of the signal state of input I0.3.
– Output Q4.1 is 0 regardless of the signal state of input I0.4.
Status Word Bits

writes – – – – – – – – –
Figure 16-6 Master Control Relay (Activate and Deactivate)
You must program the dependency of the functions (FCs) and function blocks
(FBs) in the blocks yourself. If this function or function block is called from
an MCRA/MCRD sequence, not all instructions within this sequence are
automatically dependent on the MCR bit. To achieve this, use the instruction
MCRA of the block called.
Warning
! Risk of personal injury and damage to equipment:
Never use the instruction MCR as an EMERGENCY OFF or safety device
for personnel.
MCR is not a substitute for a hardwired master control relay.

16-12 C79000-G7076-C566-01
16.6 Master Control Relay On/Off
MCR On The Master Control Relay On (MCR<) instruction triggers an operation that
saves the RLO in the MCR stack and opens an MCR zone. The instructions
shown in Table 16-4 are influenced by this RLO saved in the MCR stack
when the MCR zone is opened. The MCR stack works like a LIFO (Last In,
First Out) buffer. Only eight entries are possible. If the stack is already full,
the Master Control Relay On instruction produces an MCR stack error
(MCRF).
Table 16-8 Master Control Relay On Box
MCR< None – – Opens an MCR zone
MCR Off The Master Control Relay Off (MCR>) instruction closes the MCR zone that
was opened last. The instruction does this by removing the RLO entry from
the MCR stack. The RLO was saved there by the Master Control Relay On
instruction. The entry released at the other end of the LIFO (Last In, First
Out) MCR stack is set to 1. If the stack is already empty, the Master Control
Relay Off instruction produces an MCR stack error (MCRF).
Table 16-9 Master Control Relay Off

Closes the MCR zone that was
MCR> None – –
opened last
The MCR is controlled by a stack which is one bit wide and eight entries
deep (see Figure 16-7). The MCR is activated as long as all eight entries in
the stack are equal to 1. The MCR< instruction copies the RLO to the MCR
stack. The MCR> instruction removes the last entry from the stack and sets
the released stack address to 1. If an error occurs, for example, if there are
more than eight MCR> instructions in succession, or you attempt to execute
the instruction MCR> when the stack is empty, the MCRF error message is
activated. The monitoring of the MCR stack is based on the stack pointer
(MSP: 0 = empty, 1 = one entry, 2 = two entries, ..., 8 = eight entries).

C79000-G7076-C566-01 16-13
RLO Shifted bit

# "
RLO 1
RLO 2
MSP ! RLO 3
4
5
6
7
8
# "
Shifted bit 1
MA
" "
MCRA 1 0 MCRD
MSP = MCR stack pointer

MA = Bit controlling MCR dependency
Figure 16-7 Master Control Relay Stack
The instructions MCR< and MCR> must always be used in pairs within your
program.
The MCR< instruction adopts the signal state of the RLO and copies it to the
MCR bit.
The MCR> instruction sets the MCR bit to 1 unconditionally. Because of this
characteristic, every other instruction between the instructions MCRA and
MCRD operates independent of the MCR bit (for information about MCRA
and MCRD, see above).
Nesting the You can nest the instructions MCR< and MCR>. The maximum nesting
Instructions MCR< depth is eight, in other words, you can write a maximum of eight MCR<
and MCR> instructions in succession before inserting an MCR> instruction. You must
program an equal number of MCR< and MCR> instructions.
If the MCR< instructions are nested, the MCR bit of the lower nesting level
is formed. The MCR< instruction then combines the current RLO with the
current MCR bit according to the AND truth table.
When an MCR> instruction completes a nesting level, it fetches the MCR bit
from the next highest level.

16-14 C79000-G7076-C566-01
MCRA
I0.0 MCR<
I0.1 MCR<
Q4.0
I0.3 S
MCR>
Q4.1
I0.4 =
MCR>
MCRD
When the MCRA instruction activates the MCR function, you can create up to eight nested MCR
zones. In the example, there are two MCR zones. The first MCR> instruction works together with the
second MCR< instruction. All instructions between the second set of MCR brackets (MCR<MCR>)
belong to the second MCR zone. The operations are executed as follows:
If I0.0 = 1: the signal state of input I0.4 is assigned to output Q4.1.
If I0.0 = 0: the signal state of output Q4.1 is 0 regardless of the signal state of input I0.4. Output
Q4.0 remains unchanged regardless of the signal state of input I0.3.
If I0.0 and I0.1 = 1: output Q4.0 is set to 1 if I0.3 = 1 and Q4.1 = I0.4.
If I0.1 = 0: output Q4.0 remains unchanged regardless of the signal state of input I0.3 and input
I0.0.
Status Word Bits

writes – – – – – 0 1 – 0
Figure 16-8 Master Control Relay Off

C79000-G7076-C566-01 16-15

16-16 C79000-G7076-C566-01
Alphabetical Lists of Instructions A
Appendix
Programming Examples B
References
C
P-18 C79000-G7076-C566-01
Alphabetical Lists of Instructions A
Overview A.1 List of Instructions with International Names A-2
A.2 List of Instructions with International (English) Names and A-6
German Equivalents
A.3 List of Instructions with German SIMATIC Names A-10
A.4 List of Instructions with German Names and International A-14
(English) Equivalents

C79000-G7076-C566-01 A-1
Alphabetical List of Instructions
A.1 List of Instructions with International Names
Table A-1 contains an alphabetical list of FBD instructions with international

(English) full names, the corresponding short name or mnemonic, and the
reference to the page on which the instruction is described.
Table A-1 FBD Instructions Arranged Alphabetically by International (English) Full Names with Short
Names
Full Name Short Name Page

Add Double Integer ADD_DI 7-3
Add Integer ADD_I 7-2
Add Real ADD_R 8-3
Address Negative Edge Detection NEG 4-31
Address Positive Edge Detection POS 4-30
AND & 4-3
Assign = 4-9
Assign a Value MOVE 10-2
BCD to Double Integer BCD_DI 10-6
BCD to Integer BCD_I 10-3
Call FB from Box CALL_FB 16-4
Call FC from Box CALL_FC 16-4
Call FC SFC (without parameters) CALL 16-2
Call System FB from Box CALL_SFB 16-4
Call System FC from Box CALL_SFC 16-4
Ceiling CEIL 10-16
Compare Double Integer (>, <, ==, <>, <=, >=) CMP >=D 9-3
Compare Integer (>, <, ==, <>, <=, >=) CMP >=I 9-2
Compare Real (>, <, ==, <>, <=, >=) CMP >=R 9-4
Divide Double Integer DIV_DI 7-9
Divide Integer DIV_I 7-8
Divide Real DIV_R 8-6
Double Integer to BCD DI_BCD 10-7
Double Integer to Real DI_R 10-8
Down Counter (counter instruction) S_CD 6-7
Down Counter (bit logic instruction) CD 4-17
Exception Bit Binary Result BR 15-3
Exception Bit Overflow OV 15-7
Exception Bit Overflow Stored OS 15-8
Exception Bit Unordered UO 15-6
Exclusive OR XOR 4-6
Extended Pulse S5 Timer (timer instruction) S_PEXT 5-7

A-2 C79000-G7076-C566-01
Names, cont.

Extended Pulse Timer (bit logic instruction) SE 4-20
Floor FLOOR 10-17
Form the Absolute Value of a Floating-Point Number ABS 8-8
Form the Arc Cosine of a Floating-Point Number ACOS 8-13
Form the Arc Sine of a Floating-Point Number ASIN 8-13
Form the Arc Tangent of a Floating-Point Number ATAN 8-13
Form the Cosine of a Floating-Point Number COS 8-13
Form the Exponential Value of a Floating-Point Number EXP 8-12
Form the Natural Logarithm of a Floating-Point Number LN 8-11
Form the Sine of a Floating-Point Number SIN 8-13
Form the Square of a Floating-Point Number SQR 8-9
Form the Square Root of a Floating-Point Number SQRT 8-10
Form the Tangent of a Floating-Point Number TAN 8-13
Insert Binary Input –––| 4-7
Integer to BCD I_BCD 10-4
Integer to Double Integer I_DI 10-5
Jump JMP 14-3
Jump-If-Not JMPN 14-5
Master Control Relay Activate MCRA 16-10
Master Control Relay Deactivate MCRD 16-10
Master Control Relay Off MCR> 16-13
Master Control Relay On MCR< 16-13
Midline Output # 4-10
Multiply Double Integer MUL_DI 7-7
Multiply Integer MUL_I 7-6
Multiply Real MUL_R 8-5
Negate Binary Input –––o| 4-8
Negate Real Number NEG_R 10-13
Negative RLO Edge Detection N 4-29
Off-Delay S5 Timer (timer instruction) S_OFFDT 5-13
Off-Delay Timer (bit logic instruction) SF 4-26
On-Delay S5 Timer (timer instruction) S_ODT 5-9
On-Delay Timer (bit logic instruction) SD 4-22
Ones Complement Double Integer INV_DI 10-10
Ones Complement Integer INV_I 10-9
Open Data Block: DB or DI OPN 13-2
OR >=1 4-4

C79000-G7076-C566-01 A-3
Names, cont.

Positive RLO Edge Detection P 4-28
Pulse S5 Timer (timer instruction) S_PULSE 5-5
Pulse Timer (bit logic instruction) SP 4-18
Reset Output R 4-13
Reset_Set Flip Flop RS 4-33
Result Bit Equal 0 ==0 1-6
Result Bit Greater Equal 0 >=0 15-4
Result Bit Greater Than 0 >0 15-4
Result Bit Less Equal 0 <=0 15-4
Result Bit Less Than 0 <0 15-4
Result Bit Not Equal 0 <>0 15-4
Retentive On-Delay S5 Timer (timer instruction) S_ODTS 5-11
Retentive On-Delay Timer (bit logic instruction) SS 4-24
Return RET 16-7
Return Fraction Double Integer MOD 7-10
Rotate Left Double Word ROL_DW 12-11
Rotate Right Double Word ROR_DW 12-12
Round to Double Integer ROUND 10-14
Save RLO to BR Memory SAVE 4-11
Set Output S 4-12
Set Counter Value SC 4-14
Set_Reset Flip Flop SR 4-32
Shift Left Double Word SHL_DW 12-4
Shift Left Word SHL_W 12-3
Shift Right Double Integer SHR_DI 12-9
Shift Right Double Word SHR_DW 12-6
Shift Right Integer SHR_I 12-8
Shift Right Word SHR_W 12-5
Subtract Double Integer SUB_DI 7-5
Subtract Integer SUB_I 7-4
Subtract Real SUB_R 8-4
Truncate Double Integer Part TRUNC 10-15
Twos Complement Double Integer NEG_DI 10-12
Twos Complement Integer NEG_I 10-11
Up Counter (counter instruction) S_CU 6-5
Up Counter (bit logic instruction) CU 4-16
Up-Down Counter S_CUD 6-3

A-4 C79000-G7076-C566-01
Names, cont.

(Word) AND Double Word WAND_DW 11-4
(Word) AND Word WAND_W 11-3
(Word) Exclusive OR Double Word WXOR_DW 11-8
(Word) Exclusive OR Word WXOR_W 11-7
(Word) OR Double Word WOR_DW 11-6
(Word) OR Word WOR_W 11-5

C79000-G7076-C566-01 A-5
A.2 List of Instructions with International (English) Names and German

Equivalents
Table A-4 contains an alphabetical list of FBD instructions with international

(English) full names, the German SIMATIC equivalents, and the reference to
the page on which the instruction is described.
Table A-2 FBD Instructions Arranged Alphabetically by International (English) Full Names with German
Equivalents
Full Name German SIMATIC Equivalent Page

Add Double Integer Ganze Zahlen addieren (32 Bit) 7-3
Add Integer Ganze Zahlen addieren (16 Bit) 7-2
Add Real Gleitpunktzahlen addieren 8-3
Address Negative Edge Detection Signalflanke 1 → 0 abfragen 4-31
Address Positive Edge Detection Signalflanke 0 → 1 abfragen 4-30
AND UND-Verknüpfung 4-3
Assign Zuweisung 4-9
Assign a Value Wert übertragen 10-2
BCD to Double Integer BCD-Zahl in Ganzzahl (32 Bit) wandeln 10-6
BCD to Integer BCD-Zahl in Ganzzahl (16 Bit) wandeln 10-3
Call FB from Box FB aufrufen 16-4
Call FC from Box FC aufrufen 16-4
Call FC SFC (without parameters) FC/SFC aufrufen ohne Parameter 16-2
Call System FB from Box System FB aufrufen 16-4
Call System FC from Box System FC Box aufrufen 16-4
Ceiling Aus Gleitpunktzahl nächsthöhere Ganzzahl 10-16
erzeugen
Compare Double Integer (>, <, ==, <>, <=, >=) Ganze Zahlen vergleichen (32 Bit) 9-3
Compare Integer (>, <, ==, <>, <=, >=) Ganze Zahlen vergleichen (16 Bit) 9-2
Compare Real (>, <, ==, <>, <=, >=) Gleitpunktzahlen vergleichen 9-4
Divide Double Integer Ganze Zahlen dividieren (32 Bit) 7-9
Divide Integer Ganze Zahlen dividieren (16 Bit) 7-8
Divide Real Gleitpunktzahlen dividieren 8-6
Double Integer to BCD Ganzzahl (32 Bit) in BCD-Zahl wandeln 10-7
Double Integer to Real Ganzzahl (32 Bit) in Gleitpunktzahl wandeln 10-8
Down Counter (counter instruction) Rückwärtszählen 6-7
Down Counter (bit logic instruction) Rückwärtszählen 4-17
Exception Bit Binary Result Störungsbit BIE-Register 15-3
Exception Bit Overflow Störungsbit Überlauf 15-7
Exception Bit Overflow Stored Störungsbit Überlauf gespeichert 15-8
Exception Bit Unordered Störungsbit Ungültige Operation 15-6

A-6 C79000-G7076-C566-01
Equivalents, cont.

Exclusive OR EXKLUSIV-ODER-Verknüpfung 4-6
Extended Pulse S5 Timer (timer instruction) Zeit als verlängerten Impuls starten (SV) 5-7
Extended Pulse Timer (bit logic instruction) Zeit als verlängerten Impuls starten (SV) 4-20
Floor Aus Gleitpunktzahl nächstniedere Ganzzahl 10-17
erzeugen
Form the Absolute Value of a Floating-Point Absolutwert einer Gleitpunktzahl bilden 8-8
Number
Form the Arc Cosine of a Floating-Point Arcuscosinus einer Gleitpunktzahl bilden 8-13
Number
Form the Arc Sine of a Floating-Point Number Arcussinus einer Gleitpunktzahl bilden 8-13
Form the Arc Tangent of a Floating-Point Arcustangens einer Gleitpunktzahl bilden 8-13
Number
Form the Cosine of a Floating-Point Number Cosinus einer Gleitpunktzahl bilden 8-13
Form the Exponential Value of a Floating-Point Exponentialwert einer Gleitpunktzahl bilden 8-12
Number
Form the Natural Algorithm of a Floating-Point Natürlichen Logarithmus einer Gleitpunktzahl 8-11
Number bilden
Form the Sine of a Floating-Point Number Sinus einer Gleitpunktzahl bilden 8-13
Form the Square of a Floating-Point Number Quadrat einer Gleitpunktzahl bilden 8-9
Form the Square Root of a Floating-Point Quadratwurzel einer Gleitpunktzahl bilden 8-10
Number
Form the Tangent of a Floating-Point Number Tangens einer Gleitpunktzahl bilden 8-13
Insert Binary Input Binären Eingang einfügen 4-7
Integer to BCD Ganzzahl (16 Bit) in BCD-Zahl wandeln 10-4
Integer to Double Integer Ganzzahl (16 Bit) in Ganzzahl (32 Bit) wandeln 10-5
Jump Springe wenn 1 14-3
Jump-If-Not Springe wenn 0 14-5
Master Control Relay Activate Master Control Relay Anfang 16-10
Master Control Relay Deactivate Master Control Relay Ende 16-10
Master Control Relay Off Master Control Relay ausschalten 16-13
Master Control Relay On Master Control Relay einschalten 16-13
Midline Output Konnektor 4-10
Multiply Double Integer Ganze Zahlen multiplizieren (32 Bit) 7-7
Multiply Integer Ganze Zahlen multiplizieren (16 Bit) 7-6
Multiply Real Gleitpunktzahlen multiplizieren 8-5
Negate Binary Input Binären Eingang negieren 4-8
Negate Real Number Vorzeichen einer Gleitpunktzahl wechseln 10-13
Negative RLO Edge Detection Flanke 1 → 0 abfragen 4-29
OR ODER-Verknüpfung 4-4
Off-Delay S5 Timer (timer instruction) Zeit als Ausschaltverzögerung starten (SA) 5-13

C79000-G7076-C566-01 A-7
Equivalents, cont.

Off-Delay Timer (bit logic instruction) Zeit als Ausschaltverzögerung starten (SA) 4-26
On-Delay S5 Timer (timer instruction) Zeit als Einschaltverzögerung starten (SE) 5-9
On-Delay Timer (bit logic instruction) Zeit als Einschaltverzögerung starten (SE) 4-22
Ones Complement Double Integer 1er Komplement zu Ganzzahl (32 Bit) erzeugen 10-10
Ones Complement Integer 1er Komplement zu Ganzzahl (16 Bit) erzeugen 10-9
Open Data Block: DB or DI Datenbaustein öffnen 13-2
Positive RLO Edge Detection Flanke 0 → 1 abfragen 4-28
Pulse S5 Timer (timer instruction) Zeit als Impuls starten (SI) 5-5
Pulse Timer (bit logic instruction) Zeit als Impuls starten (SI) 4-18
Reset Output Ausgang rücksetzen 4-13
Reset_Set Flip Flop Flipflop rücksetzen setzen 4-33
Result Bit Equal 0 Ergebnisbit bei gleich 0 15-4
Result Bit Greater Equal 0 Ergebnisbit bei größer gleich 0 15-4
Result Bit Greater Than 0 Ergebnisbit bei größer als 0 15-4
Result Bit Less Equal 0 Ergebnisbit bei kleiner gleich 0 15-4
Result Bit Less Than 0 Ergebnisbit bei kleiner 0 15-4
Result Bit Not Equal 0 Ergebnisbit bei ungleich 0 15-4
Retentive On-Delay S5 Timer (timer instruction) Zeit als speich. Einschaltverzögerung starten (SS) 5-11
Retentive On-Delay Timer Zeit als speich. Einschaltverzögerung starten (SS) 4-24
(Bitverknüpfungsperation)
Return Springe zurück 16-7
Return Fraction Double Integer Divisionsrest gewinnen (32 Bit) 7-10
Rotate Left Double Word 32 Bit links rotieren 12-11
Rotate Right Double Word 32 Bit rechts rotieren 12-12
Round to Double Integer Zahl runden 10-14
Save RLO to BR Memory Verknüpfungsergebnis ins BIE-Register laden 4-11
Set Output Ausgang setzen 4-12
Set Counter Value Zähleranfangswert setzen 4-14
Set_Reset Flip Flop Flipflop setzen rücksetzen 4-32
Shift Left Double Word 32 Bit links schieben 12-4
Shift Left Word 16 Bit links schieben 12-3
Shift Right Double Integer Ganzzahl (32 Bit) rechts schieben 12-9
Shift Right Double Word 32 Bit rechts schieben 12-6
Shift Right Integer Ganzzahl (16 Bit) rechts schieben 12-8
Shift Right Word 16 Bit rechts schieben 12-5
Subtract Double Integer Ganze Zahlen subtrahieren (32 Bit) 7-5
Subtract Integer Ganze Zahlen subtrahieren (16 Bit) 7-4
Subtract Real Gleitpunktzahlen subtrahieren 8-4

A-8 C79000-G7076-C566-01
Equivalents, cont.

Truncate Double Integer Part Ganze Zahl erzeugen 10-15
Twos Complement Double Integer 2er Komplement zu Ganzzahl (32 Bit) erzeugen 10-12
Twos Complement Integer 2er Komplement zu Ganzzahl (16 Bit) erzeugen 10-11
Up Counter (counter instruction) Vorwärtszählen 6-5
Up Counter (bit logic instruction) Vorwärtszählen 4-16
Up-Down Counter Vorwärts-/Rückwärtszählen 6-3
(Word) AND Double Word 32 Bit UND verknüpfen 11-4
(Word) AND Word 16 Bit UND verknüpfen 11-3
(Word) Exclusive OR Double Word 32 Bit EXKLUSIV ODER verknüpfen 11-8
(Word) Exclusive OR Word 16 Bit EXKLUSIV ODER verknüpfen 11-7
(Word) OR Double Word 32 Bit ODER verknüpfen 11-6
(Word) OR Word 16 Bit ODER verknüpfen 11-5

C79000-G7076-C566-01 A-9
A.3 List of Instructions with German SIMATIC Names
Table A-3 contains an alphabetical list of FBD instructions with the German
full names, the corresponding short name or mnemonic, and the reference to
the page on which the instruction is described.
Table A-3 FBD Instructions Arranged Alphabetically by German Full Names, with Short Names
Full Name SIMATIC Short Name Page

1er Komplement zu Ganzzahl (16 Bit) erzeugen INV_I 10-9
1er Komplement zu Ganzzahl (32 Bit) erzeugen INV_DI 10-10
2er Komplement zu Ganzzahl (16 Bit) erzeugen NEG_I 10-11
2er Komplement zu Ganzzahl (32 Bit) erzeugen NEG_DI 10-12
16 Bit EXKLUSIV ODER verknüpfen WXOR_W 11-7
16 Bit links schieben SHL_W 12-2
16 Bit ODER verknüpfen WOR_W 11-5
16 Bit rechts schieben SHR_W 12-5
16 Bit UND verknüpfen WAND_W 11-3
32 Bit EXKLUSIV ODER verknüpfen WXOR_DW 11-8
32 Bit links rotieren ROL_DW 12-11
32 Bit links schieben SHL_DW 12-4
32 Bit ODER verknüpfen WOR_DW 11-6
32 Bit rechts rotieren ROR_DW 12-12
32 Bit rechts schieben SHR_DW 12-6
32 Bit UND verknüpfen WAND_DW 11-4
Absolutwert einer Gleitpunktzahl bilden ABS 8-8
Arcuscosinus einer Gleitpunktzahl bilden ACOS 8-13
Arcussinus einer Gleitpunktzahl bilden ASIN 8-13
Arcustangens einer Gleitpunktzahl bilden ATAN 8-13
Ausgang rücksetzen R 4-13
Ausgang setzen S 4-12
Aus Gleitpunktzahl nächsthöhere Ganzzahl erzeugen CEIL 10-16
Aus Gleitpunktzahl nächstniedere Ganzzahl erzeugen FLOOR 10-17
BCD-Zahl in Ganzzahl (16 Bit) wandeln BCD_I 10-3
BCD-Zahl in Ganzzahl (32 Bit) wandeln BCD_DI 10-6
Binären Eingang einfügen –––| 4-7
Binären Eingang negieren –––o| 4-8
Cosinus einer Gleitpunktzahl bilden COS 8-13
Datenbaustein öffnen AUF 13-2
Divisionsrest gewinnen (32 Bit) MOD 7-10
Ergebnisbit bei gleich 0 ==0 15-4
Ergebnisbit bei größer als 0 >0 15-4

A-10 C79000-G7076-C566-01
Table A-3 FBD Instructions Arranged Alphabetically by German Full Names, with Short Names, cont.

Ergebnisbit bei größer gleich 0 >=0 15-4
Ergebnisbit bei kleiner 0 <0 15-4
Ergebnisbit bei kleiner gleich 0 <=0 15-4
Ergebnisbit bei ungleich 0 <>0 15-4
EXKLUSIV-ODER-Verknüpfung XOR 4-6
Exponentialwert einer Gleitpunktzahl bilden EXP 8-12
FB aufrufen CALL_FB 16-4
FC aufrufen CALL_FC 16-4
FC/SFC aufrufen ohne Parameter CALL 16-2
Flanke 0 → 1 abfragen P 4-28
Flanke 1 → 0 abfragen N 4-29
Flipflop rücksetzen setzen RS 4-33
Flipflop setzen rücksetzen SR 4-32
Ganze Zahlen addieren (16 Bit) ADD_I 7-2
Ganze Zahlen addieren (32 Bit) ADD_DI 7-3
Ganze Zahlen dividieren (16 Bit) DIV_I 7-8
Ganze Zahlen dividieren (32 Bit) DIV_DI 7-9
Ganze Zahlen multiplizieren (16 Bit) MUL_I 7-6
Ganze Zahlen multiplizieren (32 Bit) MUL_DI 7-7
Ganze Zahlen subtrahieren (16 Bit) SUB_I 7-4
Ganze Zahlen subtrahieren (32 Bit) SUB_DI 7-5
Ganze Zahlen vergleichen (16 Bit) CMP >=I 9-2
Ganze Zahlen vergleichen (32 Bit) CMP >=D 9-3
Ganze Zahl erzeugen TRUNC 10-15
Ganzzahl (16 Bit) in Ganzzahl (32 Bit) wandeln I_DI 10-5
Ganzzahl (16 Bit) in BCD-Zahl wandeln I_BCD 10-4
Ganzzahl (16 Bit) rechts schieben SHR_I 12-8
Ganzzahl (32 Bit) in BCD-Zahl wandeln DI_BCD 10-7
Ganzzahl (32 Bit) in Gleitpunktzahl wandeln DI_R 10-8
Ganzzahl (32 Bit) rechts schieben SHR_DI 12-9
Gleitpunktzahlen addieren ADD_R 8-3
Gleitpunktzahlen dividieren DIV_R 8-6
Gleitpunktzahlen multiplizieren MUL_R 8-5
Gleitpunktzahlen subtrahieren SUB_R 8-4
Gleitpunktzahlen vergleichen CMP >=R 9-4
Konnektor # 4-10
Master Control Relay Anfang MCRA 16-10
Master Control Relay ausschalten MCR> 16-13

C79000-G7076-C566-01 A-11

Master Control Relay einschalten MCR< 16-13
Master Control Relay Ende MCRD 16-10
Natürlichen Logarithmus einer Gleitpunktzahl bilden LN 8-11
ODER-Verknüpfung >=1 4-4
Quadrat einer Gleitpunktzahl bilden SQR 8-9
Quadratwurzel einer Gleitpunktzahl bilden SQRT 8-10
Rückwärtszählen (Zähloperation) Z_RUECK 6-7
Rückwärtszählen (Bitverknüpfungsoperation) ZR 4-17
Signalflanke 0 → 1 abfragen POS 4-30
Signalflanke 1 → 0 abfragen NEG 4-31
Sinus einer Gleitpunktzahl bilden SIN 8-13
Springe wenn 0 JMPN 14-5
Springe wenn 1 JMP 14-3
Springe zurück RET 16-7
Störungsbit BIE-Register BIE 15-3
Störungsbit Überlauf OV 15-7
Störungsbit Überlauf gespeichert OS 15-8
Störungsbit Ungültige Operation UO 15-6
System FB aufrufen CALL_SFB 16-4
System FC aufrufen CALL_SFC 16-4
Tangens einer Gleitpunktzahl bilden TAN 8-13
UND-Verknüpfung & 4-3
Verknüpfungsergebnis ins BIE-Register laden SAVE 4-11
Vorwärts-/Rückwärtszählen ZAEHLER 6-3
Vorwärtszählen (Zähloperation) Z_VORW 6-5
Vorwärtszählen (Bitverknüpfungsoperation) ZV 4-16
Vorzeichen einer Gleitpunktzahl wechseln NEG_R 10-13
Wert übertragen MOVE 10-2
Zahl runden ROUND 10-14
Zähleranfangswert setzen SZ 4-14
Zeit als Ausschaltverzögerung starten (SA) (Zeitoperation) S_AVERZ 5-13
Zeit als Ausschaltverzögerung starten (SA) (Bitverknüpfungsoperation) SA 4-26
Zeit als Einschaltverzögerung starten (SE) (Zeitoperation) S_EVERZ 5-9
Zeit als Einschaltverzögerung starten (SE) (Bitverknüpfungsoperation) SE 4-22
Zeit als Impuls starten (SI) (Zeitoperation) S_IMPULS
Zeit als Impuls starten (SI) (Bitverknüpfungsoperation) SI 4-18
Zeit als speich. Einschaltverzögerung starten (SS) (Zeitoperation) S_SEVERZ 5-11

A-12 C79000-G7076-C566-01

Zeit als speich. Einschaltverzögerung starten (SS) SS 4-24
(Bitverknüpfungsoperation)
Zeit als verlängerten Impuls starten (SV) (Zeitoperation) S_VIMP 5-7
Zeit als verlängerten Impuls starten (SV) (Bitverknüpfungsoperation) SV 4-20
Zuweisung = 4-9

C79000-G7076-C566-01 A-13
A.4 List of Instructions with German Names and International (English)

Equivalents
Table A-4 contains an alphabetical list of FBD instructions with German

SIMATIC full names, the international (English) equivalents, and the
reference to the page on which the instruction is described.
Table A-4 FBD Instructions Arranged Alphabetically by German Full Names with International (English)
Equivalents
SIMATIC Full Name International (English) Equivalent Page

1er Komplement zu Ganzzahl (16 Bit) erzeugen Ones Complement Integer 10-9
1er Komplement zu Ganzzahl (32 Bit) erzeugen Ones Complement Double Integer 10-10
2er Komplement zu Ganzzahl (16 Bit) erzeugen Twos Complement Integer 10-11
2er Komplement zu Ganzzahl (32 Bit) erzeugen Twos Complement Double Integer 10-12
16 Bit EXKLUSIV ODER verknüpfen (Word) Exclusive OR Word 11-7
16 Bit links schieben Shift Left Word 12-2
16 Bit ODER verknüpfen (Word) OR Word 11-5
16 Bit rechts schieben Shift Right Word 12-5
16 Bit UND verknüpfen (Word) AND Word 11-3
32 Bit EXKLUSIV ODER verknüpfen (Word) Exclusive OR Double Word 11-8
32 Bit links rotieren Rotate Left Double Word 12-11
32 Bit links schieben Shift Left Double Word 12-4
32 Bit ODER verknüpfen (Word) OR Double Word 11-6
32 Bit rechts rotieren Rotate Right Double Word 12-12
32 Bit rechts schieben Shift Right Double Word 12-6
32 Bit UND verknüpfen (Word) AND Double Word 11-4
Absolutwert einer Gleitpunktzahl bilden Form the Absolute Value of a Floating-Point 8-8
Number
Arcuscosinus einer Gleitpunktzahl bilden Form the Arc Cosine of a Floating-Point Number 8-13
Arcussinus einer Gleitpunktzahl bilden Form the Arc Sine of a Floating-Point Number 8-13
Arcustangens einer Gleitpunktzahl bilden Form the Arc Tangent of a Floating-Point 8-13
Number
Ausgang rücksetzen Reset Output 4-13
Ausgang setzen Set Output 4-12
Aus Gleitpunktzahl nächsthöhere Ganzzahl erzeugen Ceiling 10-16
Aus Gleitpunktzahl nächstniedere Ganzzahl erzeugen Floor 10-17
BCD-Zahl in Ganzzahl (16 Bit) wandeln BCD to Integer 10-3
BCD-Zahl in Ganzzahl (32 Bit) wandeln BCD to Double Integer 10-6
Binären Eingang einfügen Insert Binary Input 4-7
Binären Eingang negieren Negate Binary Input 4-8
Cosinus einer Gleitpunktzahl bilden Form the Cosine of a Floating-Point Number 8-13
Datenbaustein öffnen Open Data Block: DB or DI 13-2

A-14 C79000-G7076-C566-01
Equivalents, cont.

Divisionsrest gewinnen (32 Bit) Return Fraction Double Integer 7-10
Ergebnisbit bei gleich 0 Result Bit Equal 0 15-4
Ergebnisbit bei größer als 0 Result Bit Greater Than 0 15-4
Ergebnisbit bei größer gleich 0 Result Bit Greater Equal 0 15-4
Ergebnisbit bei kleiner 0 Result Bit Less Than 0 15-4
Ergebnisbit bei kleiner gleich 0 Result Bit Less Equal 0 15-4
Ergebnisbit bei ungleich 0 Result Bit Not Equal 0 15-4
EXKLUSIV-ODER-Verknüpfung Exclusive OR 4-6
Exponentialwert einer Gleitpunktzahl bilden Form the Exponential Value of a Floating-Point 8-12
Number
FB aufrufen Call FB from Box 16-4
FC aufrufen Call FC from Box 16-4
FC/SFC aufrufen ohne Parameter Call FC SFC (without parameters) 16-2
Flanke 0 → 1 abfragen Positive RLO Edge Detection 4-28
Flanke 1 → 0 abfragen Negative RLO Edge Detection 4-29
Flipflop rücksetzen setzen Reset_Set Flip Flop 4-33
Flipflop setzen rücksetzen Set_Reset Flip Flop 4-32
Ganze Zahlen addieren (16 Bit) Add Integer 7-2
Ganze Zahlen addieren (32 Bit) Add Double Integer 7-3
Ganze Zahlen dividieren (16 Bit) Divide Integer 7-8
Ganze Zahlen dividieren (32 Bit) Divide Double Integer 7-9
Ganze Zahlen multiplizieren (16 Bit) Multiply Integer 7-6
Ganze Zahlen multiplizieren [32 Bit) Multiply Double Integer 7-7
Ganze Zahlen subtrahieren (16 Bit) Subtract Integer 7-4
Ganze Zahlen subtrahieren (32 Bit) Subtract Double Integer 7-5
Ganze Zahlen vergleichen (16 Bit) Compare Integer (>, <, ==, <>, <=, >=) 9-2
Ganze Zahlen vergleichen (32 Bit) Compare Double Integer (>, <, ==, <>, <=, >=) 9-3
Ganze Zahl erzeugen Truncate Double Integer Part 10-15
Ganzzahl (16 Bit) in Ganzzahl (32 Bit) wandeln Integer to Double Integer 10-5
Ganzzahl (16 Bit) in BCD-Zahl wandeln Integer to BCD 10-4
Ganzzahl (16 Bit) rechts schieben Shift Right Integer 12-8
Ganzzahl (32 Bit) in BCD-Zahl wandeln Double Integer to BCD 10-7
Ganzzahl (32 Bit) in Gleitpunktzahl wandeln Double Integer to Real 10-8
Ganzzahl (32 Bit) rechts schieben Shift Right Double Integer 12-9
Gleitpunktzahlen addieren Add Real 8-3
Gleitpunktzahlen dividieren Divide Real 8-6
Gleitpunktzahlen multiplizieren Multiply Real 8-5
Gleitpunktzahlen subtrahieren Subtract Real 8-4

C79000-G7076-C566-01 A-15
Equivalents, cont.

Gleitpunktzahlen vergleichen Compare Real (>, <, ==, <>, <=, >=) 9-4
Konnektor Midline Output 4-10
Master Control Relay Anfang Master Control Relay Activate 16-10
Master Control Relay ausschalten Master Control Relay Off 16-13
Master Control Relay einschalten Master Control Relay On 16-13
Master Control Relay Ende Master Control Relay Deactivate 16-10
Natürlichen Logarithmus einer Gleitpunktzahl bilden Form the Natural Algorithm of a Floating-Point 8-11
Number
Quadrat einer Gleitpunktzahl bilden Form the Square of a Floating-Point Number 8-9
Quadratwurzel einer Gleitpunktzahl bilden Form the Square Root of a Floating-Point 8-10
Number
ODER-Verknüpfung OR 4-4
Rückwärtszählen (Zähloperation) Down Counter 6-7
Rückwärtszählen (Bitverknüpfungsoperation) Down Counter 4-17
Signalflanke 0→1 abfragen Address Positive Edge Detection 4-30
Signalflanke 1→0 abfragen Address Negative Edge Detection 4-31
Sinus einer Gleitpunktzahl bilden Form the Sine of a Floating-Point Number 8-13
Springe wenn 0 Jump-If-Not 14-5
Springe wenn 1 Jump 14-3
Springe zurück Return 16-7
Störungsbit BIE-Register Exception Bit Binary Result 15-3
Störungsbit Überlauf Exception Bit Overflow 15-7
Störungsbit Überlauf gespeichert Exception Bit Overflow Stored 15-8
Störungsbit Ungültige Operation Exception Bit Unordered 15-6
System FB aufrufen Call System FB from Box 16-4
System FC aufrufen Call System FC from Box 16-4
Tangens einer Gleitpunktzahl bilden Form the Tangent of a Floating-Point Number 8-13
UND-Verknüpfung AND 4-3
Verknüpfungsergebnis ins BIE-Register laden Save RLO to BR Memory 4-11
Vorwärts-/Rückwärtszählen Up-Down Counter 6-3
Vorwärtszählen (Zähloperation) Up Counter 6-5
Vorwärtszählen (Bitverknüpfungsoperation) Up Counter 4-16
Vorzeichen einer Gleitpunktzahl wechseln Negate Real Number 10-13
Wert übertragen Assign a Value 10-2
Zahl runden Round to Double Integer 10-14
Zähleranfangswert setzen Set Counter Value 4-14
Zeit als Ausschaltverzögerung starten (SA) Off-Delay S5 Timer 5-13
(Zeitoperation)

A-16 C79000-G7076-C566-01
Equivalents, cont.

Zeit als Ausschaltverzögerung starten (SA) Off-Delay Timer 4-26
Zeit als Einschaltverzögerung starten (SE) On-Delay S5 Timer 5-9
(Zeitoperation)
Zeit als Einschaltverzögerung starten (SE) On-Delay Timer 4-22
Zeit als Impuls starten (SI) (Zeitoperation) Pulse S5 Timer 5-5
Zeit als Impuls starten (SI) (Bitverknüpfungsoperation) Pulse Timer 4-18
Zeit als speich. Einschaltverzögerung starten (SS) Retentive On-Delay S5 Timer 5-11
(Zeitoperation)
Zeit als speich. Einschaltverzögerung starten (SS) Retentive On-Delay Timer 4-22
Zeit als verlängerten Impuls starten (SV) Extended Pulse S5 Timer 5-7
(Zeitoperation)
Zeit als verlängerten Impuls starten (SV) Extended Pulse Timer 4-20
Zuweisung Assign 4-9
Table A-5 FBD Instructions Listed in this Manual with their International Full and Short Names and their
SIMATIC Short Names
SIMATIC Full Name International Short SIMATIC Short Name Page

Name
Down Counter (counter instruction) S_CD Z_RUECK 6-7
Down Counter (bit logic instruction) CD ZR 4-17
Exception Bit Binary Result BR BIE 15-3
Extended Pulse S5 Timer (timer instruction) S_PEXT S_VIMP 5-7
Extended Pulse Timer (bit logic instruction) SE SV 11-5
Off-Delay S5 Timer (timer instruction) S_OFFDT S_AVERZ 5-13
Off-Delay Timer (bit logic instruction) SF SA 4-26
On-Delay S5 Timer (timer instruction) S_ODT S_EVERZ 5-9
On-Delay Timer (bit logic instruction) SD SE 4-22
Open Data Block: DB or DI OPN AUF 13-2
Pulse S5 Timer (timer instruction) S_PULSE S_IMPULS 5-5
Pulse Timer (bit logic instruction) SP SI 4-18
Retentive On-Delay S5 Timer (timer S_ODTS S_SEVERZ 5-11
instruction)
Retentive On-Delay Timer (bit logic SS SS 4-24
instruction)
Set Counter Value SC SZ 4-14
Up Counter (counter instruction) S_CU Z_VORW 6-5

C79000-G7076-C566-01 A-17
Table A-5 FBD Instructions Listed in this Manual with their International Full and Short Names and their
SIMATIC Short Names, continued
SIMATIC Full Name International Short SIMATIC Short Name Page

Name
Up Counter (bit logic instruction) CU ZV 4-16
Up-Down Counter S_CUD ZAEHLER 6-3

A-18 C79000-G7076-C566-01
Programming Examples B
Overview B.1 Overview B-2
B.2 Bit Logic Instructions B-3
B.3 Timer Instructions B-7
B.4 Counter and Comparison Instructions B-11
B.5 Integer Math Instructions B-13
B.6 Word Logic Instructions B-14

C79000-G7076-C566-01 B-1
Programming Examples
B.1 Overview
Practical Each FBD instruction described in this manual executes a specific function.
Applications When you combine these instructions into a program, you can accomplish a
wide variety of automation tasks. This chapter provides the following
examples of practical applications of the FBD instructions:
Controlling a conveyor belt using bit logic instructions
Detecting direction of movement on a conveyor belt using bit logic
instructions
Generating a clock pulse using timer instructions
Keeping track of storage space using counter and comparison instructions
Solving a problem using integer math instructions
Setting the length of time for heating an oven
Instructions Used The examples in this chapter use the following instructions:
Add Integer (ADD_I)
AND
Assign (=)
Assign a Value (MOVE)
Compare Integer (CMP_I>=)
Compare Integer (CMP_I<=)
Divide Integer (DIV_I)
Down Counter (S_CD)
Extended Pulse Timer (SE)
Jump-If-Not (JMPN)
Multiply Integer (MUL_I)
OR
Positive RLO Edge Detection (P)
Reset Output (R)
Return (RET)
Set Output (S)
Up Counter (S_CU)
(Word) AND Word (WAND_W)
(Word) OR Word (WOR_W)

B-2 C79000-G7076-C566-01
B.2 Bit Logic Instructions
Controlling a Figure B-1 shows a conveyor belt that can be activated electrically. There are
Conveyor Belt two push button switches at the beginning of the belt: S1 for START and S2
for STOP. There are also two push button switches at the end of the belt: S3
for START and S4 for STOP. It it possible to start or stop the belt from either
end. Sensor S5 stops the belt when an item on the belt reaches the end.
Symbolic You can write a program to control the conveyor belt shown in Figure B-1
Programming using symbols that represent the various components of the conveyor system.
If you choose this method, you need to make a symbol table to correlate the
symbols you choose with absolute values (see Table B-1). You define the
symbols in the symbol table (see the STEP 7 Online Help).
Table B-1 Elements of Symbolic Programming for Conveyor Belt System
Absolute
System Component Symbol Symbol Table
Address
Start button I1.1 S1 I1.1 S1
Stop button I1.2 S2 I1.2 S2
Start button I1.3 S3 I1.3 S3
Stop button I1.4 S4 I1.4 S4
Sensor I1.5 S5 I1.5 S5
Motor Q4.0 MOTOR_ON Q4.0 MOTOR_ON
Sensor S5
S1 ` Start S3 ` Start
S2 ` Stop S4 ` Stop
MOTOR_ON
Figure B-1 Conveyor Belt System

C79000-G7076-C566-01 B-3
Absolute You can write a program to control the conveyor belt shown in Figure B-1
Programming using absolute values that represent the different components of the conveyor
system (see Table B-2). Figure B-2 shows an FBD program to control the
conveyor belt.
Table B-2 Elements of Absolute Programming for Conveyor Belt System
System Component Absolute Address

Start button I1.1
Stop button I1.2
Start button I1.3
Stop button I1.4
Sensor I1.5
Motor Q4.0
Network 1: Pressing either start button turns the motor on.
I1.1 >=1
Q4.0
S
I1.3
Network 2: Pressing either stop button or the sensor at the end of the belt responding turns the
motor off.
I1.2 >=1
I1.4
Q4.0
E1.5 R
Figure B-2 Function Block Diagram to Control a Conveyor Belt

B-4 C79000-G7076-C566-01
Detecting the Figure B-3 shows a conveyor belt that is equipped with two photoelectric
Direction of a barriers (PEB1 and PEB2) that are designed to detect the direction in which a
Conveyor Belt package is moving on the belt.
Symbolic You can write a program to activate a direction display for the conveyor belt
Programming system shown in Figure B-3 using symbols that represent the various
components of the conveyor system, including the photoelectric barriers that
detect direction. If you choose this method, you need to make a symbol table
to correlate the symbols you choose with absolute values (see Table B-3).
You define the symbols in the symbol table (see the STEP 7 Online Help).
Table B-3 Elements of Symbolic Programming for Detecting Direction
Absolute
System Component Symbol Symbol Table
Address
Photoelectric barrier 1 I0.0 PEB1 I0.0 PEB1
Photoelectric barrier 2 I0.1 PEB2 I0.1 PEB2
Display for movement to right Q4.0 RIGHT Q4.0 RIGHT
Display for movement to left Q4.1 LEFT Q4.1 LEFT
Clock memory bit 1 M0.0 PM1 M0.0 PM1
Clock memory bit 2 M0.1 PM2 M0.1 PM2
Absolute You can write a program to activate the direction display for the conveyor
Programming belt shown in Figure B-3 using absolute values that represent the
photoelectric barriers that detect direction (see Table B-4). Figure B-4 shows
an FBD program to control the direction display for the conveyor belt.
Q4.0 PEB2 PEB1 Q4.1
Figure B-3 Conveyor Belt System with Photoelectric Light Barriers for Detecting
Direction

C79000-G7076-C566-01 B-5
Table B-4 Elements of Absolute Programming for Detecting Direction

System Component Absolute Address
Photoelectric barrier 1 I0.0
Photoelectric barrier 2 I0.1
Display for movement to right Q4.0
Display for movement to left Q4.1
Clock memory bit 1 M0.0
Clock memory bit 2 M0.1
Network 1: If there is a transition in signal state from 0 to 1 (rising edge) at input I0.0 and, at the same
time, the signal state at input I0.1 is 0, then the package on the belt is moving to the left.
M 0.0
P &
I0.0
Q4.1
I0.1 S
Network 2: If there is a transition in signal state from 0 to 1 (rising edge) at input I0.1 and, at the same
time, the signal state at input I0.0 is 0, then the package on the belt is moving to the right.
M 0.1
I0.1 P &
Q4.0
I0.0 S
If one of the photoelectric light barriers is interrupted, this means that there is a package between the
barriers.
&
I0.0 Q4.0
I0.1 R
Q4.1
R
Figure B-4 Function Block Diagram for Detecting the Direction of a Conveyor Belt

B-6 C79000-G7076-C566-01
B.3 Timer Instructions
Clock Pulse You can use a clock pulse generator or flasher relay when you want to
Generator produce a signal that is repeated periodically. Clock pulse generators are
commonly found in signaling systems that control flashing indicator lamps.
When you use the S7-300, you can implement the clock pulse generator
function by using time-driven program execution in special organization
blocks. The example shown in the following FBD program illustrates the use
of timer functions to generate a clock pulse.
The following example shows how to implement a freewheeling clock pulse
generator by using a timer (pulse duty factor 1:1). The frequency is divided
into the values listed in Table B-5.

C79000-G7076-C566-01 B-7
Network 1: If the signal state of timer T1 is 0, load the time value 250 ms into T1 and start T1 as an
extended-pulse timer.
T1
SE
M0.2 &
S5T#250MS TV
Network 2: The state of the timer is saved temporarily in an auxiliary memory bit.
M0.2
=
T1 &
Network 3: If the signal state of timer T1 is 1, jump to jump label N001.

N001
& JMP
M0.2
Network 4: When the timer T1 expires, the memory word 100 is incremented by 1.
ADD_I
??.? EN
MW100 IN1 OUT MW100
1 IN2 ENO
Network 5: The MOVE instruction allows you to output the different clock frequencies at
outputs Q12.0 through Q13.7.
N001
MOVE
??.? EN OUT QW12
MW100 IN ENO
Figure B-5 Function Block Diagram to Generate a Clock Pulse

B-8 C79000-G7076-C566-01
A signal check of timer T1 produces the result of logic operation (RLO, see
Section 2.3) shown in Figure B-6.
1
0
250 ms
Figure B-6 RLO for the Negated Input Parameter AN T1 in the Clock Pulse Timer
Example
As soon as the time runs out, the timer is restarted. Because of this, the signal
check made by AN M0.2 produces signal state 1 only briefly.
Figure B-7 shows the negated (inverted) RLO bit.
1
0
250 ms
Figure B-7 Negated RLO Bit of Timer T1 in the Clock Pulse Timer Example
Every 250 ms the RLO bit is 0. The jump is ignored and the content of
memory word MW100 is incremented by 1.
Achieving a Table B-5 lists the frequencies that you can achieve from the individual bits
Specific of memory bytes MB101 and MB100. Network 5 in the FBD diagram shown
Frequency in Figure B-5 illustrates how the MOVE instruction allows you to see the
different clock frequencies at outputs Q12.0 through Q13.7.
Table B-5 Frequencies for Clock Pulse Timer Example
Bits in Frequency in Hz Duration

MB101/MB100
M101.0 2.0 0.5 s (250 ms on/250 ms off)
M101.1 1.0 1 s (0.5 s on/0.5 s off)
M101.2 0.5 2 s (1 s on/1 s off)
M101.3 0.25 4 s (2 s on/2 s off)
M101.4 0.125 8 s (4 s on/4 s off)
M101.5 0.0625 16 s (8 s on/8 s off)
M101.6 0.03125 32 s (16 s on/16 s off)
M101.7 0.015625 64 s (32 s on/32 s off)
M100.0 0.0078125 128 s (64 s on/64 s off)
M100.1 0.0039062 256 s (128 s on/128 s off)
M100.2 0.0019531 512 s (256 s on/256 s off)

C79000-G7076-C566-01 B-9
Table B-5 Frequencies for Clock Pulse Timer Example
Bits in Frequency in Hz Duration

MB101/MB100
M100.3 0.0009765 1024 s (512 s on/512 s off)
M100.4 0.0004882 2048 s (1024 s on/1024 s off)
M100.5 0.0002441 4096 s (2048 s on/2048 s off)
M100.6 0.000122 8192 s (4096 s on/4096 s off)
M100.7 0.000061 16384 s (8192 s on/8192 s off)
Table B-6 lists the signal states of the bits of memory byte MB101.
Figure B-8 shows the signal state of memory bit M101.1.
Table B-6 Signal States of the Bits of Memory Byte MB101
Signal State of Bits of Memory Byte MB101 Time

Scan
Value
Cycle 7 6 5 4 3 2 1 0 in ms
0 0 0 0 0 0 0 0 0 250
1 0 0 0 0 0 0 0 1 250
2 0 0 0 0 0 0 1 0 250
3 0 0 0 0 0 0 1 1 250
4 0 0 0 0 0 1 0 0 250
5 0 0 0 0 0 1 0 1 250
6 0 0 0 0 0 1 1 0 250
7 0 0 0 0 0 1 1 1 250
8 0 0 0 0 1 0 0 0 250
9 0 0 0 0 1 0 0 1 250
10 0 0 0 0 1 0 1 0 250
11 0 0 0 0 1 0 1 1 250
12 0 0 0 0 1 1 0 0 250
T
1
M101.1 0
Time
0 250 ms 0.5 s 0.75 s 1 s 1.25 s 1.5 s
Frequency 1 1 1Hz
T 1 s
Figure B-8 Signal State of Bit 1 of MB101 (M101.1)

B-10 C79000-G7076-C566-01
B.4 Counter and Comparison Instructions
Storage Area with Figure B-9 shows a system with two conveyor belts and a temporary storage
Counter and area in between them. Conveyor belt 1 delivers packages to the storage area.
Comparator A photoelectric barrier at the end of conveyor belt 1 near the storage area
detects how many packages are delivered to the storage area. Conveyor belt 2
transports packages from the temporary storage area to a loading dock where
trucks take the packages away for delivery to customers. A photoelectric
barrier at the end of conveyor belt 2 near the storage area detects how many
packages leave the storage area to go to the loading dock.
A display panel with five lamps indicates the fill level of the temporary
storage area. Figure B-10 shows the FBD program that activates the indicator
lamps on the display panel.
Display panel
Storage area Storage area Storage area Storage area Storage area
empty not empty 50% full 90% full filled to capacity
(Q12.0) (Q12.1) (Q15.2) (Q15.3) (Q15.4)
I0.0 I0.1
Temporary
Packages in storage for 100 Packages out
packages
Conveyor belt 1 Conveyor belt 2

Photoelectric barrier 1 Photoelectric barrier 2
Figure B-9 Storage Area with Counter and Comparator

C79000-G7076-C566-01 B-11
Network 1: Counter C1 counts up at each signal change from 0 to 1 at input CU and counts down at
each signal change from 0 to 1 at input CD. With a signal change from 0 to ”1” at input S, the counter
value is set to the value PV. A signal change from 0 to 1 at input R resets the counter value to 0.
MW200 contains the current counter value of C1. Q12.1 indicates “storage area not empty”.
C1
S_CUD
I12.0 CU
I12.1 CD
I12.2 S CV MW210
C#10 PV CV_BCD MW200 Q12.1

=
I12.3 R Q
Network 2: Q12.0 indicates ”storage area not empty”.
Q12.0
=
Q12.1 &
Network 3: If 50 is less than or equal to the counter value (in other words if the current counter value
is greater than or equal to 50), the indicator lamp for “storage area 50% full” is lit.
CMP
<= I
Q15.2
50 IN1
=
MW200 IN2
Network 4: If the counter value is greater than or equal to 90, the indicator lamp for “storage area 90%
full” is lit.
CMP
>= I
Q15.3
MW200 IN1
=
90 IN2
Network 5: If the counter value is greater than or equal to 100, the indicator lamp for “storage area full”
is lit. Use output Q4.4 to interlock conveyor belt 1.
CMP
>= I
MW200 IN1 Q15.4
100 IN2 =
Figure B-10 Function Block Diagram for Activating Indicator Lamps on a Display Panel

B-12 C79000-G7076-C566-01
B.5 Integer Math Instructions
Solving a Math The following sample program shows you how to use three integer math
Problem instructions and the L and T instructions to produce the same result as the
following equation:
(IW0 ) DBW3) 15
MW4 +
MW0
Network 1: Open Data Block DB1
DB1
OPN
Network 2: Input word IW0 is added to shared data word DBW3 (data block must be defined and
opened) and the sum is loaded into memory word MW100. MW100 is then multiplied by 15 and the
answer stored in memory word MW102. MW102 is divided by MW0 with the result stored in MW4. As
long as all results are in the permitted range of each instruction, the ENO passes a signal state of 1 to
the next box.
ADD_I
??.? EN
IW0 IN1 OUT MW100

MUL_I
DBW3 IN2 ENO EN
MW100 IN1 OUT MW102

DIV_I
15 IN2 ENO EN
MW102 IN1 OUT MW4
MW0 IN2 ENO
Figure B-11 Function Block Diagram for Integer Math Instructions

C79000-G7076-C566-01 B-13
B.6 Word Logic Instructions
Heating an Oven The operator of the oven shown in Figure B-12 starts the oven heating by
pushing the start push button. The operator can set the length of time for
heating by using the thumbwheel switches shown in the figure. The value
that the operator sets indicates seconds in binary coded decimal (BCD)
format. Table B-7 lists the components of the heating system and their
corresponding absolute addresses used in the sample program shown in
Figure B-12.
Table B-7 Heating System Components and Corresponding Absolute Addresses
System Component Absolute Address in FBD Program

Start button I0.7
Thumbwheel for ones I1.0 to I1.3
Thumbwheel for tens I1.4 to I1.7
Thumbwheel for hundreds I0.0 to I0.3
Start heating Q4.0
Thumbwheels for setting BCD digits
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Oven
4 4 4
Heat 7.... ...0 7... ...0 Bits

Q4.0
XXXX 0001 1001 0001 IW0
IB0 IB1 Bytes

Start button I0.7
Figure B-12 Using the Inputs and Outputs for a Time-Limited Heating Process

B-14 C79000-G7076-C566-01
Network 1: If the timer is running, then turn on the heater. If the timer is running, the Return instruction
ends the processing here.
Q4.0
& =
T1
Network 2: If the timer is running, the Return instruction ends the processing here.
T1 & RET
Network 3: Mask input bits I0.4 through I0.7 (that is, reset them to 0). These bits of the thumbwheel
inputs are not used. The 16 bits of the thumbwheel inputs are combined with W#16#0FFF according
to the (Word) And Word instruction. The result is loaded into memory word MW1. In order to set the
time base of seconds, the preset value is combined with W#16#2000 according to the (Word) Or
Word instruction, setting bit 13 to 1 and resetting bit 12 to 0.
WAND_W
??.? EN
IW0 IN1 OUT MW1

WOR_W
W#16#FFF IN2 ENO EN
MW1 IN1 OUT MW2
W#16#2000 IN2 ENO
Network 4: Start timer T1 as an extended pulse timer if the start push button is pressed, loading as a
preset value memory word MW2 (derived from the logic above).
T1
I0.7 & SE
MW2 TV
Figure B-13 Function Block Diagram for Heating an Oven

C79000-G7076-C566-01 B-15

B-16 C79000-G7076-C566-01
References C
/30/ Getting Started: Working with STEP 7 V5.0
/70/ Manual: S7-300 Programmable Controller,
Hardware and Installation
/71/ Reference Manual: S7-300, M7-300 Programmable Controllers
Module Specifications
/72/ Instruction List: S7-300 Programmable Controller
/100/ Manual: S7-400/M7-400 Programmable Controllers,
Hardware and Installation
/101/ Reference Manual: S7-400/M7-400 Programmable Controllers
Module Specifications
/102/ Instruction List: S7-400 Programmable Controller
/231/ Manual:
Configuring Hardware and Communication Connections, STEP 7 V5.0
/232/ Reference Manual: Statement List (STL) for S7-300 and S7-400
Programming
/233/ Reference Manual: Ladder Logic (LAD)for S7-300and S7-400,
Programming
/234/ Manual: Programming with STEP 7 V5.0
/235/ Reference Manual: System Software for S7-300 and S7-400
System and Standard Functions
/250/ Manual: Structured Control Language (SCL) for S7-300/S7-400,
Programming
/251/ Manual: S7-GRAPH for S7-300 and S7-400,
Programming Sequential Control Systems
/252/ Manual: S7-HiGraph for S7-300 and S7-400,
Programming State Graphs
/253/ Manual: C Programming for S7-300 and S7-400,
Writing C Programs
/254/ Manual: Continuous Function Charts (CFC) for S7 and M7,
Programming Continuous Function Charts
/270/ Manual: S7-PDIAG for S7-300 and S7-400
“Configuring Process Diagnostics for LAD, STL, and FBD”
/271/ Manual: NETPRO,
“Configuring Networks”

C79000-G7076-C566-01 C-1
References
/800/ DOCPRO
Creating Wiring Diagrams (CD only)
/801/ TeleService for S7, C7 and M7
Remote Maintenance for Automation Systems (CD only)
/802/ PLC Simulation for S7-300 and S7-400 (CD only)
/803/ Reference Manual: Standard Software for S7-300 and S7-400,
STEP 7 Standard Functions, Part 2

C-2 C79000-G7076-C566-01
Glossary
Absolute In absolute addressing, the memory location of the address to be processed is

Addressing given.
Accumulator Accumulators are registers in the CPU which act as intermediate buffers for
load, transfer, comparison, math, and conversion operations.
Actual Parameter Actual parameters replace the formal parameters when function blocks (FBs)
and functions (FCs) are called.
Example: The formal parameter “Start” is replaced by the actual parameter
“I3.6”.
Address An address is part of a STEP 7 statement and specifies what the processor
should execute the instruction on. Addresses can be absolute or symbolic.
Address Identifier An address identifier is the part of the address which contains various data.
The data can include elements such as a value itself (data object) or the size
of a value with which the instruction can, for example, perform a logic
operation. In the instruction statement “L IB10” IB is the address identifier
(“I” indicates the memory input area and “B” indicates a byte in that area).
Array An array is a complex data type which consists of data elements of the same
type. These data elements can be elementary or complex.
Bit Result (BR) The bit result is the link between bit and word-oriented processing. This is an
efficient method to allow the binary interpretation of the result of a word
instruction and to include it in a series of logic operations.

C79000-G7076-C566-01 Glossary-1
Glossary
Call Hierarchy All blocks must be called first before they can be processed. The sequence
and nesting of these calls within an organized block is called the call
hierarchy.
Condition Codes The CC 1 and CC 0 bits (condition codes) provide information on the
CC 1 and CC 0 following results or bits:
Result of a math operation
Result of a comparison
Result of a digital operation
Bits that have been shifted out by a shift or rotate command
Current Path Characteristic of the Ladder Logic programming language. Current paths
contain contacts and coils. Complex elements (for example, math functions)
can also be inserted into current paths in the form of “boxes.” Current paths
are connected to power rails.
Data Block (DB) Data blocks (DBs) are areas in a user program which store user data. There
are shared data blocks which can be accessed by all logic blocks and there
are instance data blocks which are associated with a certain function block
(FB) call. In contrast to all other blocks, data blocks do not contain
instructions.
Data, Static Static data are local data of a function block which are stored in the instance
data block and, therefore, remain intact until the function block is processed
again.
Data Type A data type defines how the value of a variable or a constant should be used
in the user program.
In SIMATIC STEP 7 two data types are available to the user (IEC 1131–3):
Elementary data types
Complex data types
Data Type, Complex data types are created by the user with the data type declaration.
Complex They do not have their own name and cannot, therefore, be used again. They
can either be arrays or structures. The data types STRING and DATE AND
TIME are classed as complex data types.

Glossary-2 C79000-G7076-C566-01
Glossary
Data Type, Elementary data types are preset data types according to IEC 1131–3.
Elementary
Examples:
Data type “BOOL” defines a binary variable (“Bit”)
Data type “INT” defines a 16-bit fixed-point variable.
Declaration The declaration section is used for the declaration of the local data of a logic
block when programming in the Text Editor.
Direct Addressing In direct addressing, the address contains the memory location of a value
which is to be used by the instruction.
Example:
The location Q4.0 defines bit 0 in byte 4 of the process-image output table.
First Check Bit First check of the result of logic operation.
Folder Directory of the user interface of the SIMATIC Manager which can be
opened and can hold other directories or objects.
Formal Parameter A formal parameter is a placeholder for the actual parameter in logic blocks.
In function blocks (FBs) and functions (FCs) the formal parameters are
declared by the user, in system function blocks (SFBs) and system functions
(SFCs) they are already available. When a block is called, formal parameters
are assigned actual parameters, so the called block works with the current
values.
The formal parameters are classed as local data. They can be input, output, or
in/out parameters.
Function (FC) According to the International Electrotechnical Commission’s IEC 1131–3

standard, functions are logic blocks without a ‘memory’ (meaning they do
not have static data). A function allows you to transfer parameters in the user
program, which means they are suitable for programming frequently
recurring, complex functions, such as calculations. Important: As a function
has no memory, you must continue processing the calculated values directly
after the function has been called.

C79000-G7076-C566-01 Glossary-3
Glossary
Function Block According to the International Electrotechnical Commission’s IEC 1131–3

(FB) standard, function blocks are logic blocks with a ‘memory’ (meaning they
have static data). A function block allows you to transfer parameters in the
user program, which means they are suitable for programming frequently
recurring, complex functions, such as closed-loop control and operating
mode selection. As a function block has a memory (instance data block), you
can access its parameters (for example, outputs) at any time and at any point
in the user program.
Function Block Function Block Diagram (FBD) is one of the programming languages in
Diagram (FBD) STEP 5 and STEP 7. FBD represents logic in the boxes familiar from
Boolean algebra. In addition, complex functions (for example, math
functions) can be represented in direct connection with the logic box.
Programs created with FBD can also be translated into other programming
languages (for example, Ladder Logic).
Immediate In immediate addressing, the address contains the value with which the
Addressing instruction works.
Example: L.27 means load constant 27 into accumulator.
Input, Incremental When a block is input incrementally, each line or element is checked
immediately for errors (for example, syntax errors). If an error is detected, it
is marked and must be corrected before programming is completed.
Incremental input is possible in STL (Statement List), LAD (Ladder Logic),
and FBD (Function Block Diagram).
Instance An “instance” is the call of a function block. An instance data block is

assigned to each call.
Instance Data An instance data block stores the formal parameters and the static data of
Block (DB) function blocks. An instance data block can be assigned to one function
block call or a call hierarchy of function blocks.
Instruction An instruction is part of a STEP 7 statement; it specifies what the processor

should do.

Glossary-4 C79000-G7076-C566-01
Glossary
Keyword Keywords are used when programming with source files to identify the start
and end of a block and to select sections in the declaration section of blocks,
the start of block comments and the start of titles.
Ladder Logic Ladder Logic is a graphic programming language in STEP 5 and STEP 7. Its
(LAD) representation is standardized in compliance with DIN 19239 (international
standard IEC 1131-1). Ladder Logic representation corresponds to the
representation of relay ladder logic diagrams. In contrast to Statement List
(STL), LAD has a restricted set of instructions.
Logic Block Logic blocks are blocks within SIMATIC S7 that contain a part of the
STEP 7 user program. In contrast, data blocks (DBs) only contain data. There
are the following types of logic blocks: organization blocks (OBs), function
blocks (FBs), functions (FCs), system function blocks (SFBs), and system
functions (SFCs). Blocks are stored in the “Blocks” folder under the “S7
Program” folder.
Logic String A logic string is that portion of a user program which begins with an FC bit
that has a signal state of 0 and which ends when an instruction or event resets
the FC bit to 0. When the CPU executes the first instruction in a logic string,
the FC bit is set to 1. Certain instructions such as output instructions (for
example, Set, Reset, or Assign) reset the FC bit to 0. See First Check Bit
above.
Master Control The Master Control Relay (MCR) is an American relay ladder logic master
Relay switch for energizing and de-energizing power flow (current path). A
de-energized current path corresponds to an instruction sequence that writes a
zero value instead of the calculated value, or, to an instruction sequence that
leaves the existing memory value unchanged.
Memory Area In SIMATIC S7 a CPU has three memory areas:

Load memory
Work memory
System memory

C79000-G7076-C566-01 Glossary-5
Glossary
Mnemonic Mnemonic representation is an abbreviated form for displaying the names of

Representation addresses and programming instructions in the program (for example, “I”
stands for “input”). STEP 7 supports the international representation (based
on the English language), and the SIMATIC representation (based on the
German abbreviations of the instruction set and the SIMATIC addressing
conventions).
Network Networks subdivide LAD and FBD blocks into complete current paths and
Statement List (STL) blocks into clear units.
Overflow Bit The status bit OV stands for overflow. An overflow can occur, for example,
after a math operation.
Pointer You can use a pointer to identify the address of a variable. A pointer contains
an identifier instead of a value. If you allocate an actual parameter type, you
provide the memory address. With STEP 7 you can either enter the pointer in
pointer format or simply as an identifier (for example, M 50.0). In the
following example, the pointer format is shown with which data from M 50.0
is accessed:
P#M50.0
Project A project is a folder for all objects in an automation task, irrespective of the
number of stations, modules, and how they are connected in networks.
Reference Data Reference data are used to check your S7 program and include the
cross-reference list, the assignment lists, the program structure, the list of
unused addresses, and the list of addresses without symbols.

Glossary-6 C79000-G7076-C566-01
Glossary
Result of Logic The result of logic operation (RLO) is the result of the logic string which is
Operation (RLO) used to process other binary signals. The execution of certain instructions
depends entirely on their preceding RLO.
S7 Program A folder for blocks, source files, and charts for S7 programmable controllers.
The S7 program also includes the symbol table.
Shared Data Block A shared data block is a DB whose address is loaded in the DB address
(DB) register when it is opened. It provides storage and data for all logic blocks
(FCs, FBs, or OBs) that are being executed.
In contrast, an instance DB is designed to be used as specific storage and data
for the FB with which it has been associated.
Source File A source file (text file) is part of a program created either with a graphic or a
text-oriented editor and is compiled into an executable S7 user program or
the machine code for M7.
An S7 source file is stored in the “Sources” folder under the “S7 program”
folder.
Statement List Statement List (STL) is a textual representation of the STEP 7 programming
(STL) language, similar to machine code. STL is the assembler language of STEP 5
and STEP 7. If you program in STL, the individual statements represent the
actual steps in which the CPU executes the program.
Station A station is a device which can be connected to one or more subnets; for
example, the programmable controller, programming device, and operator
station.
Status Bit The status bit stores the value of a bit that is referenced. The status of a bit
instruction that has read access to the memory (A, AN, O, ON, X, XN) is
always the same as the value of the bit that this instruction checks (the bit on
which it performs its logic operation). The status of a bit instruction that has
write access to the memory (S, R, =) is the same as the value of the bit to
which the instruction writes or, if no writing takes place, the same as the
value of the bit that the instruction references. The status bit has no
significance for bit instructions that do not access the memory. Such
instructions set the status bit to 1 (STA=1). The status bit is not checked by
an instruction. It is interpreted during program test (program status) only.

C79000-G7076-C566-01 Glossary-7
Glossary
Status Word The status word is part of the register of the CPU. It contains status
information and error information which is displayed when specific STEP 7
commands are executed. The status bits can be read and written on by the
user, the error bits can only be read.
Stored Overflow The status bit OS stands for “stored overflow bit of the status word”. An
Bit overflow can take place, for example, after a math operation.
Symbol A symbol is a name which can be defined by the user subject to syntax
guidelines. After it has been declared (for example, as a variable, data type,
jump label, block etc) the symbol can be used for programming and for
operator interface functions. Example: Address: I 5.0, data type: BOOL,
Symbol: momentary contact switch / emergency stop.
Symbol Table A table in which the symbols of addresses for shared data and blocks are
allocated. Examples: Emergency Stop (symbol) -I 1.7 (address) or
closed-loop control (symbol) - SFB24 (block).
Symbolic In symbolic addressing, the address being processed is designated with a

Addressing symbol (as opposed to an absolute address).
System Function A system function is a function (without a memory) that is integrated in the
(SFC) S7 operating system and can, if necessary, be called from the STEP 7 user
program like a function (FC).
System Function A system function block (SFB) is a function (with a memory) that is
Block (SFB) integrated in the S7 operating system and can, if necessary, be called from
the STEP 7 user program like a function block (FB).
User Data Types User data types are special data structures which you can create yourself and
(UDTs) use in the entire user program after they have been defined. They can be used
like elementary or complex data types in the variable declaration of logic
blocks (FCs, FBs, OBs) or as a template for creating data blocks with the
same data structure.
User Program The user program contains all the statements and declarations and all the data
for signal processing which can be used to control a device or a process. It is
part of a programmable module (CPU, FM) and can be structured with
smaller units (blocks).

Glossary-8 C79000-G7076-C566-01
Glossary
User Program The user program structure describes the call hierarchy of the blocks within
Structure an S7 program and provides an overview of the blocks used and their
dependency.
Variable The variable declaration table is used for declaring the local data of a logic
Declaration Table block, when programming takes place in the Incremental Editor.
Variable Table The variable table is used to collect together the variables that you want to
(VAT) monitor and modify and set their relevant formats.

C79000-G7076-C566-01 Glossary-9
Glossary

Glossary-10 C79000-G7076-C566-01
Index
Symbols Address types, 3-4
Addressing
(Word) AND Double Word (WAND_DW)
absolute, B-4
instruction, 11-4–11-5
definition, 3-2
(Word) AND Word (WAND_W) instruction,
direct, 3-2
11-3–11-4
immediate, 3-2
(Word) Exclusive OR Double Word
symbolic, B-3
(WXOR_DW) instruction, 11-8–11-9
AND, 4-3
(Word) Exclusive OR Word (WXOR_W)
truth table, 2-6
AND-before-OR, 4-5
(Word) OR Double Word (WOR_DW)
Arc Cosine (ACOS), 8-13–8-15
Arc Sine (ASIN), 8-13–8-14
(Word) OR Word (WOR_W) instruction,
Arc Tangent (ATAN), 8-13
11-5–11-6
ASIN. See Arc Sine
#. See Connector
Assign Value (MOVE), 10-2
=. See Assign
Assignment, 4-9
ATAN. See Arc Tangent
AUF. See Open Data Block, SIMATIC
A mnemonic
Absolute addressing, practical application, B-4
Accumulators
count value, 6-2 B
description, 2-9
BCD Conversion Error (BCDF), 10-3, 10-6
function, 2-9
BCD to Double Integer (BCD_DI), 10-6
ACOS. See Arc Cosine
BCD to Integer (BCD_I), 10-3
Add Double Integer (ADD_DI), 7-3
BCD_DI. See BCD to Double Integer
Add Integer (ADD_I), 7-2
BCD_I. See BCD to Integer
Add Real (ADD_R), 8-3
BCDF. See BCD Conversion Error
ADD_DI. See Add Double Integer
Beginning of a logic string, 2-10
ADD_I. See Add Integer
BIE. See Exception Bit Binary Result,
ADD_R. See Add Real
SIMATIC mnemonic
Address
Binary input
box with address, 2-2
inserting, 4-7
box with address and value, 2-2
negating, 4-8
description, 3-4
Binary Result bit (BR), status bit, 2-13
element, 3-2
Binary result bit (BR)
label of a jump instruction, 14-2
Exception Bit Binary Result (BR), 15-3
types, 3-4
Exception Bit Unordered (UO), 15-6
Address identifier, 3-4
save RLO to BR memory, 4-11
Address Negative Edge Detection (NEG), 4-31
Bit logic, practical applications, B-3–B-6
Address Positive Edge Detection (POS), 4-30

C79000-G7076-C566-01 Index-1
Index
Bit logic instruction Call FC/SFC without Parameters (CALL),

Address Negative Edge Detection (NEG), 16-2–16-3
4-31 Calling function blocks
Address Positive Edge Detection (POS), as a box, 16-4–16-6
4-30 effects of a call on the status bits, 16-4
assignment (=), 4-9 supplying parameters, 16-6
connector, 4-10 Calling functions
down counter (CD), 4-17 as a box, 16-4–16-6
Extended Pulse Timer (SE), 4-20 effects of a call on the status bits, 16-4
insert binary input, 4-7 supplying parameters, 16-6
negate binary input, 4-8 with the Call FC/SFC without Parameters
Negative RLO Edge Detection (N), 4-29 instruction, 16-2
Off-Delay Timer (SF), 4-26 Calling system function blocks
On-Delay Timer (SD), 4-22 as a box, 16-4–16-6
Positive RLO Edge Detection, 4-28 effects of the call on the status bits, 16-4
Pulse Timer (SP), 4-18 supplying parameters, 16-6
Reset output (R), 4-13 Calling system functions
Reset_Set Flip Flop, 4-33 effects of the call on the status bits, 16-4
Retentive On-Delay Timer (SS), 4-24 supplying parameters, 16-6
save RLO to BR memory, 4-11 with the Call FC/SFC without Parameters
set counter value (SC), 4-14 instruction, 16-2
set output (S), 4-12 CC1 and CC0. See Condition code bits (CC1
Set_Reset Flip Flop, 4-32 and CC0)
up counter (CU), 4-16 CD. See Down Counter, international mnemonic
Bit logic instructions, 4-2 CEIL. See Ceiling
See also Status bit instructions Ceiling (CEIL), 10-16
practical application, B-3–B-6 Character (CHAR), range, 3-3
Bit logic operation Checking the condition code bits (CC1 and
AND, 4-3 CC0), 2-11
AND-before-OR, 4-5 CMP_D. See Compare Double Integer
EXCLUSIVE OR logic operation, 4-6 CMP_I. See Compare Integer
OR, 4-4 CMP_R. See Compare Real
OR-before-AND, 4-5 Compare Double Integer (CMP_D), 9-3
Bits of the status word, changing, 2-9 Compare Integer (CMP_I), 9-2
Blocks Compare Real (CMP_R), 9-4
calling, 16-2–16-3 Comparing the result of math instruction with
exiting, 16-7 zero, 15-4
Boolean (BOOL), range, 3-3 Comparison instructions
Boolean logic, 2-6–2-8 Compare Double Integer, 9-3
Box, instruction as box, 2-2 Compare Integer, 9-2
BR. See Exception Bit Binary Result, Compare Real, 9-4
international mnemonic practical applications, B-11–B-12
Byte, range, 3-3 Condition code bits (CC1 and CC0), 2-11
and Exception Bit Unordered, 15-6
effects of math instructions, 7-11, 8-7
C relative to the result bit, 15-4–15-5
status bits, 2-11
CALL. See Call FC/SFC without Parameters

Index-2 C79000-G7076-C566-01
Index
Conditional Jump (JMP), 14-4 D

Connector, 4-10
Data block (DB)
Conversion instructions
instance, 16-6
BCD to Integer (BCD_I), 10-3
memory areas, 2-5
BCD to Integer (BDC_I), 10-3
Data block instructions, Open Data Block
Ceiling (CEIL), 10-16
(OPN), 13-2
Double Integer to BCD (DI_BCD), 10-7
Data types, 3-3
Double Integer to Real (DI_R), 10-8
Boolean (BOOL), 3-3
Floor (FLOOR), 10-17
BYTE, 3-3
Integer to BCD (I_BCD), 10-4
character (CHAR), 3-3
Integer to Double Integer (I_DI), 10-5
date (D), 3-3
Negate Real Number (NEG_R), 10-13
double integer (DINT), 3-3
Ones Complement Double Integer
double word (DWORD), 3-3
(INV_DI), 10-10
integer (INT), 3-3
Ones Complement Integer (INV_I), 10-9
REAL, 3-3
Round to Double Integer (ROUND), 10-14
S5 TIME, 3-3
Truncate Double Integer Part (TRUNC),
time (T), 3-3
10-15
time of day (TOD), 3-3
Twos Complement Double Integer
WORD, 3-3
(NEG_DI), 10-12
DI_BCD. See Double Integer to BCD
Twos Complement Integer (NEG_I), 10-11
DI_R. See Double Integer to Real
Count, up/down, 6-3
DIV_DI. See Divide Double Integer
Count value
DIV_I. See Divide Integer
format, 6-2
DIV_R. See Divide Real
range, 6-2
Divide Double Integer (DIV_DI), 7-9
Counter, instructions with counters
Divide Integer (DIV_I), 7-8
down counter (CD), 4-17
Divide Real (DIV_R), 8-6
set counter value (SC), 4-14
Double integer (DINT), range, 3-3
up counter (CU), 4-16
Double Integer to BCD (DI_BCD), 10-7
Counters
Double Integer to Real (DI_R), 10-8
address range, 2-4, 2-5
Double word, as data object, 3-5
count instructions, Up Counter/Down
Double word (DWORD), range, 3-3
Counter (S_CUD), 6-3
Down counter (CD), 4-17
count value
Down Counter (S_CD), 6-7–6-8
format, 6-2
range, 6-2
instructions used with counters, practical
applications, B-11–B-12 E
memory area, 6-2 Edge detection, 4-28
supported counters, 6-2 Element, instruction as, 2-2
Counting Element assignment (=), 4-9
down, 4-17, 6-7–6-8 EN. See Enable input (EN)
up, 4-16, 6-5–6-6 EN / ENO, meaning, 2-14
CPU register, 2-9 Enable input (EN), parameters, 2-3
count value in a counter, 6-2 Enable output (ENO)
status word, 2-9 See also BR bit
time value in timer cell, 5-3 parameters, 2-3
CPU registers, function, 2-9 ENO. See Enable output (ENO)
CU. See Up Counter, international mnemonic

C79000-G7076-C566-01 Index-3
Index
Examples, practical application of instructions, Floating-point math, 8-2

B-2 Arc Cosine (ACOS), 8-13–8-15
Exception Bit Binary Result (BR), 15-3 Arc Sine (ASIN), 8-13–8-14
Exception Bit Overflow (OV), 15-7 Arc Tangent (ATAN), 8-13
Exception Bit Overflow Stored (OS), effects on the bits of the status word, 8-7
15-8–15-10 result within the valid range, 8-7
Exception Bit Unordered (UO), 15-6 Floor (FLOOR), 10-17
and floating-point math, 15-6 Format
Exclusive OR, truth table, 2-8 count value, 6-2
Extended Pulse S5 Timer (S_PEXT), 5-7–5-8 time value, 5-2
Extended Pulse Timer (SE), 4-20 Function Block Diagram, 1-1
Function blocks (FBs)
calling FBs as a box, 16-4–16-6
F supplying parameters, 16-6
Functions (FCs)
FBD, explanation, 1-1
calling FCs as a box, 16-4–16-6
First Check (FC), 2-10–2-14
calling FCs with the Call FC/SFC without
result, 2-10
Parameters instruction, 16-2
status bit, 2-10
supplying parameters, 16-6
Flip flop, 4-32
Reset_Set, 4-33
Set_Reset, 4-32
Floating-point math G
and exception bit unordered (UO), 15-6 German SIMATIC names and SIMATIC
Subtract Double Integer (SUB_DI), 7-5 mnemonics, alphabetical list, A-10
Floating-point math instructions
Add Real (ADD_R), 8-3
Divide Real (DIV_R), 8-6 I
Multiply Real (MUL_R), 8-5
I/O external inputs and outputs, address range,
Subtract Real (SUB_R), 8-4
2-4, 2-5
Floating-point numbers
I_BCD. See Integer to BCD
Compare Real, 9-4
I_DI. See Integer to Double Integer
data type for. See Real number, data type

Index-4 C79000-G7076-C566-01
Index
Input Instructions
inserting, 4-7 alphabetical list, A-10–A-24
negating, 4-8 German SIMATIC names and SIMATIC
Input parameter, as part of a box, 2-3 mnemonics, A-10
Instance data block (DI), 16-6 international names and international
Instruction mnemonics, A-2
as box with address, 2-2 international names and SIMATIC
as box with address and value, 2-2 equivalents, A-6
as box with parameters, 2-3 SIMATIC names and international
as element, 2-2 equivalents, A-14
SIMATIC names with SIMATIC
mnemonics and international
mnemonics, A-17
bit logic instructions, 4-2
practical application, B-3
comparison, practical applications,
B-11–B-12
counter, practical applications, B-11–B-12
dependent on Master Control Relay (MCR),
16-8
evaluating the condition code bits (CC1 and
CC0), 7-11, 8-7
evaluating the OS bit, 7-11, 8-7
evaluating the OV bit, 7-11, 8-7
floating-point math, 8-7
effects on the bits of the status word, 8-7
result within the valid range, 8-7
integer math instructions, 7-11
effects on the bits of the status word,
7-11
valid range for results, 7-11
jump instructions, 14-2
math instructions with integers, practical
applications, B-13
practical application, B-2
result bits, 15-4–15-5
rotate instructions, 12-10–12-12
shift instructions, 12-2–12-10
status bit instructions, 15-2–15-10
timer, practical applications, B-7–B-10
word logic, practical applications,
B-14–B-15
word logic instructions, practical
applications, B-14–B-16
Integer (INT), range, 3-3

C79000-G7076-C566-01 Index-5
Index
Integer math instructions M

Add Double Integer (ADD_DI), 7-3
Master Control Relay (MCR)
Add Integer (ADD_I), 7-2
effects on the instructions Set Output (S) and
Divide Double Integer (DIV_DI), 7-9
Reset Output (R), 16-8
Divide Integer (DIV_I), 7-8
important notes, 16-9
effects on the bits of the status word, 7-11
Master Control Relay (MCR) instructions,
Multiply Double Integer (MUL_DI), 7-7
16-8–16-9
Multiply Integer (MUL_I), 7-6
Master Control Relay Activate (MCRA),
Return Fraction Double Integer (MOD_DI),
16-10
7-10
Master Control Relay Deactivate (MCRD),
Subtract Integer (SUB_I), 7-4
16-10
valid range for results, 7-11
Master Control Relay Off (MCR>), 16-13
Integer to BCD (I_BCD), 10-4
Master Control Relay On (MCR<),
Integer to Double Integer (I_DI), 10-5
16-13–16-16
Integers, comparing, 9-2, 9-3
nesting, 16-14
International names and German SIMATIC
equivalents, alphabetical list, A-6
16-10–16-16
International names with international
mnemonics, alphabetical list, A-2
16-10–16-16
International names with SIMATIC mnemonics
Master Control Relay Off (MCR), 16-13–16-16
and international mnemonics, alphabetical
Master Control Relay On (MCR<), 16-13–16-16
list, A-17
Math instructions, practical applications with
INV_DI. See Ones Complement Double Integer
integers, B-13
INV_I. See Ones Complement Integer
MCR Functions, important notes, 16-9
MCR<. See Master Control Relay On
MCR>. See Master Control Relay Off
J MCRA. See Master Control Relay Activate
JMP. See Conditional Jump; Unconditional MCRD. See Master Control Relay Deactivate
Jump Memory area, process input image, 2-4
Jump instruction, jump label as address, 14-2 Memory areas, 2-3
Jump instructions, 14-2 bit memory, 2-4
conditional Jump (JMP), 14-4 counters, 2-4
unconditional jump, 14-3 data block, 2-4
Jump label, as address of the jump instruction, I/Os (external inputs and outputs), 2-4
14-2 inputs and outputs, 2-4
local data, 2-4
process input image, 2-4
L process output image, 2-4
timers, 2-4
Languages, switching between LAD, FBD, and
MOD_DI. See Return Fraction Double Integer
STL, 1-1
MOVE. See Assign Value
Loading a count value
Move instructions, Assign Value, 10-2
format, 6-2
MUL_DI. See Multiply Double Integer
range, 3-3
MUL_I. See Multiply Integer
Loading a time value
MUL_R. See Multiply Real
format, 5-2
Multiple instances, calling, 16-6
range, 3-3
Multiply Double Integer (MUL_DI), 7-7
Local data, memory area, address range, 2-4,
Multiply Integer (MUL_I), 7-6
2-5

Index-6 C79000-G7076-C566-01
Index
Multiply Real (MUL_R), 8-5 Pointer, 3-5

POS. See Address Positive Edge Detection
Positive RLO edge detection (P), 4-28
N Process input image, memory area, 2-4
address range, 2-5
N. See Negative RLO Edge Detection
Process output image, memory area, 2-4
NEG. See Address Negative Edge Detection
address range, 2-5
NEG_DI. See Twos Complement Double
Program control instructions
Integer
Call FC/SFC without Parameters (CALL),
NEG_I. See Twos Complement Integer
16-2–16-3
NEG_R. See Negate Real Number
Negate Real Number (NEG_R), 10-13
16-10–16-12
Negative RLO Edge Detection (N), 4-29
Nesting, Master Control Relay (MCR), 16-14
16-10
Master Control Relay Off (MCR>),
16-13–16-16
O Master Control Relay On (MCR<),
Off-Delay S5 Timer (S_OFFDT), 5-13–5-14 16-13–16-16
On-Delay S5 Timer (S_ODT), 5-9–5-10 Return (RET), 16-7
Ones Complement Double Integer (INV_DI), Programming, practical applications, B-2
10-10 Pulse S5 Timer (S_PULSE), 5-5–5-6
Ones Complement Integer (INV_I), 10-9 Pulse Timer (SP), 4-18
Open Data Block (OPN), instruction, 13-2
OPN. See Open Data Block, international
mnemonic R
OR, 4-4
R. See Reset output
truth table, 2-7
Real number
OR status bit, 2-11
data type, 3-3
OR-before-AND, 4-5
range, 3-3
OS. See Exception Bit Overflow Stored
Register, CPU, 2-9–2-14
OS bit (stored overflow)
Reset output (R), 4-13
Exception Bit Overflow Stored (OS),
Resolution. See Time base for S5 TIME
15-8–15-10
Result bits
status bit, 2-11
checking the condition code bits (CC1 and
Output parameter, as part of the structure of a
CC0), 2-11
box, 2-3
instructions, 15-4–15-5
OV. See Exception Bit Overflow
Result of logic operation, description, 2-6
OV bit (overflow)
Result of logic operation (RLO)
Exception Bit Overflow (OV), 15-7
status bit, 2-6
status bit, 2-11
status word bit, 2-10–2-11
Overflow (OV), effects of math instructions,
RET. See Return instruction
7-11, 8-7
Retentive On-Delay Timer (S_ODTS),
5-11–5-12
Retentive on-delay timer (SS), 4-24
P Return Fraction Double Integer (MOD_DI),
P. See Positive RLO Edge Detection 7-10
Parameter Return instruction (RET), 16-7
Enable input (EN), 2-3 RLO. See Result of Logic Operation
Enable output (ENO), 2-3 ROL_DW. See Rotate Left Double Word
inputs and outputs as part of a box, 2-3 ROR_DW. See Rotate Right Double Word

C79000-G7076-C566-01 Index-7
Index
Rotate instructions, 12-10–12-12 SC. See Set counter value, international

Rotate Left Double Word (ROL_DW), mnemonic
12-10–12-12 SD. See On-Delay Timer, international
Rotate Right Double Word (ROR_DW), mnemonic
12-11–12-12 SE. See Extended Pulse Timer, international
Rotate Left Double Word (ROL_DW), mnemonic; On-Delay Timer, SIMATIC
12-10–12-12 mnemonic
Rotate Right Double Word (ROR_DW), Set counter value, 4-14
12-11–12-12 Set counter value (SC), 4-14
ROUND. See Round to Double Integer Set output (S), 4-12
Round to Double Integer (ROUND), 10-14 SF, 4-26
RS. See Reset_Set Flip Flop Shift instructions, 12-2–12-9
Shift Left Double Word (SHL_DW),
12-4–12-9
S Shift Left Word (SHL_W), 12-2–12-9
Shift Right Double Integer (SHR_DI), 12-9
S. See Set output
Shift Right Double Word (SHR_DW),
S_AVERZ. See Off-Delay S5 Timer, SIMATIC
12-6–12-9
mnemonic
Shift Right Integer (SHR_I), 12-7–12-9
S_CD. See Down Counter, international
Shift Right Word (SHR_W), 12-5–12-9
mnemonic
Shift Left Double Word (SHL_DW), 12-4–12-9
S_CU. See Up Counter, international mnemonic
Shift Left Word (SHL_W), 12-2–12-9
S_CUD. See Up Counter/Down Counter,
Shift Right Double Integer (SHR_DI), 12-9
international mnemonic
Shift Right Double Word (SHR_DW),
S_EVERZ. See On-Delay S5 Timer, SIMATIC
12-6–12-9
mnemonic
Shift Right Integer (SHR_I), 12-7–12-9
S_IMPULS, 5-5
Shift Right Word (SHR_W), 12-5–12-9
S_ODT. See On-Delay S5 Timer, international
SHL_DW. See Shift Left Double Word
mnemonic
SHL_W. See Shift Left Word
S_ODTS. See Retentive On-Delay S5 Timer,
SHR_DI. See Shift Right Double Integer
SHR_DW. See Shift Right Double Word
S_OFFDT. See Off-Delay S5 Timer,
SHR_I. See Shift Right Integer
SHR_W. See Shift Right Word
S_PEXT. See Extended Pulse S5 Timer,
SI. See Pulse Timer, SIMATIC mnemonic
SIMATIC names and international equivalents,
S_PULSE. See Pulse S5 Timer instruction
alphabetical list, A-14
S_SEVERZ. See Retentive On-Delay S5 Timer,
SP. See Pulse Timer, international mnemonic
SIMATIC mnemonic
SR. See Set_Reset Flip Flop
S_VIMP. See Extended Pulse S5 Timer,
SS. See Retentive On-Delay Timer
SIMATIC mnemonic
STA. See Status bit
S5 TIME
Status bit (STA), 2-11
range, 3-3
time base, 5-2
time value, 5-2
SA. See Off-Delay Timer, SIMATIC mnemonic
SAVE. See Save RLO to BR Memory
Save RLO to BR memory (SAVE), 4-11

Index-8 C79000-G7076-C566-01
Index
Status bit instructions, 15-2 System functions (SFCs)

Exception Bit Binary Result (BR), 15-3 calling SFCs as a box, 16-4–16-6
Exception Bit Overflow (OV), 15-7 supplying parameters, 16-6
Exception Bit Overflow Stored (OS), 15-8 SZ. See Set counter value, SIMATIC mnemonic
Exception Bit Unordered (UO), 15-6
result bits, 15-4–15-5
Status word T
binary result bit (BR bit), 15-3
Time base, resolution, 5-3
Binary Result bit (BR), 2-13
Time base for S5 TIME, 5-2–5-14
bits affected by math instructions, 7-11, 8-7
Time of day (TOD), range, 3-3
changing the bits, 2-9
Time resolution. See Time base for S5 TIME
condition code bits (CC1 and CC0), 2-11
Time value, 5-3
and Exception Bit Unordered (UO), 15-6
format in timer cell, 5-3
relative to the result bit instructions,
range, 5-3–5-14
15-4–15-5
reading, 5-3
description, 2-9
syntax, 5-2
effects of calling an FB, FC, SFB or SFC on
Timer, instructions with timers
the status bits, 16-4
Extended Pulse Timer (SE), 4-20
EN = 0, 2-14
Off-Delay Timer (SF), 4-26
EN = 1, 2-14
On-Delay Timer (SD), 4-22
Exception Bit Overflow, 15-7
Pulse Timer (SP), 4-18
Exception Bit Overflow Stored, 15-8–15-10
Retentive On-Delay Timer (SS), 4-24
First Check (FC), 2-10
Timers
OR bit, 2-11
address range, 2-5
OS bit (stored overflow), 2-11
components, 5-2–5-3
OV bit (overflow), 2-11
Extended Pulse S5 Timer (S_PEXT),
result of logic operation (RLO) bit,
5-7–5-8
2-10–2-11
instructions used with timers, practical
specifying the invalid range for integer math
applications, B-7–B-10
instructions, 7-11
memory area, 5-2
specifying the valid range for integer math
numbers supported, 5-2
instructions, 7-11
overview, 5-4
Status bit (STA), 2-11
Pulse S5 Timer (S_PULSE), 5-5–5-6
status bit instructions, 15-2–15-10
reading the time and the time base, 5-3
structure, 2-9, 15-2
time value, 5-2
Stored overflow (OS), effects of math
range, 5-2–5-14
instructions, 7-11, 8-7
syntax, 5-2
String of logic operations
timer instructions
definition, 2-10
Off-Delay S5 Timer (S_OFFDT), 5-13
end, 2-10
On-Delay S5 Timer (S_ODT), 5-9
SUB_DI. See Subtract Double Integer
Retentive On-Delay S5 Timer
SUB_I. See Subtract Integer
(S_ODTS), 5-11
SUB_R. See Subtract Real
TRUNC. See Truncate Double Integer Part
Subtract Double Integer (SUB_DI), 7-5
Truncate Double Integer Part (TRUNC), 10-15
Subtract Integer (SUB_I), 7-4
Truth table
Subtract Real (SUB_R), 8-4
AND, 2-6
SV. See Extended Pulse Timer, SIMATIC
exclusive OR, 2-8
mnemonic
OR, 2-7
Symbolic addressing, practical example, B-3
Twos Complement Double Integer (NEG_DI),
System function blocks (SFBs)
10-12
calling SFBs as a box, 16-4–16-6
Twos Complement Integer (NEG_I), 10-11
supplying parameters, 16-6

C79000-G7076-C566-01 Index-9
Index
U WXOR_DW. See (Word) Exclusive OR Double

Word instruction
Unconditional Jump (JMP), 14-3
WXOR_W. See (Word) Exclusive OR Word
UO. See Exception Bit Unordered
instruction
Up Counter, (S_CU), 6-5–6-6
Up counter, CU, 4-16
Up Counter/Down Counter (S_CUD), 6-3
X
XOR, 4-6
W
WAND_DW. See (Word) AND Double Word
instruction Z
WAND_W. See (Word) AND Word instruction Z_RUECK. See Down Counter, SIMATIC
WOR_DW. See (Word) OR Double Word mnemonic
instruction Z_VORW. See Up Counter, SIMATIC
WOR_W. See (Word) OR Word instruction mnemonic
WORD, range, 3-3 ZAEHLER. See Up Counter/Down Counter,
Word, as data object, 3-5 SIMATIC mnemonic
Word logic instructions ZR. See Down Counter, SIMATIC mnemonic
(Word) AND Double Word (WAND_DW), ZV. See Up Counter, SIMATIC mnemonic
11-4–11-5
(Word) AND Word (WAND_W), 11-3–11-4
(Word) Exclusive OR Double Word
(WXOR_DW), 11-8–11-9
(Word) Exclusive OR Word (WXOR_W),
11-7–11-8
(Word) OR Double Word (WOR_DW),
11-6–11-7
(Word) OR Word (WOR_W), 11-5–11-6
practical applications, B-14–B-16

Index-10 C79000-G7076-C566-01
Siemens AG
A&D AS E81
Oestliche Rheinbrueckenstr. 50
D-76181 Karlsruhe
Federal Republic of Germany
From:
Your Name: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Your Title: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Company Name: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Street: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
City, Zip Code_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Country: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Phone: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Please check any industry that applies to you:
r Automotive r Pharmaceutical
r Chemical r Plastic
r Electrical Machinery r Pulp and Paper
r Food r Textiles
r Instrument and Control r Transportation
r Nonelectrical Machinery r Other _ _ _ _ _ _ _ _ _ _ _
r Petrochemical

$
C79000-G7076-C566-01 1
Remarks Form
Your comments and recommendations will help us to improve the quality and usefulness
of our publications. Please take the first available opportunity to fill out this questionnaire
and return it to Siemens.
Please give each of the following questions your own personal mark within the range
from 1 (very good) to 5 (poor).
1. Do the contents meet your requirements?
2. Is the information you need easy to find?
3. Is the text easy to understand?
4. Does the level of technical detail meet your requirements?
5. Please rate the quality of the graphics/tables:
Additional comments:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

2 C79000-G7076-C566-01

Siemens Simatic S 7 300 - 400 - Function Block Diagram For S7-300 and S7-400

Încărcat de

Informații document

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Siemens Simatic S 7 300 - 400 - Function Block Diagram For S7-300 and S7-400

Încărcat de

Drepturi de autor:

Formate disponibile

Preface, Contents

Bit Logic Instructions 4

Floating-Point Math Instructions 8

Word Logic Instructions 11

Shift and Rotate Instructions 12

Data Block Instructions 13

Status Bit Instructions 15

Program Control Instructions 16

Correct Usage Note the following:

Copyright Siemens AG 1998 All rights reserved 

Siemens Aktiengesellschaft C79000-G7076-C566

Function Block Diagram (FBD) for S7-300 and S7-400

Audience The manual is intended for S7 programmers, operators, and

Function Block Diagram (FBD) for S7-300 and S7-400

Documentation Purpose Order Number

Online Helps Purpose Order Number

References References to other documentation are indicated by reference numbers in

Function Block Diagram (FBD) for S7-300 and S7-400

Function Block Diagram (FBD) for S7-300 and S7-400

Function Block Diagram (FBD) for S7-300 and S7-400

Function Block Diagram (FBD) for S7-300 and S7-400

4.18 On-Delay Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22

Function Block Diagram (FBD) for S7-300 and S7-400

8 Floating-Point Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

Function Block Diagram (FBD) for S7-300 and S7-400

11 Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

Function Block Diagram (FBD) for S7-300 and S7-400

A.2 List of Instructions with International (English) Names and German

Function Block Diagram (FBD) for S7-300 and S7-400

Function Block Diagram (FBD) for S7-300 and S7-400

Function Block Diagram (FBD) for S7-300 and S7-400

Function Block Diagram (FBD) for S7-300 and S7-400

2.1 Elements and Box Structure

Table 2-1 FBD Instruction as an Element without Address or Parameters

Element Description Section in this Manual

Negate binary input 4.7

Table 2-2 FBD Instruction as Box with Address

Element Description Section in this Manual

Table 2-3 FBD Instruction as a Box with Address and Value

Element Description Section in this Manual

Function Block Diagram (FBD) for S7-300 and S7-400

Table 2-4 FBD Operation as a Box with Inputs and Outputs

Box Description Section in this Manual

Function Block Diagram (FBD) for S7-300 and S7-400

Table 2-5 Memory Areas and Their Functions

Function Block Diagram (FBD) for S7-300 and S7-400

Table 2-6 Memory Areas and Their Address Ranges

Data bit in the data block DBX 0.0 to 65 535.7

Data bit in the instance DB DIX 0.0 to 65 535.7

Function Block Diagram (FBD) for S7-300 and S7-400

2.2 Boolean Logic and Truth Tables

& The condition is satisfied when the

Figure 2-1 AND Logic Operation in FBD

The possible results of an AND logic operation can be represented in a truth

Table 2-7 AND Truth Table

Function Block Diagram (FBD) for S7-300 and S7-400

>=1 The condition is satisfied when the

Figure 2-2 OR Logic Operation in FBD

The possible results of an OR logic operation can be shown in a truth table.

Table 2-8 OR Truth Table

XOR The condition is satisfied when the

Figure 2-3 Exclusive OR Logic Operation in FBD

Function Block Diagram (FBD) for S7-300 and S7-400

Copyright Siemens AG 1998 All rights reserved