EECS 170 Winter 2013 Due Tuesday Week 8 HW 5 1. A 2-input XOR gate is defined as Y = A B + A B .

. A 3-input XOR is defined recursively as shown below:

A B C

(a) Express Y in terms of A, B and C. Is this an Even parity checker or an Odd parity checker? (b) Implement a 3-input XOR gate using CMOS circuit. 2. 3. 4. Implement Y = A + C ( B + D) using CMOS circuit Implement Y Y = A B C + A B C using CMOS circuit Design a CMOS full-adder circuit with inputs A, B, and C, and two outputs S and Co such that S is 1 if one or three inputs are 1 and o is 1 is two or more inputs are 1. 5. 10.34 (Transistor Sizing): Find appropriate sizes for transistors used in the XOR circuit in the text (see figure below). Assume that the basic inverter has (W/L)n = 0.75m/0.5m and (W/L)p = 3.0m/0.5m. What is the total area, including that of the required inverters?

6. 10.35 (Transistor Sizing): Consider a 4-input CMOS NAND gate for which the transient response is dominated by CL. Compare the values of tpLH and tPHL obtained when the devices are sized as in Fig. 10.17 (see below), to the values obtained when all NMOSs have W/L = n and all PMOSs have W/L = p.

7. The purpose of this problem is to put physical layout of an acutal CMOS circuit into perspective. Consider following CMOS 2-inputs NAND terminated with a load capacitor. (Vdd = 5V, and Vss = 0V) (a) The inputs {A, B} are {1,0} initially. At t = 0, the inputs change to {1, 1}, indicate the flow of current during the switching process. Is the load capacitor charging or discharging? (b) The input is then switched from {1, 1} to {0, 0}, indicate the flow of current during the switching process. Is the load capacitor charging or discharging?
A 1 1 0 0 B 1 0 1 0 Y 0 1 1 1

CL