27/12/12

Wire Assignments

Wire Assignments
A w ire can be declared and continuously assigned in a single statement - a w ire assignment. This is a shortcut w hich saves declaring and assigning a w ire separately. There are no advantages or disadvantages betw een the tw o methods other than the obvious difference that w ire assignments reduce the size the the text. Later on w e w ill discuss delays on assignments and w ires. A delay in a w ire assignment is equivalent to a delay in the corresponding continuous assignment, not a delay on the w ire. Thus it could be necessary to separate the w ire declaration from the continuous assignment to put the delay onto the w ire rather than the assignment. Note that this is a subtle point that you are unlikely to encounter in practice!

Verilog: Using wire assignments to describe an AOI gate module

/ /V e r i l o gc o d ef o rA N D O R I N V E R Tg a t e m o d u l eA O I( i n p u tA ,B ,C ,D ,o u t p u tF ) ; / * s t a r to fab l o c kc o m m e n t w i r eF ; w i r eA B ,C D ,O ; a s s i g nA B=A&B ; a s s i g nC D=C&D ; a s s i g nO=A B|C D ; a s s i g nF=~ O ; e n do fab l o c kc o m m e n t* / / /E q u i v a l e n t . . . w i r eA B=A&B ; w i r eC D=C&D ; w i r eO=A B|C D ; w i r eF=~ O ; e n d m o d u l e / /e n do fV e r i l o gc o d e So in this sample code, each of the w ire declarations and its corresponding assign statement are effectively merged into one w ire assignment. Note the use of a block comment in the Verilog code, rather than the line comments w e have seen so far. A block comment may span several lines of code. Block comments may not be nested. Prev Next Copyright 2005-2012 Doulos. All rights reserved.

www.doulos.com/knowhow/verilog_designers_guide/wire_assignments/

1/1