Interface Sec 1c

Typical Application
Optical Interface
10G Line Card

SerDes
XSBI LVDS XAUI XGMII
MAC
LVDS
National's SCAN50C400
CML
Switch Fabric Card

National's SCAN50C400
LVDS CML
Backplane
Gigabit Ethernet Card

GBE Legacy SerDes
GMII TBI
MAC
Legacy SerDes
LVDS
CML
FR-4 SCAN50C400
Analog Technical Seminar, Asia October 2004
J - 81 2004 National Semiconductor Corporation
LVDS versus CML

LVDS is TIA/EIA644-A Standard No Standard for CML LVDS operates in multiple configurations up to approximately 1 Gbps CML operates up to 10 Gbps but limited to pointto-point applications
LVDS 1Gbps CML
Differential I/O Comparisons

4V 3V 2V 1V 0V -1V -2V
PECL CML 3.3 LVPECL LVDS Bus LVD S CML 1.2 RS-422
D
ECL
VOD V
B
VA
Gnd
LVDS CML AC
SCAN50C400 Quad 5 Gbps SerDes

Quad 5 Gbps SerDes 4 x 1.25 Gbps LVDS parallel bus 625 MHz clock 5 Gbps CML serial interface IEEE 802.3ae Compatible MDIO management & control interface Testability Features Sampling Now!
SCAN50C400 Simplified Diagram (5 Gbps Mode)

This is the primary operating mode
1.25 Gbps LVDS 5 Gbps CML
b c d or a
c d a b
or
d a b c
SCAN50C400 1.25 Gbps 5 Gbps 4
De-emphasis Feature
After 16 of the Tyco backplane (no de-emphasis) After 16 of the Tyco backplane with de-emphasis
0.62 UI of Jitter with PRBS-7 Pattern
0.33 UI of Jitter with PRBS-7 Pattern
De-emphasis not only helps reduce crosstalk but also reduces the DJ caused by the backplane.
SCAN50C400 de-emphasis crosstalk DJ
How Equalization Works

From Backplane High Pass Filter Equalized Signal
+
Backplane Response Equalizer Response
=
Total Response
RC filter used to show the effects of equalization on a backplane signal.
Scope shots on 30 Backplane

5 Gbps signal coming out of the backplane.
No de-emphasis or equalization. DJ is approximately 1 UI.
Signal after equalization. The output of the equalizer reduces the jitter from 1UI to 0.33 UI.
FR-4 1.25 Gbps 5 Gbps 30 DJ
Equalization
Virtually No Eye Opening
Recovered with no bit errors!
With equalization, even this signal can be recovered with no bit errors.
EQ50F100
Fixed Equalizer, 6.25 Gbps Max

Pr
Offset Cancellation VDD
od
uc
tP
50 IN+ 100 INEqualizer Filter Limiter
50
re
OUT+ OUT-
vi
ew
The EQ50F100 is a single channel adaptive equalizer Equalize up to 25dB loss at 2.5GHz 45ps residual deterministic jitter at 5 Gbps Small 3mm x 3mm 6-pin leadless LLP package Single 1.8V power supply Low power consumption: 90mW On-chip CML terminations Samples available now
EQ50F100
Potential Benefits from using a FPGA with LVDS I/O and SerDes
Reduce the number of wires on the PCB because all parallel signals to SERDES are internal to the FPGA. Reduce the number of components on PCB However, the un-terminated trace length to the connector becomes longer limiting maximum performance Potential to reduce power consumption Depends on the application and number of LVDS I/O resources used on the FPGA
FPGA I/O FAB FPGA I/O National LVDS 2Gbps I/O 3Gbps I/O LVDS 3.3V FPGA LVDS I/O 2.5V 3.3V LVDS LVDS IC LVDS 4kV ESD FPGA LVDS LVCMOS FPGA FPGA LVDS FPGA VCC I/O I/O
Analog Technical Seminar, Asia October 2004 J - 92 2004 National Semiconductor Corporation
Disadvantages to using FPGA with LVDS I/O and SerDes

The FGPA LVDS signal integrity is poor for speeds > 500 Mbps final test and yield becomes an issue for the FPGA that must meet analog performance criteria - can not afford to suffer yield hit due to I/O analog performance Wasteful of LVDS+SERDES resource unless customer can use all of them. For applications that need less than 4 LVDS channels, FPGA LVDS is definitely not suitable. Limited options of compression ratio 1:4, 1:7, 1:8, 1:10 & 1:20 only. Difficult to trouble shoot and expansive to replace Imagine replacing a $8 LVDS chip vs. $300 FPGA if one of the LVDS channel is down !
Advantages in using Nationals LVDS Buffers, Bus LVDS & SerDes

NSC is recognized as LVDS industry expert NSC can make make recommendations based on specific application requirements Improve the ESD protection for cable and backplane applications Improve signal integrity and drive distance Use Nationals application specific LVDS I/O for cables and backplanes FPGA I/O is programmable and not best suited for any single application (output loading capacitance is double Nationals) Enables using lower cost FPGA LVDS I/O and SERDES cells are an expensive addition FPGA LVDS I/O is hard to troubleshoot and expensive to replace FPGA vendors tend to have a software focus. NSC FAEs are experts in signal integrity and analog design. Improve EMI performance
Saving FPGA I/O Resources
Problem
FPGA LVDS I/O consumes valuable resources and requires different VCCIO level Use LVDS splitter to make multiple copies of signal Better LVDS performance Lower EMI
Solution
FMAX vs. Stub Length

Small Backplane
Higher FMAX indicates better performance
350 300
Frequency [MHz]
250 200 150 100 50 0 0.5 1 2 Stub Length [in] 3 4 DS92001 Virtex-II
stubDS92001 stub hider 150200 MHz FPGA DS92001 Virtex-II FPGA FMAX
FPGA vs. Discrete Bus LVDS

Backplane Performance
18-Slot, 18 Backplane at 100 Mbps (50 MHz clock)
DS92LV090A with 1 stub
Virtex-II with 1 stub
7-Slot, 7 Backplane at 100 Mbps (50 MHz clock)
DS92001 with 0.5 Stubs
Virtex-II with 2 Stubs
18 1 50MHz Virtex-II 7 LVDS DS92001 8 SOIC
SCAN90CP02 vs. FPGAs

50 feet (15 m) CAT5 Cable
SCAN90CP02 Xilinx Virtex-II
640 Mbps No Pre-Emphasis
640 Mbps
SCAN90CP02
SCAN90CP02
640 Mbps 100% Pre-Emphasis
1500 Mbps 100% Pre-Emphasis
FPGA Xilinx Virtex-II LVDS
Designing with Nationals LVDS products
LVDS
Which Product Should I Use?

Each product is optimized for a certain set of applicationsthere is no universal solution Match output driver characteristics to application
drive strength higher for driving lower impedances lower for less power, noise, etc. edge rates slower for longer stubs faster for cable & point-to-point applications simulate, especially for complex buses
LVDS LVDS Channel Link I/O
Recommended Design Practices for NSCs Chips

Read the datasheet thoroughly, especially recommended or required operating conditions. Use evaluation board designs as reference. Operate devices within datasheet temperature and voltage limits. Follow proper ESD and handling procedures. Understand and follow system standards. Use HF/RF and best analog design practices.
What Not to Do...

Connect more than 1 power or ground pin to 1 via. Exceed temperature or voltage ratings. Use outside of data rate or frequency limits. Overload outputs or overdrive inputs. Allow electrical overstress or ESD. Omit LF (electrolytic) bypassing. Omit RF (ceramic) bypassing.
Design Review Checklist

Correct supply voltages at all pins? Have bypass capacitors? Correct values? All input levels correct? Input signals clean & correct frequency? I/P common-mode voltages within range? Outputs loaded correctly? Not overloaded?
Design Review Checklist

Have terminations where needed? Separate vias used for every power pin? High-gain, wide-band I/Ps isolated? Clocks are correct frequency? Have good PCB layout? Checked datasheet? Application notes? FAQs? (www.national.com)
Typical Applications
LVDS
Multi-Market Application Examples
Industrial Color Cameras Copiers
Storage Area Networks
Scoreboards Industrial
Printers
DVD R/W
SerDes 30 30 MHz Storage Area Networks
Laser Printers / Copiers
FPGA or ASIC
Tx
LVDS 155 Mbps
Rx
Laser Diode
Inkjet/Bubblejet Printers
FPGA or ASIC
Tx
LVDS 80 -155Mbps
Rx
Print Head
DS90LV049 Dual LVDS Transceiver Application
Tx
ASIC CONTROLLER
Rx Tx Rx
LVDS @ 200 Mbps
Tx Rx Tx Rx
LIO Internal Print Server
Telecom/Wireless
ATM Platforms Digital Loop Carriers Central Office Switch Access Platforms Add Drop Mux Platforms
RT
>400 Mbps LVDS Backplane

RT
Transceivers Serializers Tx/Rx PHYs
Multi-Drop Backplane Multi-Point Backplane Switch
LVDS Application Example

Point-to-Point transport of OC-12 (622 Mbps) payload
10m of cable
DS90LV047 DS90LV048
OC-12 octet signaling
DS90LV047
DS90LV048
OC-12 octet signaling
DS90LV019
DS90LV019
78 MHz CLK
78 MHz CLK
STS-12 OC-12
Interface Applications for LVDS in Multiple Markets

Consumer: DVD R/W, sensor connects, flat panels for notebooks, all-in-1s, desktops, workstations, and wearable displays Industrial: backplanes, cameras, graphical flat panels, robotics, control systems, sensor connects Telecom: basestations, access equipment, transmission equipment Datacom: Routers, switches, and access systems Imaging: copiers, printers, cameras Medical: Imaging and sensor interconnect
LVDS LVDS Telecom Datacom PC
LVDS Resources
www.national.com/LVDS
LVDS Applications Notes

www.national.com/lvds
AN - 971 AN - 977 AN - 1040 AN - 1041 AN - 1059 AN - 1060 AN - 1084 AN - 1108 AN - 1109 AN - 1110 AN - 1115 AN - 1123 AN - 1173 AN - 1194 AN - 1217 Introduction to LVDS LVDS Signal Quality BERT for LVDS Channel Link Introduction HSL Jitter & Skew Calculations LVDS Intro. (EDN Feature Article) Parallel Application of Link Chips PCB and Interconnect Design Guidelines Multidrop Applications of Channel Links Power Dissipation of LVDS Drivers DS92LV010A Bus LVDS - Backplane Design topics Sorting Out Backplane Driver Alphabet Soup Clock Distribution with the DS92CK16 Failsafe Biasing of LVDS Buses How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask Wide Bus Applications Using Parallel BLVDS SerDes Devices Enhancing CLC031Jitter Performance with Easyto-use VCXOs
AN - 1238 AN - 1320
LVDS www.national.com/lvds
SOLUTIONS.NATIONAL.COM
solutions.national.com
General Design Resources
LVDS Owners Manual www.national.com/lvdsmanual
RapiDesigner Slide Rule LIT# 633200-001 LIT# 633201-001 (instructions/formulas in application note AN-905)
Coming Soon: Schematic Review Service!
LVDS 3 2005 schematic review service
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Typical Application

10G Line Card

Switch Fabric Card

Gigabit Ethernet Card

Analog Technical Seminar, Asia October 2004

J - 81 2004 National Semiconductor Corporation

LVDS versus CML

LVDS 1Gbps CML

Analog Technical Seminar, Asia October 2004

J - 82 2004 National Semiconductor Corporation

Differential I/O Comparisons

Analog Technical Seminar, Asia October 2004

J - 83 2004 National Semiconductor Corporation

SCAN50C400 Quad 5 Gbps SerDes

Analog Technical Seminar, Asia October 2004

J - 84 2004 National Semiconductor Corporation

SCAN50C400 Simplified Diagram (5 Gbps Mode)

SCAN50C400 1.25 Gbps 5 Gbps 4

Analog Technical Seminar, Asia October 2004

J - 85 2004 National Semiconductor Corporation

0.62 UI of Jitter with PRBS-7 Pattern

0.33 UI of Jitter with PRBS-7 Pattern

SCAN50C400 de-emphasis crosstalk DJ

Analog Technical Seminar, Asia October 2004

J - 86 2004 National Semiconductor Corporation

How Equalization Works

RC filter used to show the effects of equalization on a backplane signal.

Analog Technical Seminar, Asia October 2004

J - 87 2004 National Semiconductor Corporation

Scope shots on 30 Backplane

No de-emphasis or equalization. DJ is approximately 1 UI.

FR-4 1.25 Gbps 5 Gbps 30 DJ

Analog Technical Seminar, Asia October 2004

J - 88 2004 National Semiconductor Corporation

Recovered with no bit errors!

Analog Technical Seminar, Asia October 2004

J - 89 2004 National Semiconductor Corporation

Fixed Equalizer, 6.25 Gbps Max

50 IN+ 100 INEqualizer Filter Limiter

Analog Technical Seminar, Asia October 2004

J - 90 2004 National Semiconductor Corporation

Analog Technical Seminar, Asia October 2004

J - 91 2004 National Semiconductor Corporation

Disadvantages to using FPGA with LVDS I/O and SerDes

Analog Technical Seminar, Asia October 2004

J - 93 2004 National Semiconductor Corporation

Advantages in using Nationals LVDS Buffers, Bus LVDS & SerDes

Analog Technical Seminar, Asia October 2004

J - 94 2004 National Semiconductor Corporation

Saving FPGA I/O Resources

Analog Technical Seminar, Asia October 2004

J - 95 2004 National Semiconductor Corporation

FMAX vs. Stub Length

Analog Technical Seminar, Asia October 2004

J - 96 2004 National Semiconductor Corporation

FPGA vs. Discrete Bus LVDS

DS92LV090A with 1 stub

Virtex-II with 1 stub

7-Slot, 7 Backplane at 100 Mbps (50 MHz clock)

DS92001 with 0.5 Stubs

Virtex-II with 2 Stubs

18 1 50MHz Virtex-II 7 LVDS DS92001 8 SOIC

Analog Technical Seminar, Asia October 2004