library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL; entity state_machine_vhdl is PORT( clock : IN std_logic; reset : IN std_logic; --magistrala Nord-Sud Nr : OUT std_logic; Ng : OUT std_logic; Ny : OUT std_logic; --magistrala Est-Vest Er : OUT std_logic; Eg : OUT std_logic; Ey : OUT std_logic); end state_machine_vhdl;

architecture Behavioral of state_machine_vhdl is TYPE t_state is (red, green, yellow); SIGNAL present_state, next_state : t_state := green; SIGNAL sensor_count : std_logic_vector (3 downto 0); COMPONENT proiect_counter_down PORT( clk : IN std_logic; reset : IN std_logic;

count : OUT std_logic_vector (3 downto 0) ); END COMPONENT; begin Inst_proiect_counter_down:proiect_counter_down PORT MAP( clk => clock, reset => reset, count => sensor_count ); PROCESS(present_state, sensor_count) BEGIN CASE present_state IS WHEN green => next_state <= yellow; Nr <= '0'; Ng <= '1'; Ny <= '0';

Er <= '1'; Eg <= '0'; Ey <= '0'; WHEN red => Nr <= '1'; Ng <= '0'; Ny <= '0';

Er <= '0'; Eg <= '1'; Ey <= '0'; next_state <= green; WHEN yellow => next_state <= red; Nr <= '0'; Ng <= '0'; Ny <= '1';

Er <= '0'; Eg <= '0'; Ey <= '1'; IF (sensor_count = "0000") then next_state <= green; elsif (sensor_count = "0101") then next_state <= red; elsif (sensor_count = "1011") then next_state <= yellow;

END IF; END CASE; END PROCESS; PROCESS(clock,next_state) BEGIN if (clock'EVENT and clock = '1') then

present_state <= next_state; end if; END PROCESS; end Behavioral;

SIMULARE: