llibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.

all; entity PWM is ( CLK : D : PWM : ); end PWM; architecture Behavioral of PWM is signal signal signal signal tmp up_down Oup TC : : : : std_logic_vector( 3 downto 0 ); std_logic; std_logic; std_logic; port in std_logic; in std_logic_vector( 3 downto 0 ); out std_logic

begin process( CLK, TC, tmp ) begin if( CLK'event and CLK = '1' and TC = '0' ) then if( up_down = '1' ) then tmp <= tmp + 1; elsif( up_down = '0' ) then tmp <= tmp - 1; end if; elsif( TC'event and TC = '1' ) then tmp <= D; Oup <= not Oup; PWM <= Oup; up_down <= Oup; elsif( tmp'event and tmp = "1111" ) then TC <= '1'; elsif( tmp'event and tmp = "0000" ) then TC <= '1'; end if; end process; end Behavioral;