Barrel

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity barrel is
PORT(datain:in std_logic_vector(7 downto 0);
opcode:in std_logic_vector(2 downto 0);
count:in std_logic_vector(2 downto 0);
dataout:out std_logic_vector(7 downto 0)
);
end barrel;
architecture Behavioral of barrel is

begin
process(opcode,count)
begin
--takin count as case statement
case count is
--this case indicates there is no shift and rotate
when"000"=>
if opcode="000"then
dataout<=datain;
elsif opcode="001"then
dataout<=datain;
dataout<=datain;
dataout<=datain;
dataout<=datain;
dataout<=datain;
end if;
--this case indicates input data in shifted by 1 bit
when "001"=>
if opcode="000"then --shift right logical
dataout<="0"&datain( 7 downto 1);
elsif opcode="001"then --shift right arithmetic
dataout<=datain(7)& datain(7 downto 1);
elsif opcode="010"then --rotate right
dataout<=datain(0) & datain(7 downto 1);
elsif opcode="100"then --shift left logical
dataout<=datain(6 downto 0) &"0";
elsif opcode="101"then --shift left arithmetic
dataout<=datain(7)&datain(5 downto 0) &"0";
elsif opcode="110"then--rotate left
dataout<=datain(6 downto 0) & datain(7);
end if;
--this case indicate that input data is shifted by 2 bits
when "010"=>
if opcode="000"then
dataout<="00" & datain(7 downto 2);
dataout<=datain(7)&datain(7)&datain(7 downto 2);
dataout<=datain(1 downto 0)&datain(7 downto 2);
dataout<=datain(7)&datain(4 downto 0)&"00";
dataout<=datain(5 downto 0)&datain( 7 downto 6);
end if;
--this case indicates that data is shifted by 3 bits
when "011"=>
if opcode="000"then
dataout<="000" &datain( 7 downto 3);
dataout<=datain(7)&datain(7)&datain(7)&datain(7 downto 3);
dataout<=datain(2 downto 0) &datain( 7 downto 3);
dataout<=datain(7)&datain(3 downto 0)&"000";
dataout<=datain(4 downto 0 )&datain( 7 downto 5);
end if;
--this case indicates that input data is shifted by 4 bits
when "100"=>
if opcode="000"then
dataout<="0000" & datain(7 downto 4);
dataout<=datain(7)&datain(7)&datain(7)&datain(7)&datain(7 downto 4);
dataout<=datain(7)&datain(2 downto 0) & "0000";
dataout<=datain(3 downto 0)&datain( 7 downto 4);
end if;
when "101"=>
if opcode="000"then
dataout<="00000" &datain( 7 downto 5);
dataout<=datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7 downto 5);
dataout<=datain(4 downto 0) & datain(7 downto 5);
dataout<=datain(7)&datain(1 downto 0 )& "00000";
dataout<=datain(2 downto 0) & datain(7 downto 3);

end if;
when "110"=>
if opcode="000"then
dataout<="000000"&datain( 7 downto 6);
dataout<=datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7 downto 6);
dataout<=datain(7)&datain( 0) &"000000";
end if;
--this case indicates that the input data is shifted by 7 bits
when others=>
if opcode="000"then
dataout<="0000000" &datain(7);
dataout<=datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7);
dataout<=datain(6 downto 0)&datain(7);
dataout<=datain(0) &"0000000";
dataout<=datain(7)&"0000000";
dataout<=datain(0)&datain( 7 downto 1);
end if;
end case;
end process;
end Behavioral;
32 bit barrel shifter

--32BIT BARREL_SHIFTER
--BY SUMEET SAURAV
--COUNT:AMOUNT OF ROTATE/SHIFT REQUIRED

--I
:32 BIT INPUT DATA
--SHLR :4 BIT CONTROL SIGNAL

--Z
:32 BIT OUTPUT DATA
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BARREL_SHIFTER IS
PORT(
SHLR
:IN STD_LOGIC_VECTOR(3 downto 0);--SHLR(3) TO DECIDE WHETHER TO SHIFT LEFT OR
RIGHT
I
:IN STD_LOGIC_VECTOR(31 downto 0);
COUNT :IN STD_LOGIC_VECTOR(4 downto 0);

Z
:OUT STD_LOGIC_VECTOR(31 downto 0)
);
END BARREL_SHIFTER;
ARCHITECTURE ARCH OF BARREL_SHIFTER IS

SIGNAL S,H,L:STD_LOGIC;
SIGNAL F
:STD_LOGIC_VECTOR(1 downto 0);
SIGNAL D
SIGNAL B
SIGNAL P
SIGNAL X,A,Y
: STD_LOGIC_VECTOR(31 downto 0);--X IS BIT REVERSED OUTPUT
SIGNAL C,E,G : STD_LOGIC_VECTOR(31 downto 0);
COMPONENT MUX2_1 IS
PORT(
A,B :IN STD_LOGIC;
SEL :IN STD_LOGIC;
OUTPUT :OUT STD_LOGIC);
END COMPONENT;
BEGIN
--TO DECIDE WHETHER TO GET LEFT OR RIGHT OPERATION
-- RIGHT->0,LEFT->1 (A,B,SEL,OUT)
--IF SEL->0 THEN OUT->A SEL->1 THEN OUT->B
--BITREVERSAL OPERATION ON INPUT BITS
--SHLR(3)->0 RIGHT SHLR(3)->1 LEFT

M0:MUX2_1 PORT MAP(I(31),I(0),SHLR(3),X(31));


--TO DECIDE WHETHER ARITHMETIC OR LOGICAL

---SHLR(2)->0 LOGICAL SHLR(2)->1 ARITHMEATIC
MA:MUX2_1 PORT MAP('0',I(31),SHLR(2),S)
--SHLR(2) TO DECIDE WHETHER TO DO ARITHMETIC
OR LOGICAL
-- TO DECIDE WHETHER TO SHIFT/ROTATE BY 16 BITS

--SHLR(1)->0 SHIFT SHLR->1 ROTATE
Mr0:MUX2_1 PORT MAP(S,X(15),SHLR(1),P(15)); ---SHLR(1) TO DECIDE WHETHER TO SHIFT/ROTATE

Mr1:MUX2_1 PORT MAP(S,X(14),SHLR(1),P(14));

--STAGE 1
Ml0:MUX2_1 PORT MAP(X(31),P(15),COUNT(4),A(31));


Mr00:MUX2_1 PORT MAP(S,A(7),SHLR(1),B(7));

--STAGE 2
M20:MUX2_1 PORT MAP(A(31),B(7),SHFTAMT(3),C(31));

M28:MUX2_1 PORT MAP(A(23),A(31),SHFTAMT(3),C(23));

Mr20:MUX2_1 PORT MAP(S,C(3),SHLR(1),D(3));

--STAGE 3
M30:MUX2_1 PORT MAP(C(31),D(3),COUNT(2),E(31));

M34:MUX2_1 PORT MAP(C(27),C(31),COUNT(2),E(27));

MB21:MUX2_1 PORT MAP(C(10),C(14),COUNT(2),E(10));
Mr30:MUX2_1 PORT MAP(S,E(1),SHLR(1),F(1));

Mr31:MUX2_1 PORT MAP(S,E(0),SHLR(1),F(0));
--LAYER 4
M40:MUX2_1 PORT MAP(E(31),F(1),COUNT(1),G(31));

M41:MUX2_1 PORT MAP(E(30),F(0),COUNT(1),G(30));
M42:MUX2_1 PORT MAP(E(29),E(31),COUNT(1),G(29));

ME30:MUX2_1 PORT MAP(S,G(0),SHLR(1),H);
--STAGE 5
M50:MUX2_1 PORT MAP(G(31),H,COUNT(0),Y(31));
M51:MUX2_1 PORT MAP(G(30),G(31),COUNT(0),Y(30));


--FOR LEFT SHIFT ARITHMEATIC
--SHLR(0)->0 LOGICAL SHLR(1)->ARITHMETIC
MR0:MUX2_1 PORT MAP(Y(0),X(0),SHLR(0),L);
--BITREVERSAL OPERATION ON OUTPUT BITS
MS0:MUX2_1 PORT MAP(Y(31),Y(0),SHLR(2),Z(31));



MS31:MUX2_1 PORT MAP(L,Y(31),SHLR(0),Z(0));
END ARCH;

Barrel

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Barrel

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library IEEE;

architecture Behavioral of barrel is

dataout<=datain(2 downto 0) & datain(7 downto 3);

32 bit barrel shifter

--COUNT:AMOUNT OF ROTATE/SHIFT REQUIRED

:32 BIT INPUT DATA

--SHLR :4 BIT CONTROL SIGNAL

:32 BIT OUTPUT DATA

:IN STD_LOGIC_VECTOR(3 downto 0);--SHLR(3) TO DECIDE WHETHER TO SHIFT LEFT OR

:IN STD_LOGIC_VECTOR(31 downto 0);

COUNT :IN STD_LOGIC_VECTOR(4 downto 0);

:OUT STD_LOGIC_VECTOR(31 downto 0)

ARCHITECTURE ARCH OF BARREL_SHIFTER IS

:STD_LOGIC_VECTOR(1 downto 0);

:STD_LOGIC_VECTOR(3 downto 0);

:STD_LOGIC_VECTOR(7 downto 0);

:STD_LOGIC_VECTOR(15 downto 0);

: STD_LOGIC_VECTOR(31 downto 0);--X IS BIT REVERSED OUTPUT

SIGNAL C,E,G : STD_LOGIC_VECTOR(31 downto 0);

--SHLR(3)->0 RIGHT SHLR(3)->1 LEFT

M6:MUX2_1 PORT MAP(I(25),I(6),SHLR(3),X(25));

M29:MUX2_1 PORT MAP(I(2),I(29),SHLR(3),X(2));

--TO DECIDE WHETHER ARITHMETIC OR LOGICAL

--SHLR(2) TO DECIDE WHETHER TO DO ARITHMETIC

-- TO DECIDE WHETHER TO SHIFT/ROTATE BY 16 BITS

Mr0:MUX2_1 PORT MAP(S,X(15),SHLR(1),P(15)); ---SHLR(1) TO DECIDE WHETHER TO SHIFT/ROTATE

Mr11:MUX2_1 PORT MAP(S,X(4),SHLR(1),P(4));

Ml0:MUX2_1 PORT MAP(X(31),P(15),COUNT(4),A(31));

Ml14:MUX2_1 PORT MAP(X(17),P(1),COUNT(4),A(17));

-- TO DECIDE WHETHER TO SHIFT/ROTATE BY 8 BITS

Mr00:MUX2_1 PORT MAP(S,A(7),SHLR(1),B(7));

M20:MUX2_1 PORT MAP(A(31),B(7),SHFTAMT(3),C(31));

M211:MUX2_1 PORT MAP(A(20),A(28),SHFTAMT(3),C(20));

-- TO DECIDE WHETHER TO SHIFT/ROTATE BY 4 BITS

Mr20:MUX2_1 PORT MAP(S,C(3),SHLR(1),D(3));

M30:MUX2_1 PORT MAP(C(31),D(3),COUNT(2),E(31));

M313:MUX2_1 PORT MAP(C(18),C(22),COUNT(2),E(18));

-- TO DECIDE WHETHER TO SHIFT/ROTATE BY 2 BITS

Mr30:MUX2_1 PORT MAP(S,E(1),SHLR(1),F(1));

M40:MUX2_1 PORT MAP(E(31),F(1),COUNT(1),G(31));

M418:MUX2_1 PORT MAP(E(13),E(15),COUNT(1),G(13));

-- TO DECIDE WHETHER TO SHIFT/ROTATE BY 1 BITS

ME30:MUX2_1 PORT MAP(S,G(0),SHLR(1),H);

M50:MUX2_1 PORT MAP(G(31),H,COUNT(0),Y(31));

M51:MUX2_1 PORT MAP(G(30),G(31),COUNT(0),Y(30));

M524:MUX2_1 PORT MAP(G(7),G(8),COUNT(0),Y(7));

--FOR LEFT SHIFT ARITHMEATIC

--SHLR(0)->0 LOGICAL SHLR(1)->ARITHMETIC

MR0:MUX2_1 PORT MAP(Y(0),X(0),SHLR(0),L);

--BITREVERSAL OPERATION ON OUTPUT BITS

MS0:MUX2_1 PORT MAP(Y(31),Y(0),SHLR(2),Z(31));

MS6:MUX2_1 PORT MAP(Y(25),Y(6),SHLR(2),Z(25));

MS29:MUX2_1 PORT MAP(Y(2),Y(29),SHLR(2),Z(2));

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