ECE 110 M.-C.

Brunet

Logic Gates
TRUTH TABLES NOT SYMBOLS

George Boole (1854)

Book on logic theory (Boolean Algebra) . . . True & False Statements

X 0 1

NOT(X) 1 0

NOT(X)

OR, NOR

Boolean outputs Claude Shannon (1938)

Applied logic theory to relay circuits (switching theory) . . . High and Low Voltages

X 0 0 1 1

Y 0 1 0 1

OR NOR 1 0 0 1 0 1 0 1

X Y X Y

OR (X, Y) is 1 when X = 1 OR Y = 1
NOR (X, Y) )) NOT - OR

AND, NAND

switching outputs All variables are binary (0 or 1)

X 0 0 1 1

Y 0 1 0 1

AND NAND 1 0 1 0 1 0 0 1

X Y X Y

AND (X, Y) is 1 when X = 1 AND Y = 1

NAND (X, Y) )) NOT - AND

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One additional gate (very useful for transmission of data, and error detection, encryption, etc).
XOR Exclusive OR

N O T A T I O N S 1+1=?
NOT (X) = AND (X, Y) =

X 0 0 1 1

Y 0 1 0 1

XOR 0 1 1 *0

X Y

XOR (X,Y)

OR (X, Y) = XOR (X, Y) =

These notations will be used to provide Boolean expressions. 2 Truth Logic Circuits Tables 1 2

= 1 when X = 1, or Y = 1, but not both

(only difference versus OR)

and the corresponding complemented gate:

XNOR
X Y

NOT - XOR

X
XNOR (X,Y) 0

0 1 1
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Y 0 1 0 1

XNOR 1 0 0 1

Boolean Expressions Design, analyze circuits best circuits

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Example 1: One logic circuit

Inputs
X Y Z

Truth Table for F

X Y Z F
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

Any ideas on how to find the truth table?

F
Output

F(X, Y, Z) is a Boolean output (binary!) 1 Boolean expression for F: use notations! F(X, Y, Z) =

Other ways to draw the same circuit:

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Example 2:
X X Y Y G

Example 3:
X X Y Y H

Timing Diagrams
Inputs and output vary with time. Example here with G(X,Y) (in example 2) 2 inputs, 1 output : 1

3 graphs.

1 G(X,Y) =

Boolean Expression
H(X,Y) =

0 1 0 1 0

t
Y X

All graphs on one; and shift vertical variables! 1 0 1 0 1 0

Y ?G

?
Timing Diagram

t t
Remove axis

Truth Table
G X Y
0 0 1 1 0 1 0 1

X Y
0 0 1 1 0 1 0 1

X Y ?G
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Obtained from the Truth Table

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Compare G and H !!!

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Example 4:

Example 5:
X Y Z Y

AND_out

X Y Z X Y Z 1

AND_out =

Boolean Expression

I (X, Y, Z) =

OR_out

J (X, Y, Z) =

OR_out =

Truth Table (Split in two for convenience)

I J X Y Z
1 1 1 1
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X Y Z
0 0 0 0
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I J

0 0 1 1

0 1 0 1

0 0 1 1

0 1 0 1
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Designing Circuits from Truth Tables Example 6: X Y Z K

0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 1 0

Definitions A product term: an AND of input variables

Examples:

A minterm. For a Boolean output (for a given

number of inputs): Is a special product term in which all input variables appear once, complemented or not.

K (X, Y, Z) =

Example 8: All expressions below are product terms. Are they minterms? For function(X,Y,Z): XYZ? XY?
yes yes yes yes no no no no

Example 7: X Y Z L
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 0 1

For function(W,X,Y,Z): XYZ? WXYZ? For function(X,Y) give all minterms:

L (X, Y, Z) =
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Sum-Of-Product (SOP) Expressions:

An OR of product terms

Example 10:

Canonical SOP
M (X, Y, Z) = 1 1 1 1 0 0 0 1

X Y Z M
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

Canonical SOP for F:

An OR of minterms of F equal to 1 (= sum of minterms equal to 1)
Example 9: let us look at previous examples (Ex. 4) I = XYZ+XYZ (Ex. 5) J = XYZ+Y (Ex. 6) K = XYZ+XYZ (Ex. 7) L = XYZ+XYZ+XYZ One minterm of F equal to 1 corresponds to a particular input combination for which F is 1.

Circuit (C1):

Canonical SOP

AND-OR Circuit

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On the road to Boolean Algebra Identities

X X

Basic Boolean Algebra Identities

OR
X+0=X

F=

X X F
0 1 AND
X.1 = X X.0 = 0 X.X = X X.X = 0

Name of Identity
identity null idempotence complementary X involution commutative associative distributive DeMorgan absorption no name

Complementary:

X Involution: De Morgan
X Y

F=

X X F
0 1

X + 1= 1 X+X=X X + X = 1 X = X

X
X.Y = Y.X

X
G= 0 0 1 1

Y
0 1 0 1

X.Y G

X+Y=Y+X

X+(Y+ Z) = (X+Y)+Z X.(Y.Z) = (X.Y).Z X.(Y+Z) = X.Y + X.Z (X + Y) = X.Y NOR X + X.Y = X X+Y.Z = (X+Y).(X+Z) (X.Y) = X + Y NAND X.(X + Y) = X

X Y

X
H=

Y
0 1 0 1

0 0 1 1
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X + X.Y = X + Y

X.(X + Y) = X.Y

Careful! XY is not equal to XY

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Example 11: Using Boolean Identities prove that X Y Z + X Y Z + X Y Z is equal to X Y + X Y Z.

(note: the second expression yields a better circuit fewer gates and connections!)

Back to Example 7: Optimization? (SOPs only)

X Y Z L
0 0 0 0 1 1 1 1 L L 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 0 1

{This is the canonical SOP}

L (X, Y, Z) = XYZ + XYZ + XYZ

All expressions below are equal to L (for P=L, see ex. 11; others prove it!): P (X, Y, Z) = X Y + X Y Z Q (X, Y, Z) = X Y Z + Y Z R (X, Y, Z) = X Y + Y Z R

XYZ+XYZ+XYZ = = =

LOGIC CIRCUITS: P Q

Circuits # Gates # Connections # Levels L

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Back to Example 10: Optimization?

R (X, Y, Z) = X Y + Y Z

X Y Z M
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 1

1) Below is the optimal 2-level AND-OR circuit. Connect the inputs! X X Y Y Z Z Circuit (C2) M

2) Compare C2 to circuit C1 from the canonical SOP # Gates # Connections # Levels

C1 C2

21

Suggested practice: prove that the canonical SOP from circuit (C1) can be reduced to the SOP output of circuit (C2) using the Boolean Algebra Identities.
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NAND-NAND Circuits
Example 12: Give the Truth Table for I
X Y
X Y Z X Y Z I 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

De Morgans Identities Other way!

I
X Y Z X Y Z I

Z
0 1 0 1 0 1 0 1

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Example 13: Give a NAND circuit for J

Z J 1) 2-level NAND-NAND (complemented inputs are available) 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 2) 3-level NAND-NAND-NAND (no complemented inputs are available) X Y

X Y 0 0 0 0 0 1 0 1

Z 0 1 0 1

F 0 1 0 1

X Y 1 0 1 0 1 1 1 1

Z 0 1 0 1

F 1 0 0 0

1) Assume complemented inputs are available. use {AND,OR} gates to build a logic circuit for F (the optimal circuit has 3 gates). Assume complemented inputs are not available: 2) Use {NOT, AND, OR} gates 3) Use {NOT, OR} gates 4) Use {NAND} gates
2 Give the truth table for F & G

X Y X Z

X Y Z

3 Build a XOR gate using NAND gates only

(hint: write a SOP for the XOR)

X Y
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X + Y

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4 Connect the inputs for the optimal 2-level

SOLUTIONS:
1

circuits below: X Y 0 0 0 0 0 1 0 1 Z 0 1 0 1 H 1 0 0 0 K 0 1 1 1 X Y 1 0 1 0 1 1 1 1 Z 0 1 0 1 H 1 1 0 0 K 1 1 1 0

X X Y Y Z Z

1)
F = XZ + XYZ

2) F

X X Y Y Z Z H 3) Use 2) and make a AND gate using

OR and NOR: XY = X + Y i.e. X (outputs AND (X,Y) Y

X X Y Y Z Z K

4) From 2) For K, there are two different optimal solutions! F

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SOLUTIONS continued:
2

F = XY + XZ G = XY +Z

X 0 0 0 0

Y 0 0 1 1

Z 0 1 0 1

F 0 1 0 1

G 1 0 1 0

X 1 1 1 1

Y 0 0 1 1

Z 0 1 0 1

F 0 0 1 1

G 1 0 1 1

X + Y = XY + XY X X+ Y Y

Circuits correspond to the following SOPs: H = YZ + XY K = XY + YZ + XZ (2 optimal SOPs) = XZ + YZ + XY

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