Advanced FinFET Process Technology for Low Vth Tuning and Variation Reduction

National Institute of Advanced Industrial Science and Technology
Advanced FinFET Process Technology

M. Masahara National Institute of AIST
1
Contents
1. Introduction Merits and Issues of FinFET
2. Advanced FinFET Process Technology Vth Tuning Vth Variation
3. Summary
Multi-Gate FinFETs
D G S
FinFET
1st FinFET Patent in 1980 from AIST
Proposed by AIST in 1980 (named FinFET by UCB in 1999) Ultrathin and undoped channel and self-aligned double gate Extremely high short channel effect (SCE) immunity
3
DIBL Benchmark
FinFETs show the smallest DIBL (=highest SCE immunity)

4
Issues for Advanced FinFET

However, several technological issues still exist Fin Formation Vth Tuning Variation
D G
Stress Eng. (110) Channel
Low Resistive Source/Drain
S
Cpara Compact Model
SOI or Bulk I/O, ESD

5
Contents
3. Summary
Vth for FinFETs

VthDG(NMOS), -VthDG(PMOS) (V) 0.8 0.6
0.4 0.4V(LSTP) 0.2 0.2V(LOP) 0 -0.2 4 4.2 4.6eV 4.4 4.6 4.8 5 5.2 4.75eV 4.9eV Gate Workfunction (eV) 5.4
n+-Si (4.17eV)
p+-Si (5.25eV) AIST, IEEE TED 2007
Vth has a linear relationship with Gate Workfunction For low Vth, dual metal gate (dual WF) is needed
7
Id-Vg for Poly- and TiN-Gate FinFET

Drain Current, I d [ A ]
Drain Current, I d [ A ]
10 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10
-3
n+ poly-Si gate
PMOS |Vd | = 1 V 0.05 V NMOS
10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10
TiN-gate
PMOS |Vd | = 1 V 0.05 V NMOS
Weff =17 m -12
Lg = 21 m Weff =7.5 m
-1.5 -1 -0.5 0 0.5 1 1.5
g 10-11 Weff =17 m Weff =7.5 m -12 10 -1.5 -1 -0.5 0 0.5 1 1.5
L = 21 m
Gate Voltage, V g [ V ]
Asymmetric Vth
Gate Voltage, V g [ V ]
Symmetric Vth
Almost symmetrical Vths (normally off) are obtained thanks to the midgap work function of TiN (4.75 eV)
Dual Metal Gate Integration

Integration of TiN and TaCN gate FinFETs
General approach:
Deposition and etching

Etching residue
TiN nMOS TaCN pMOS
This work :
Metal Inter-diffusion
For PMOS Mo(4.95 eV) For NMOS Ta(4.25 eV)/Mo stack Ta Inter-diffusion in Mo
(No metal etching)
Ref. M.M.Hussain et al., ESSDERC2007, p.207
Ta diffusion in Mo
Back-side SIMS
Ta layer
Ta ion count [arb. unit] 100
Mo layer
SiO2
10
-1
Ta diffusion
O2+
10
-2
As depo.
Annealed (700oC 1 h)
10-3 0
10 Depth [nm]
15
Ta diffuses in Mo and piles-up at Mo/SiO2 interface after annealing Thus WF for NMOS is determined by Ta (4.25eV)
10
Features of Dual MG FinFETs

SiO2 HM etchback in nMOS region Ta and SiO2 HM etchback in pMOS region Patterning of Mo and Ta/Mo gates
No metal residue
11
I-V for Mo and Ta/Mo FinFETs

PMOS NMOS
Mo (high WF) Ta (low WF)
Mo (high WF)
low gate WF by Ta diffusion
AIST, IEEE EDL 2008
For NMOS, low Vth can be achieved by Ta diffusion in Mo For PMOS, low Vth can be achieved by Mo Off leakage Negligible
12
Four-Terminal FinFET
4T-FinFET = Independent DG FinFET
D G S
DG separation
Drive gate G1 S
D G2
Vth control gate
log Id
log Id
Ion
+Vg2 Ion -Vg2
Ioff
Ioff VthDG Vg1 Vth(G1) Vg1
Vth for FinFET can be controlled flexibly and individually by separating the DG
13
DG Separation
CMP Process
G D G1 S CMP S CMP Stopper D G2
Image after CMP
FinFET Formation
DG Separation by CMP
Local Etch-back Process

Stopper Fin Resist Gate
Image after LEB

Gate1
Fin Top
BOX sub FinFET Formation and Lithography DG Separation by LEB
Gate2 Side Wall 100nm Source Drain
14
Vth Tuning by Controlling Vg2

D G1 S G2
& & & & Tsi = Tsi = Tsi = Tsi = 8.5-nm, 13-nm, 23-nm, 43-nm, = = = = 0.79 0.66 0.42 0.24
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2
350 300 250 200 150 100 50 0
-1.2 -1 -0.8 -0.6 -0.4 -0.2 0
Vg2 [ V ]
Vth can be tuned from LSTP to HP flexibly by selecting a proper Vg2 (The Second Gate)
S-Slope [ mV/decade ]
15
Vth [ V ]
Contents
3. Summary
16
Vth Variation for MG FinFETs

(2) (1) (4)
Possible Vth Variation Sources

(1) Gate Length (Lg)
G S
(3)
D
(5)
(2) Fin Thickness (TSi) (3) Oxide Thickness (Tox) (4) RDF (5) Work Function WFV (m)
FinFET variability sources were systematically analyzed

17
Main Cause of Vth Variation

Measured Vth LG Source T Fin Source Tox Source m Source
LG=6.7 nm (measured) TFin =2.9 nm (measured) Tox=0.032 nm (measured) LG= 100 nm T Fin = 40 nm <Vth >= 0.42 V
Dimension Variation sources
Negligible
Main Cause
0 5 10 15 20 25 30 35 Vth [mV] AIST, IEEE EDL 2010
Dimension variation sources are negligible Main cause of the Vth variation is the Workfunction Variation
18
Workfunction Variation
RIE
S G D 2-Metal Si SiO2 1-Metal
Ideal
SiO2 Si 1-Metal
Randomly aligned Metal Higher WF variation
Uniformly aligned Metal Lower WF variation
Rough etched side wall causes randomly aligned metal grain and thus higher WF variation If side wall is flat, uniformly aligned metal grain and thus lower WF variation can be expected
19
Nano-Wet Etching Process

5000
Etching Depth [ nm ]
4000 3000 2000 1000 0
2.38% TMAH 50oC

(110)
/m in nm
Etchant 2.38% TMAH (Resist Developer) (Tetramethylammonium hydroxide)

CH3
+
CH3 OH
35 9
4 21
nm
n (100) i /m
CH3 N CH3
<110> <111>
15
9 nm/min (111)
0 5 10
Etching time [ min ]
fin-mask TMAH
SOI BOX
Si-fin
AIST, IEDM 2006

20
Extremely low ER of (111) in TMAH Flat (111) side wall
SEM and STEM images of FinFET

20 nm Gate Tox Source Drain Hfin = 45 nm
AIST, VLSI Symp. 2010
Si-fin
TSi = 12 nm
Min.Lg = 20 nm, TSi = 17.8 nm, HSi = 45 nm Nano-Wet-Etched FinFET Undoped channel Tox(CET) = 2.3 nm by C-V Gate Stack : PVD-TiN/SiO2
21
Measured Vth for Nano-Wet-Etched FinFET

AIST, VLSI Symp. 2010
40 35 30 Vth [ mV ] 25 20 15 10 5 0 0
PVD-TiN Gate CET = 2. 3 nm
5 10 15 20 1/2 -1 1/(WL) [ mm ]
25
AVt was significantly lowered by flattening the side channel

22
Avt Benchmark
4 Avt =Vt(LW)1/2 [mV-um] Bulk-planar FDSOI FinFET
4
3
List of reported AVt values

Ref. # 1 2 Device Structure FDSOI FDSOI FDSOI (SOTB) Bulk-planar Bulk-planar Bulk-planar Bulk-planar Bulk-planar FinFET Bulk-planar Bulk-planar Bulk-planar FDSOI FinFET FinFET Gate Stack Author. Poly/SiO2 TiN/HfO2 NiSi/ Poly/SiON MG/HK MG/HK s-Si/SiON HK/MG Mo/SiO2 MG/HK MG/HK MG/HK MG/HK TiN/HfSiO TiN/SiO2 A.Cathignol C. FenouilletST Beranger Y.Morita T.Tsunomura F.Arnaud S.Hasegawa H.Fukutome M.Goto T.Matsukawa F.Arnaud L.A.Ragnarsso n L.A.Ragnarsso n K.Cheng T.Chiarella Y.Liu OrganiReference zation ST ESSDERC2006 IEDM2007 VLSI2008 VLSI2008 IEDM2008 IEDM2008 IEDM2009 VLSI2009 VLSI2009 IEDM2009 IEDM2009 IEDM2009 IEDM2009 ESSDERC2009 VLSI2010
Hitachi Selete ST Toshiba Fujitsu Toshiba AIST ST IMEC IMEC IBM IMEC AIST
3
7 12 5 6 11 8 10 14 13 LSTP15nm 3 2 15 1 9 LSTP22nm
4 5 6 7 8 9 10 11 12 13 14 15
2 Tox [nm]
T. Matsukawa, et al., (AIST.) SOI Conf, 2011, 7.1.
Obtained Avt meets 22-nm-node SRAM requirement For 15nm and beyond, Avt should be further reduced
23
Contents
3. Summary
24
Summary
By introducing Ta/Mo dual metal gate technology, low Vth (0.2V) can be obtained for CMOS FinFETs. By separating the DG, Vth can be tuned from 0.2V to 0.4V flexibly. Flattening of Si-fin sidewall channel is very promising for reducing Vth variations.
This work was supported in part by NEDO
25

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