DMEM library ieee; use ieee.std_logic_1164.all; use std.textio.all; use work.txt_util.

all; entity Memory is port (clk : in std_logic; reset : in std_logic; WriteData : in std_logic_vector(31 downto 0); Address : in std_logic_vector(31 downto 0); MemWrite : in std_logic; MemRead : in std_logic; ReadData : out std_logic_vector(31 downto 0)); end Memory; architecture rtl of Memory is signal data : std_logic_vector(31 downto 0); signal nwe, noe, ncs : std_logic; begin -- Data Memory memory: entity work.sram64kx8(sram_behaviour) port map (ncs, Address, data, nwe, noe); nwe <= not MemWrite; noe <= not MemRead; ncs <= not (MemWrite or MemRead) or (not reset); -- connect data to reg out 2 with a tristate buffer GEN_memtris: for n in 31 downto 0 generate data(n) <= WriteData(n) when MemWrite='1' else 'Z'; end generate GEN_memtris; ReadData <= data; end rtl; VHDL register library ieee; use ieee.std_logic_1164.all; use work.all; entity registerfile is port ( clock4: in std_logic; registerNumber: in std_logic_vector(1 downto 0); Read_registerNumber1: in std_logic_vector(1 downto 0); Read_registerNumber2: in std_logic_vector(1 downto 0); DataIn: in std_logic_vector(3 downto 0); DataOut_A: out std_logic_vector(3 downto 0); DataOut_B: out std_logic_vector(3 downto 0) ); end registerfile; architecture struct of registerfile is component dff is port ( clock: in std_logic; D: in std_logic; Q: out std_logic

); end component; component decoder is port ( I: in std_logic_vector(1 downto 0); O: out std_logic_vector(3 downto 0) ); end component; component AND1 is port ( x: in std_logic; y: in std_logic; F: out std_logic ); end component; component multiplexor4 is port ( I3: in std_logic_vector(3 downto 0); I2: in std_logic_vector(3 downto 0); I1: in std_logic_vector(3 downto 0); I0: in std_logic_vector(3 downto 0); S: in std_logic_vector(1 downto 0); O: out std_logic_vector(3 downto 0) ); end component; signal ss1: std_logic; signal ss2: std_logic; signal ss3: std_logic; signal ss4: std_logic; signal ss: std_logic_vector(3 downto 0); 7 signal DataOut1: std_logic_vector(3 downto 0); signal DataOut2: std_logic_vector(3 downto 0); signal DataOut3: std_logic_vector(3 downto 0); signal DataOut4: std_logic_vector(3 downto 0); begin decoder1: decoder port map ( I(0) => registerNumber(0), I(1) => registerNumber(1), O(0)=>ss1, O(1)=>ss2,O(2)=>ss3, O(3)=>ss4); And_1: AND1 port map ( X=>clock4,Y=>ss1,F=>ss(0)); And_2: AND1 port map ( X=>clock4,Y=>ss2,F=>ss(1)); And_3: AND1 port map ( X=>clock4,Y=>ss3,F=>ss(2)); And_4: AND1 port map ( X=>clock4,Y=>ss4,F=>ss(3)); D1: dff port map (clock => ss(0), D =>DataIn(0), Q=>DataOut1(0)); D2: dff port map (clock => ss(0), D=>DataIn(1), Q=>DataOut1(1)); D3: dff port map (clock=>ss(0), D=>DataIn(2), Q=>DataOut1(2)); D4: dff port map (clock=>ss(0), D=>DataIn(3), Q=>DataOut1(3)); D5: dff port map (clock => ss(1), D =>DataIn(0), Q=>DataOut2(0)); D6: dff port map (clock => ss(1), D=>DataIn(1), Q=>DataOut2(1)); D7: dff port map (clock=>ss(1), D=>DataIn(2), Q=>DataOut2(2)); D8: dff port map (clock=>ss(1), D=>DataIn(3), Q=>DataOut2(3)); D9: dff port map (clock => ss(2), D =>DataIn(0), Q=>DataOut3(0)); D10: dff port map

(clock => ss(2), D=>DataIn(1), Q=>DataOut3(1)); D11: dff port map (clock=>ss(2), D=>DataIn(2), Q=>DataOut3(2)); D12: dff port map (clock=>ss(2), D=>DataIn(3), Q=>DataOut3(3)); D13: dff port map (clock => ss(3), D =>DataIn(0), Q=>DataOut4(0)); D14: dff port map (clock => ss(3), D=>DataIn(1), Q=>DataOut4(1)); D15: dff port map (clock=>ss(3), D=>DataIn(2), Q=>DataOut4(2)); D16: dff port map (clock=>ss(3), D=>DataIn(3), Q=>DataOut4(3)); mux1: multiplexor4 port map (S(0)=>Read_registerNumber1(0), S(1)=>Read_registerNumber1(1), I0(0)=> DataOut1(0),I0(1)=>DataOut1(1),I0(2)=>DataOut1(2),I0(3)=>DataOut1(3), I1(0)=>DataOut2(0),I1(1)=>DataOut2(1),I1(2)=>DataOut2(2), 8 I1(3)=>DataOut2(3), I2(0)=>DataOut3(0),I2(1)=>DataOut3(1),I2(2)=>DataOut3(2), I2(3)=>DataOut3(3), I3(0)=>DataOut4(0),I3(1)=>DataOut4(1),I3(2)=>DataOut4(2), I3(3)=>DataOut4(3), O(0)=>DataOut_A(0),O(1)=>DataOut_A(1), O(2)=>DataOut_A(2), O(3)=>DataOut_A(3)); mux2: multiplexor4 port map (S(0)=>Read_registerNumber2(0), S(1)=>Read_registerNumber2(1), I0(0)=> DataOut1(0),I0(1)=>DataOut1(1),I0(2)=>DataOut1(2),I0(3)=>DataOut1(3), I1(0)=>DataOut2(0),I1(1)=>DataOut2(1),I1(2)=>DataOut2(2), I1(3)=>DataOut2(3), I2(0)=>DataOut3(0),I2(1)=>DataOut3(1),I2(2)=>DataOut3(2), I2(3)=>DataOut3(3), I3(0)=>DataOut4(0),I3(1)=>DataOut4(1),I3(2)=>DataOut4(2), I3(3)=>DataOut4(3), O(0)=>DataOut_B(0),O(1)=>DataOut_B(1), O(2)=>DataOut_B(2), O(3)=>DataOut_B(3)); end struct; Description: Implements a counter that points to instruction memory -- fetching a new instruction on every cycle. Supports branching and synchronous reset --------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_unsigned.all; use std.textio.all; library mmix; use mmix.opcode.all; use mmix.pipeline_ports.all; entity Fetch is port( en : in std_logic; reset : in std_logic; clk : in std_logic; branch : branch; output : out fetch_decode); end Fetch; architecture Behavioural of Fetch is

type rom_type is array (0 to 255) constant rom : rom_type := ( MMIX_SETL & X"00" & X"00" MMIX_SETL & X"01" & X"00" MMIX_SETL & X"02" & X"00" MMIX_SETL & X"03" & X"00" MMIX_STBI & X"00" & X"FF" MMIX_STBI & X"01" & X"FF" MMIX_STBI & X"02" & X"FF" MMIX_STBI & X"02" & X"FF" MMIX_STBI & X"03" & X"FF" others => X"00000000");

of std_logic_vector(31 downto 0); & & & & & & & & & X"48", X"45", X"4C", X"4F", X"00", X"01", X"02", X"03", X"04",

signal PC : std_logic_vector(63 downto 0) := (others => '0'); begin increment_process: process(clk) begin if rising_edge(clk) then if reset = '1' then PC <= (others => '0'); elsif en = '1' then if branch.en = '1' then PC <= branch.addr; else PC <= std_logic_vector(unsigned(PC) + 1) ; end if; end if; end if; end process; output.IR <= rom(to_integer(resize(unsigned(PC), 8))); output.NPC <= std_logic_vector(unsigned(PC) + 1); end Behavioural; ---------------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY SCOMP IS PORT( clock, reset : IN STD_LOGIC; program_counter_out : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ); register_AC_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0 ); memory_data_register_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0 )); END SCOMP; ARCHITECTURE a OF scomp IS TYPE STATE_TYPE IS ( reset_pc, fetch, decode, execute_add, execute_load, execute _store, execute_store3, execute_store2, execute_jump ); SIGNAL state: STATE_TYPE;

SIGNAL instruction_register, memory_data_register : STD_LOGIC_VECTOR(15 DOWNTO 0 ); SIGNAL register_AC : STD_LOGIC_VECTOR(15 DOWNTO 0 ); SIGNAL program_counter : STD_LOGIC_VECTOR( 7 DOWNTO 0 ); SIGNAL memory_address_register : STD_LOGIC_VECTOR( 7 DOWNTO 0 ); SIGNAL memory_write : STD_LOGIC; BEGIN -- Use LPM function for computer's memory (256 16-bit words) memory: lpm_ram_dq GENERIC MAP ( lpm_widthad => 8, lpm_outdata => "UNREGISTERED", lpm_indata => "REGISTERED", lpm_address_control => "UNREGISTERED", -- Reads in mif file for initial program and data values lpm_file => "program.mif", lpm_width => 16 ) PORT MAP ( data => Register_AC, address => memory_address_register, we => memory_write, inclock => clock, q => memory_data_register ); program_counter_out <= program_counter; register_AC_out <= register_AC; memory_data_register_out <= memory_data_register; PROCESS ( CLOCK, RESET ) BEGIN IF reset = '1' THEN state <= reset_pc; ELSIF clock'EVENT AND clock = '1' THEN CASE state IS -- reset the computer, need to clear some registers WHEN reset_pc => program_counter <= "00000000"; memory_address_register <= "00000000"; register_AC <= "0000000000000000"; memory_write <= '0'; state <= fetch; -- Fetch instruction from memory and add 1 to PC WHEN fetch => instruction_register <= memory_data_register; program_counter <= program_counter + 1; memory_write <= '0'; state <= decode; -- Decode instruction and send out address of any data operands WHEN decode => memory_address_register <= instruction_register( 7 DOWNTO 0); CASE instruction_register( 15 DOWNTO 8 ) IS WHEN "00000000" => state <= execute_add; WHEN "00000001" => state <= execute_store; WHEN "00000010" => state <= execute_load; WHEN "00000011" => state <= execute_jump; WHEN OTHERS => state <= fetch; END CASE; -- Execute the ADD instruction WHEN execute_add => register_ac <= register_ac + memory_data_register; memory_address_register <= program_counter; state <= fetch;

-- Execute the STORE instruction -- (needs three clock cycles for memory write) WHEN execute_store => -- write register_A to memory memory_write <= '1'; state <= execute_store2; -- This state ensures that the memory address is -- valid until after memory_write goes inactive WHEN execute_store2 => memory_write <= '0'; state <= execute_store3; WHEN execute_store3 => memory_address_register <= program_counter; state <= fetch; -- Execute the LOAD instruction WHEN execute_load => register_ac <= memory_data_register; memory_address_register <= program_counter; state <= fetch; -- Execute the JUMP instruction WHEN execute_jump => memory_address_register <= instruction_register( 7 DOWNTO 0 ); program_counter <= instruction_register( 7 DOWNTO 0 ); state <= fetch; WHEN OTHERS => memory_address_register <= program_counter; state <= fetch; END CASE; END IF; END PROCESS; END a; -----------------------------------------------------------------------------------------------------------SIMPLE ALU library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity simple_alu is port( Clk : in std_logic; --clock signal A,B : in signed(7 downto 0); --input operands Op : in unsigned(2 downto 0); --Operation to be performed R : out signed(7 downto 0) --output of ALU ); end simple_alu; architecture Behavioral of simple_alu is --temporary signal declaration. signal Reg1,Reg2,Reg3 : signed(7 downto 0) := (others => '0'); begin Reg1 <= A; Reg2 <= B; R <= Reg3; process(Clk)

begin if(rising_edge(Clk)) then --Do the calculation at the positive edge of clock cycle. case Op is when "000" => Reg3 <= Reg1 + Reg2; --addition when "001" => Reg3 <= Reg1 - Reg2; --subtraction when "010" => Reg3 <= not Reg1; --NOT gate when "011" => Reg3 <= Reg1 nand Reg2; --NAND gate when "100" => Reg3 <= Reg1 nor Reg2; --NOR gate when "101" => Reg3 <= Reg1 and Reg2; --AND gate when "110" => Reg3 <= Reg1 or Reg2; --OR gate when "111" => Reg3 <= Reg1 xor Reg2; --XOR gate when others => NULL; end case; end if; end process; --------------------------------------------------------------------ALU library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity ALU_VHDL is port ( Nibble1, Nibble2 : in std_logic_vector(3 downto 0); Operation : in std_logic_vector(2 downto 0); Carry_Out : out std_logic; Flag : out std_logic; Result : out std_logic_vector(3 downto 0) ); end entity ALU_VHDL; architecture Behavioral of ALU_VHDL is signal Temp: std_logic_vector(4 downto 0); begin process(Nibble1, Nibble2, Operation, temp) is begin Flag <= '0'; case Operation is when "000" => -- res = nib1 + nib2, flag = carry = overflow Temp <= std_logic_vector((unsigned("0" & Nibble1) + unsigned(Nibbl e2))); Result <= temp(3 downto 0);

Flag <= temp(4); when "001" => -- res = |nib1 - nib2|, flag = 1 iff nib2 > nib1 if (Nibble1 >= Nibble2) then Result <= std_logic_vector(unsigned(Nibble1) - unsigned(Nibble2)) ; Flag <= '0'; else Result <= std_logic_vector(unsigned(Nibble2) - unsigned(Nibble1)) ; Flag <= '1'; end if; when "010" => Result <= Nibble1 and Nibble2; when "011" => Result <= Nibble1 or Nibble2; when "100" => Result <= Nibble1 xor Nibble2; when "101" => Result <= not Nibble1; when "110" => Result <= not Nibble2; when others => -- res = nib1 + nib2 + 1, flag = 0 Temp <= std_logic_vector((unsigned("0" & Nibble1) + unsigned(not N ibble2)) + 1); Result <= temp(3 downto 0); Flag <= temp(4); end case; end process; end architecture Behavioral; --------------------------------------------------------------------------------8 bit mux library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity mux8to1 is port (X: in std_logic_vector(7 downto 0); S: in std_logic_vector(2 downto 0); F: out std_logic); end mux8to1; architecture RTL of mux8to1 is begin with S select F <= X(0) when "000", X(1) when "001", X(2) when "010", X(3) when "011", X(4) when "100", X(5) when "101", X(6) when "110", X(7) when "111", 'X' when others; end RTL; --------------------------------------------------------------------------------

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