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TEM PROIECT Nr.33 S se proiecteze un decodificator din codul BCD ponderat 5421 / zecimal (logic combinaional).

Proiectarea se va referi la o singur decad.Proiectul va cuprinde urmtoa-rele puncte: a) S se exprime funciile logice asociate circuitului combinaional cu FCD (forma canonic disjunctiv), FCC (forma canonic conjunctiv), tabel de adevr i diagrame Karnaugh. b) S se obin formele minime disjunctive i conjunctive pentru funciile logice asociate decodificatorului BCD 5421 / zecimal (utiliznd combinaiile indiferente) prin metoda diagramelor Karnaugh; se vor obine, de asemenea, formele minime disjunctive pentru dou dintre funciile logice de ieire f5,f7 i prin metoda Quine-McCluskey. c) S se implementeze fiecare funcie logic, independent, numai cu pori logice I-NU (porile logice sunt realizate n tehnologia TTL). d) S se implementeze ansamblul funciilor logice numai cu pori logice I-NU (porile logice sunt realizate n tehnologia TTL). e) S se implementeze ansamblul funciilor logice n urmtoarea variant: primele 5 funcii logice de ieire cu pori logice I-NU, realizate n tehnologia TTL, iar urmtoarele 5 cu pori logice SAU-NU, realizate n tehnologia CMOS. f) S se implementeze ansamblul funciilor logice cu MUX-uri de 8 respectiv 16 ci (circuitele sunt realizate n tehnologia TTL). g) S se implementeze ansamblul funciilor logice cu DMUX-uri de 8 respectiv 16 ci i pori logice I-NU n prima variant, respectiv I n a doua variant (toate circuitele sunt realizate n tehnologia CMOS). h) S se calculeze timpii de propagare intrare-ieire, pentru toate schemele logice obinute. i) S se calculeze puterile disipate pentru toate schemele logice obinute. j) S se compare soluiile de implementare obinute. k) Se va face analiza, prin simulare, a tuturor schemelor logice obinute utilizndu-se pachetul de programe OrCAD.

Pe schemele logice obinute se vor specifica tipul i gradul de utilizare al fiecrui circuit integrat. Pentru a putea scrie o functie sub una din formele ei canonice, trebuie cunoscut tabelul de adevar unde se trec toate combinatiile liniare ale variabilelor de intrare, adica 24 = 16 combinatii. Tabel de adevar: Cifra Zecimala 0 1 2 3 4 8 9 10 11 12 Codul 5421 X2 X3 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 Zecimal f4 f5 f6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0

X1 0 0 0 0 0 1 1 1 1 1

X4 0 1 0 1 0 0 1 0 1 0

f0 1 0 0 0 0 0 0 0 0 0

f1 0 1 0 0 0 0 0 0 0 0

f2 0 0 1 0 0 0 0 0 0 0

f3 0 0 0 1 0 0 0 0 0 0

f7 0 0 0 0 0 0 0 1 0 0

f8 0 0 0 0 0 0 0 0 1 0

F9 0 0 0 0 0 0 0 0 0 1

a) Pentru a obtine din tabelul de adevar FCC (forma canonica conjunctiva) se iau in considerare combinatiile pentru care o functie are valoarea 0, iar pentru FCD (forma canonica disjunctiva) se iau in considerare combinatiile pentru care functia are valoarea 1. f0FCD = P0 = (0) = x1 x2 x3 x4 f0FCC = S1*S2*S3*S4*S8*S9*S10*S11*S12 = (1, 2, 3, 4, 8, 9, 10, 11, 12) = = ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x 3 + x4 ) ( x1 + x2 + x 3 + x 4 )
( x1 + x 2 + x3 + x4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x 3 + x4 )

( x1 + x2 + x 3 + x 4 ) ( x1 + x 2 + x3 + x4 )

f1FCD = P1 = (1) = x1 x2 x3 x4 f1FCC = S0*S2*S3*S4*S8*S9*S10*S11*S12 = (0, 2, 3, 5, 8, 9, 10, 11, 12) = = ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x 3 + x4 ) ( x1 + x2 + x 3 + x 4 )


( x1 + x 2 + x3 + x4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x 3 + x4 )

( x1 + x2 + x 3 + x 4 ) ( x1 + x 2 + x3 + x4 )

f2FCD = P2 = (2) = x1 x2 x3 x4 f2FCC = S0*S1*S3*S4*S8*S9*S10*S11*S12 = (0, 1, 3, 4, 8, 9, 10, 11, 12) = = ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x 3 + x 4 ) ( x1 + x 2 + x3 + x4 )

( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x 3 + x4 ) ( x1 + x2 + x 3 + x 4 ) ( x1 + x 2 + x3 + x4 )

f3FCD = P3 = (3) = x1 x2 x3 x4 f3FCC = S0*S1*S2*S4*S8*S9*S10*S11*S12 = (0, 1, 2, 4, 8, 9, 10, 11, 12) = = ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x 2 + x3 + x4 )


( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x 3 + x4 ) ( x1 + x2 + x 3 + x 4 ) ( x1 + x 2 + x3 + x4 )

f4FCD = P4 = (4) = x1 x2 x 3 x4 f4FCC = S0*S1*S2*S3*S8*S9*S10*S11*S12 = (0, 1, 2, 3, 8, 9, 10, 11, 12) = = ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x 3 + x 4 )


( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x 3 + x4 ) ( x1 + x2 + x 3 + x 4 ) ( x1 + x 2 + x3 + x4 )

f5FCD = P8 = (8) = x1 x2 x3 x 4 f5FCC = S0*S1*S2*S3*S4*S9*S10*S11*S12 = (0, 1, 2, 3, 4, 9, 10, 11, 12) = = ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x 3 + x 4 )


( x1 + x 2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x 3 + x4 ) ( x1 + x2 + x 3 + x 4 ) ( x1 + x 2 + x3 + x4 )

f6FCD = P9 = (9) = x1 x 2 x 3 x 4 f6FCC = S0*S1*S2*S3*S4*S8*S10*S11*S12 = (0, 1, 2, 3, 4, 8, 10, 11, 12) = = ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x 3 + x 4 )


( x1 + x 2 + x3 + x4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x 3 + x4 ) ( x1 + x2 + x 3 + x 4 ) ( x1 + x 2 + x3 + x4 )

f7FCD = P10= (10) = x1 x 2 x3 x 4 f7FCC = S0*S1*S2*S3*S4*S8*S9*S11*S12 = (0, 1, 2, 3, 4, 8, 9, 11, 12) = = ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x 3 + x 4 )


( x1 + x 2 + x3 + x4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x 3 + x 4 ) ( x1 + x 2 + x3 + x4 )

f8FCD = P11 = (11) = x1 x 2 x3 x4 f8FCC = S0*S1*S2*S3*S4*S8*S9*S10*S12 = (0, 1, 2, 3, 4, 8, 9, 10, 12) = = ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x 3 + x 4 )


( x1 + x 2 + x3 + x4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x 3 + x4 ) ( x1 + x 2 + x3 + x4 )

f9FCD = P12 = (12) = x1 x2 x 3 x 4 f9FCC = S0*S1*S2*S3*S4*S8*S9*S10*S11 = (0,1, 2, 3, 4, 8, 9, 10, 11) = = ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x 3 + x 4 )


( x1 + x 2 + x3 + x4 ) ( x1 + x2 + x3 + x4 ) ( x1 + x2 + x3 + x 4 ) ( x1 + x2 + x 3 + x4 )

( x1 + x2 + x 3 + x 4 )

b) Metoda diagramelor K este o metod grafo-analitic foarte util la minimizarea funciilor cu un numr relativ mic de variabile. Metoda pornete de la una din formele canonice ale funciei. Diagramele Karnaugh se prezint sub forma unui patrat (sau dreptunghi) cu 2 n locaii, n cazul nostru cu 16 locaii.n fiecare locaie va aprea un termen canonic al funciei. Diagrama este astfel organizat, nct dou componente vecine pe linie sau pe coloan, s difere printr-o aceeai variabil, variabil care ntr-o combinaie s apar negat, i n alta adevrat (proprietatea de adiacen). Formele minime disjunctive (FMD) prin diagrame Karnaugh: f0FMD =
x1 x2 x3 x4

f1FMD = 01 0 * * * 11 0 * * * 10 0 0 0 0

x1 x3 x4

x1, x2 x3, x4 00 01 11 10

00 1 0 0 0

x1, x2 x3, x4 00 01 11 10 f2FMD = x1 x3 x4 x1, x2 00 x3, x4 00 0 01 0 11 0 10 1 f4FMD = x1 x2 f3FMD = 01 0 * * * 11 0 * * * 10 0 0 0 0 x1, x2 x3, x4 00 01 11 10

00 0 1 0 0

01 0 * * *

11 0 * * *

10 0 0 0 0

x1 x3 x4

00 0 0 1 0

01 0 * * *

11 0 * * *

10 0 0 0 0

f5FMD =

x1 x2 x3 x4

x1, x2 x3, x4 00 01 11 10 x1, x2 x3, x4 00 01 11 10 00 0 0 0 0 01 1 * * * 11 0 * * * 10 0 0 0 0 f7FMD = 01 0 * * * 11 0 * * * 10 0 1 0 0 x1, x2 x3, x4 00 01 11 10

00 0 0 0 0

01 0 * * *

11 0 * * *

10 1 0 0 0

f6FMD = x1 x3 x4 x1, x2 00 x3, x4 00 0 01 0 11 0 10 0 f8FMD = x1 x3 x4 x1, x2 00 x3, x4 00 0 01 0 11 0 10 0

x1 x3 x4

00 0 0 0 0

01 0 * * *

11 0 * * *

10 0 0 0 1

f9FMD = x1 x2 01 0 * * * 11 0 * * * 10 0 0 1 0

x1, x2 x3, x4 00 01 11 10

00 0 0 0 0

01 0 * * *

11 1 * * *

10 0 0 0 0

Formele minime conjunctive (FMC) prin diagrame Karnaugh: f0FMC =


x1 x2 x3 x4

f1FMC = 01 11 10

x1 x3 x4

x1, x2

00

x3, x4 00 01 11 10 1 0 0 0 0 * * * 0 * * * 0 0 0 0

x1, x2 x3, x4 00 01 11 10

00 0 1 0 0

01 0 * * *

11 0 * * *

10 0 0 0 0

f2FMC = x1 x3 x4 x3, x2 00 x1, x0 00 0 01 0 11 0 10 1 f4FMC = x1 x2 x3, x2 x1, x0 00 01 11 10 f6FMC =


x1 x3 x4

f3FMC = 01 0 * * * 11 0 * * * 10 0 0 0 0 x3, x2 x1, x0 00 01 11 10 f5FMC =

x1 x3 x4

00 0 0 1 0

01 0 * * *

11 0 * * *

10 0 0 0 0

x1 x2 x3 x4

00 0 0 0 0

01 1 * * *

11 0 * * *

10 0 0 0 0

x3, x2 x1, x0 00 01 11 10

00 0 0 0 0

01 * * * *

11 0 * * *

10 1 0 0 0

f7FMC = 00 0 0 0 0 01 0 * * * 11 0 * * * 10 0 1 0 0 x3, x2 x1, x0 00 01 11 10 00 0 0 0 0

x1 x3 x4

x3, x2 x1, x0 00 01 11 10

01 0 * * *

11 0 * * *

10 0 0 0 1

f8FMC = x1 x3 x4 x3, x2 x1, x0 00 01 11 10

f9FMC = x1 x2 00 0 0 0 0 01 0 * * * 11 0 * * * 10 0 0 1 0

x3, x2 x1, x0 00 01 11 10

00 0 0 0 0

01 0 * * *

11 1 * * *

10 0 0 0 0

Minimizarea funciei cu metoda Quine-McClusky Aceast metod pornete de la forma canonic a funciei de minimizat. Metoda are dou etape: se determin implicanii primi se selecteaz dintre implicanii primi obinui doar aceia care acoper total termenii canonici ai funciei date i asigur realizarea acesteia la un pre de cost minim.

Termenii canonici se compar n felul urmtor: - se compar fiecare termen canonic cu toi ceilali - cnd se gsesc doi termeni care au propietate de adicen, variabila redundant se elimin, obinndu-se un termen elementar. - primul ciclu de comparaii se consider ncheiat n momentul n care s-au compara ntre ei toi termenii canonici, obinndu-se toi implicanii primi posibili. - se compar ntre ei pe acelai criteriu termenii elementari obinui. Se vor face attea cicluri de comparaie cte sunt necesare, pentru a nu mai exista termeni elementari cu proprietatea de adiacen. f0FCD = P0 = (0) = *4 = 0100 *5 = 0101; *7 = 0111; *8 = 1000; *10 = 1010; *11 = 1011;
x3 x 2 x1 x 0

= 0000

Grupa 0 1 2 3 Grupa 0 IP TC
x3 x2 x1 x0 x2 x1 x0 x3 x1 x0

IT P0 *8 *4 *5 *10 *7 *11 IT P0, *8 P0, *4

x3 x2 x1 x0 0000 1000 0100 0101 1010 0111 1011 x3 x2 x1 x0 0000-00

*
x3 x1 x0

f0FMD =

f1FCD = P1 = (1) = *4 = 0100 *5 = 0101; *7 = 0111; *8 = 1000; *10 = 1010; *11 = 1011; Grupa 0 2 3 Grupa 1

x3 x2 x1 x0

= 0001

IT P1 *4 *8 *5 *10 *7 *11 IT P1, *5

x3 x2 x1 x0 0001 0100 1000 0101 1010 0111 1011 x3 x2 x1 x0 0-01

I P TC
x3 x2 x1 x0

x3 x1 x0

*
x3 x1 x0

f1FMD =

c) Implementarea functiilor (individual) numai cu porti logice SI-NU (realizate in tehnologia TTL). Implementarile pentru fiecare dintre cele 10 functii de ieire sunt prezentate mai jos: d) Ansamblul functiilor logice realizat numai cu porti logice SI-NU (porti logice realizate in tehnologia TTL).

e) Implementarea ansamblului functiilor logice: - primele doua porti prin SAU-NU (tehnologia CMOS); - ultimele doua porti prin SI-NU (tehnologia TTL).

f) Implementarea ansamblului functiilor logice cu MUX-uri de 8 si 16 cai in tehnologia CMOS

g) Implementarea ansamblului cu DMUX-uri de 8 cai (realizate in tehnologia TTL).

Incapsularea portilor in circuitele logice folosite:


14 13 12 11 10 9 8 14 13 12 11 10 9 8

Vcc
12 13 11 9 10 8

Vcc
9 10 11 8

74LS00
1 2 3 4 5 6 1 2 13 12 3 4 5

74LS10
6

V dd
1 2 3 4 5 6 7 1 2 3 4 5 6

V dd
7

14

13

12

11

10

14

13

12

11

10

Vcc
12 13 11 10 9 8

Vcc
11 12 13 10

4001
1 2 3 5 6 4 1 2 8 9 3 4 5 6

4025

V dd
1 2 3 4 5 6 7 1 2 3 4 5 6

V dd
7