`timescale 1ns / 1ps module pong(clk50,red,green,blue,hsync,vsync, button,led); input [8:0] button; input clk50; output red; output green;

output blue,led; output hsync; output vsync; // divide input clock by two, and use a global // clock buffer for the derived clock reg clk25_int; always @(posedge clk50) begin clk25_int <= ~clk25_int; end wire clk25; BUFG bufg_inst(clk25, clk25_int); wire [9:0] xpos; wire [9:0] ypos; Display DisInstance(clk25, hsync, vsync, xpos, ypos); Grid_Display Grid_Displayinst(clk25,xpos, ypos, red, green, blue, button,led); endmodule

module Grid_Display(clk25,xpos,ypos,red,green,blue, button,led); input clk25; input [9:0] xpos;//responsible for current pixel display location input [9:0] ypos;// responsible for current display row input [8:0] button; //spartan 3 kit has 3-bits per pixel, so 2^3 means 8 colours can be selected. output output output output red; // colour 1 green; // colour 2 blue; // colur 3 led;

//reg tempRed,tempGreen,tempBlue, GridRed,GridGreen,GridBlue; //reg nextPlayer=1; reg player1,player2; reg [8:0] player1History=0,player2History=0; wire [8:0] a,b; wire grid = ((xpos >= (xpos >= 4 && xpos <= (xpos >= 200 && xpos (xpos >= 440 && xpos 4 && xpos <= 799 && ypos >= 160 && ypos <= 165) || 790 && ypos >= 310 && ypos <= 315) || <= 205 && ypos >= 0 && ypos <= 520) || <= 445 && ypos >= 0 && ypos <= 520));

always @(posedge clk25) begin player1History= 1? button ^ player2History: 0; player2History= 1? button ^ player1History: 0 ;

player1 = ((player1History[0] && (xpos >=50 && xpos<=150 && ypos >= 20 && ypos < =120) ) || (player1History[1] && (xpos >=250 && xpos<=350 && ypos >= 20 && ypos <=120)) || (player1History[2] && (xpos >=490 && xpos<=590 && ypos >= 20 && ypos <=120)) || (player1History[3] && (xpos >=50 && xpos<=150 && ypos >= 180 && ypos <=280)) || (player1History[4] && (xpos >=250 && xpos<=350 && ypos >= 180 && ypos <=280)) || (player1History[5] && (xpos >=490 && xpos<=590 && ypos >= 180 && ypos <=280)) || (player1History[6] && (xpos >=50 && xpos<=150 && ypos >= 330 && ypos <=430)) || (player1History[7] && (xpos >=250 && xpos<=350 && ypos >= 330 && ypos <=430)) || (player1History[8] && (xpos >=490 && xpos<=590 && ypos >= 330 && ypos <=430)) ); player2 = ((player2History[0] && (xpos >=50 && xpos<=150 && ypos >= 20 && ypos < =120) ) || (player2History[1] && (xpos >=250 && xpos<=350 && ypos >= 20 && ypos <=120)) || (player2History[2] && (xpos >=490 && xpos<=590 && ypos >= 20 && ypos <=120)) || (player2History[3] && (xpos >=50 && xpos<=150 && ypos >= 180 && ypos <=280)) || (player2History[4] && (xpos >=250 && xpos<=350 && ypos >= 180 && ypos <=280)) || (player2History[5] && (xpos >=490 && xpos<=590 && ypos >= 180 && ypos <=280)) || (player2History[6] && (xpos >=50 && xpos<=150 && ypos >= 330 && ypos <=430)) || (player2History[7] && (xpos >=250 && xpos<=350 && ypos >= 330 && ypos <=430)) || (player2History[8] && (xpos >=490 && xpos<=590 && ypos >= 330 && ypos <=430)) ); end assign a= player1History; assign b= player2History; assign red = (grid || player1 ); assign green = (grid || player2); assign blue = (grid );

endmodule

module Display(clk25, hsyncOut, vsyncOut, xposOut, yposOut); input clk25; // clock divided by 2 output hsyncOut; output vsyncOut; output [9:0] xposOut; output [9:0] yposOut; reg [9:0] xpos; // as resolution is 800 pixel by 600 rows so both of the values can be covered in 2^10 bits. reg [9:0] ypos; wire endline = (xpos == 799); // 1 pixel has dropped cz ov retrace time 799 always @(posedge clk25) begin if (endline) xpos <= 0; // if in 1 row 799 pixels are displayed else xpos <= xpos + 1; // counter tracks current pixel dispay location on a given row end always @(posedge clk25) begin if (endline) // if 799 pixels are displayed then change the row begin if (ypos == 520) // 520 ypos <= 0; else ypos <= ypos + 1; // counter tracks the current di splay row. end end reg hsync, vsync; // for 800 pixel by 600 rows pulse width of hsync is 96 clocks and pulse width o f vsync signal is 2 clocks. always @(posedge clk25) // passing through d-flip flop 2 get glitch free output. begin hsync <= ~(xpos > 664 && xpos <= 759); // active for 96 clocks, here pu lse width of sync signal is 96 clocks. vsync <= ~(ypos == 490 || ypos == 491); // active for lines 490 and 49 1 end assign assign assign assign hsyncOut = hsync; vsyncOut = vsync; xposOut = xpos; yposOut = ypos;

endmodule