VLSI WORKSHOP

COURSE CONTENT
Day1
Introduction to VLSI Design flow Digital System Design

Day2 Introduction to HDL Basic Concepts

Types of Modeling Data Types in Verilog, System Task Logic Values Port Definition, Declaration Port Connection Rule Gate Types Gate Delays Vectors in Verilog Test Bench Basics Writing Verilog Modules Gate Level Modeling Examples

Gate Level Modeling

COURSE CONTENT
Day3 Dataflow Modeling

Type of Operators Continuous assignment statement Regular assignment delay Examples Of Data Flow Modeling
Initial and Always Statements Procedural Assignment Statements Timing Control Statements If__ else Statements Case statement Block Statements Loops Design of Flip-flops Design of Digital circuits using Behavioral Modeling

Behavioral Modeling

Task and Functions State Machines

Moore and Mealy Machines Examples of Moore and Mealy Machines

COURSE CONTENT
Day4
Mini Project System Verilog Overview
Overview of SystemVerilog SystemVerilog Books and Resources
System verilog data types and enumerated types Operators, Queues and Arrays Typedefs Structures and unions Casting, Packages and Strings Loop enhancements Tasks and Functions Time values Basics of OOP Class Based Randomization Advanced OOP

Day5

Data Types

Flow Control

OOP in System Verilog

COURSE CONTENT
Day6
Advanced Concepts Interfaces Process Synchronization Program Blocks Functional Coverage SV labs Mini Project Open Verification Methodology(OVM) Overview Stimulus Modeling Creating a Simple Environment OVM Simulation Phases Test Classes OVM Sequences

Day7

Day8

Day9

Day10