Documente Academic
Documente Profesional
Documente Cultură
Internal Guide by:Prof. Hardik .H .Patel Assistance professor, Department of EC, SRPEC, Unjha.
By:Ankita Patel(090780111007) Kinjal Prajapati(100783111004) Vidhi Patel(090780111001) 8th Semester, B.E (EC), SRPEC, Dabhi Unjha
CONTENTS
AIM MOTIVATION OVERVIEW OF PROJECT COMPONENT SPECIFICATION STATE DIAGRAM SIMULATION /RESULTS WORK PLAN CONCLUSION FUTURE WORK REFERENCES
RS-232 TX/RX USING FPGA WITH VHDL CODE
8/14/2013
AIM
Aim of this project is to transfer data from PC to FPGA and FPGA to PC using serial communication. For this Serial communication we are using RS-232 for interfacing of PC and FPGA and Using Code of data transfer with VHDL language we Transfer data between FPGA and PC. Hyper terminal is used for transferring data and for giving input for receiver section and showing output on hyper terminal for transmitting section.
8/14/2013
MOTIVATION
Many more Data acquisition system are available in the market Based on DSP ,microcontroller and FPGA etcBut the Faster response, low Power Consumption, less time consuming of FPGA we are going though FPGA. Reason for Choosing FPGA based System: Faster Response. Low Power Consumption. Less Time Consuming. Data Security. Accuracy.
8/14/2013
RS-232 TX/RX USING FPGA WITH VHDL CODE
OVERVIEW OF PROJECT
8/14/2013
ALTERA MODEL[1]
8/14/2013
RX
8 BIT
DATA R (7 DOWN T0 0)
RST
CLK
TX
8 BIT DATA_TX (7 DOWN T0 0)
RST
CLK
HYPER TERMINAL
This is a built in interface in windows which sends and receives data through the serial port.it has the option of sending through port COM1 and COM2 and also has flexible baud rate.
8/14/2013
10
COMPONENTS
Altera kit(FPGA) RS-232 Power Supply Cyclone QUARTUS II software PC
8/14/2013
11
8/14/2013
12
8/14/2013
13
8/14/2013
RS-232 TX/RX USING FPGA WITH VHDL CODE
14
STATE DIAGRAM
8/14/2013
15
Data_r(1)<=rx
S3 Data_r(2)<=rx S4 Data_r(3)<=rx
16
S5
TX<=data_tx(1)
TX<=data_tx(3)
S5 S4
TX<=data_tx(1)
TX<=data_tx(2)
17
SIMULATION/RESULT
8/14/2013
18
Design flow
19
8/14/2013
20
8/14/2013
21
22
23
24
25
WORK PLAN
Jul-12 Aug-12 Sep-12 Oct-12
Sr. No
Sr. No Selection of project (1) . Topic (2) . Introduction Detail study in project (3) . work To study the VHDL (4) . Language
W- WW-1 W-2 W-3 4 1 W-2 W-3 W-4 W-1 W-2 W-3 W-4 W-1 W-2 W-3 W-4
26
WORK PLAN
Sr. No Sr. No (1) . Coding of receiver part (2) Implement receiver . code on altera kit (3) Coding of transmiter . part (4) Implement transmiter . part on altera kit Implement both code (5) on Xillinx spartan3 . code (6) Prepare a report and . presenatation
8/14/2013
RS-232 TX/RX USING FPGA WITH VHDL CODE
Jan-13
Feb-13
Mar-13
Apr-13
W- WW-1 W-2 W-3 4 1 W-2 W-3 W-4 W-1 W-2 W-3 W-4 W-1 W-2 W-3 W-4
27
CONCLUSION
The FPGA based Transmitter/Receiver data using serial communication are most of the high fidelity (hi-fi) are maintain using VHDL code design was successfully design by behavioral model. Here, we get particular output according input what we are given as and that output is unique for every input. So that we control many circuits by every unique output or we operate that many circuits by giving input.
8/14/2013
28
FUTURE WORK
We can also use this method, For transferring file and documents from one pc to another pc like one pc is data transmit to the FPGA and from FPGA to another pc. In the transmitter section, There is not stable output ,that means here we get continuous output on the hyper terminal. so we are trying to get the stable output or static output for transmitter section. In this session project was based on different code for TX/RX. So, code will be merged for TX and RX with help of logic loop.
8/14/2013
29
REFERENCES
[1] Cyclone II FPGA Starter Development Board Reference Manual [2]Stephen Brown and Jonathan Rose(for fpga)s Department of Electrical and Computer Engineering University of Toronto email: brown | jayar@eecg.toronto.edu
8/14/2013
30
THANK YOU
8/14/2013
31