`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
//
// Company:
// Engineer:
//
// Create Date:
17:55:42 08/06/2013
// Design Name:
// Module Name:
color_spectrum
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//
module color_spectrum
(
input [9:0]hcount,vcount,
output reg r,g,b);
always @ (hcount,vcount)
begin
if((hcount>10'd143 && hcount<10'd223)
{r,g,b}=3'b111;
else
if((hcount>10'd223 && hcount<10'd303)
{r,g,b}=3'b110;
else
if((hcount>10'd303 && hcount<10'd383)
{r,g,b}=3'b101;
else
if((hcount>10'd383 && hcount<10'd463)
{r,g,b}=3'b100;
else
if((hcount>10'd463 && hcount<10'd543)
{r,g,b}=3'b011;
else
if((hcount>10'd543 && hcount<10'd623)
{r,g,b}=3'b010;
else
if((hcount>10'd623 && hcount<10'd703)
{r,g,b}=3'b001;
else
if((hcount>10'd703 && hcount<10'd784)
{r,g,b}=3'b000;
else
{r,g,b}=3'bxxx;
end
endmodule

&& (vcount>10'd30 && vcount<10'd511))

&& (vcount>10'd30 && vcount<10'd511))
&& (vcount>10'd30 && vcount<10'd511))
&& (vcount>10'd30 && vcount<10'd511))
&& (vcount>10'd30 && vcount<10'd511))
&& (vcount>10'd30 && vcount<10'd511))
&& (vcount>10'd30 && vcount<10'd511))
&& (vcount>10'd30 && vcount<10'd511))