ARBITER

An Arbiter is a logic block which manages the resource allocations in the context of a single resource shared by multiple masters.

PORT DESCRIPTION:
INPUT PORTS: Read Request0, Read Request1, Read Request2, Read Request3(Active low): Request signals from the masters requesting for read operation. Request is valid if ReadRequest is LOW.else if there is no request, ReadRequest is HIGH

Write Request0, Write Request1, Write Request2, Write Request3(Active low): Request signals from the masters requesting for Write operation. Request is valid if WriteRequest is LOW.else if there is no request, WriteRequest is HIGH

Ack_FSM(Active low): Acknowledgement signal provided by the FSM_control block. When the read or write operation is completed the Ack_FSM is LOW, else Ack _FSM is HIGH.

OUTPUT PORTS: Grant [3 :0 ]: (Grant ) Based upon the priority logic, the arbiter grants requests by making Grant=1(high) ,and for denial Grant=0(low).

BusSelect[1:0] : (Bus Select Lines) Select lines to allocate the required bus to the outputs and inputs. The bus select lines selected the bus lines corresponding to the master whose request is granted.

R/W_Bar: Read/Write Depending on the type of request by master, the arbiter block makes R/W_bar line HIGH for Read operation and similarly R/W_bar =0 for write operation.