Documente Academic
Documente Profesional
Documente Cultură
Compal confidential
Schematics Document
Mobile AMD S1G2 CPU with ATI
RS780M(NB) & SB700(SB) core logic
3
2007-12-03
REV:0.2
l.c
ho
Cover Sheet
Rev
0.2
f@
ai
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
he
2007/08/02
Issued Date
tm
Security Classification
om
of
48
Compal Confidential
Thermal Sensor
ADM1032ARMZ
Page 6
Page 30
Fan conn
72QFN
DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
Dual Channel
Clock Generator
SLG8SP626VTR
Page 8, 9
Page 15
Page 4
Page 4, 5, 6, 7
USB conn x2
LVDS Panel
Interface Page
ATI RS780M
17
CRT
BT Conn
Page 16
DDR2 400MHz
HDMI
4X PCI-E
USB conn x1
PCI-E BUS*5
CardReader
JMicron
JMB385-LGEZ0A
Realtek
Mini-Card*2
8102E(10/100M) WLAN & WWAN
Page 27
Page 25
CardReader Socket
26
Page 31
Page 17
SATA Slave
FingerPrinter AES1610
USBx1
page 35
SATA Slave
Page 19, 20, 21, 22, 23
daughter board
daughter board
Page 26
MDC V1.5
3
daughter board
SATA Master-2
Express Card
Page 26
Page 31
USB WebCam
SATA Master-1
ATI SB700
daughter board
Mini-Card WWAN
Page
14" Only
USB2.0 X12
A-Link Express II
Page 18
Page 31
LPC BUS
RJ45/11 CONN
daughter board
Page 34
Audio CKT
Page 25
Page 27
TPA6017A2
Page 28
KBC
ENE KB926
Codec_IDT9271B7
Page 29
Page 24
Page 33
Docking CONN.
*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*S-VIDEO OUT
*SPDIF
*Headphone/Line Out L/R
*Stereo Mic L/R
*Volume Control
*Consumer IR
*USB x1
*DC JACK
LED
Page 24
P41
Int.KBD
Page 34
Page 33
Page 19
Consumer IR
Page 34
Page 32
P35
Issued Date
Page 31
Power OK CKT.
Security Classification
Page 35
RTC CKT.
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Page 36
B
Title
Rev
0.2
Sheet
of
48
O MEANS ON
Voltage Rails
X MEANS OFF
Symbol Note :
+1.5VS
power
plane
+0.9V
+VCCP
+CPU_CORE
+B
12/03 update
+VGA_CORE
+2.5VS
+1.8VS
+1.2VS
+0.9VGA
S1
S3
S5 S4/AC
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
HEX
ADDRESS
DDR SO-DIMM 0
A0
10100000
I2C_CLK
DDR SO-DIMM 1
A4
10100100
I2C_DATA
D2
11010010
DDC_CLK0
SMB_EC_DA2
DDC_DATA0
DDC_CLK1
EC SM Bus1 address
Device
HEX
Address
Smart Battery
16H
0001 011X b
24C16
A0H
1010 000X b
EC SM Bus2 address
DDC_DATA1
SCL0
Device
HEX
Address
CPU
98H
1001 100X b
SCL1
9AH
1001 101X b
SDA1
ADI1032-2 CPU
KB926
RS780M
RS780M
RS780M
SB700
SDA0
SB700
SCL2
SB700
SDA2
4
KB926
SCL3
SB700
SDA3
X
X
X
X
X
X
X
X
X
BATT
V
X
X
X
X
X
X
X
X
SERIAL
EEPROM
V
X
X
X
X
X
X
X
X
THERMAL
SENSOR
CPU &
ADM1032
SODIMM
I / II
X
V
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
X
2007/08/02
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
CLK CHIP
X
X
X
X
X
V
X
X
X
Security Classification
Issued Date
INVERTER
Title
MINI CARD
Slot 2
X
X
X
X
X
X
V
X
X
LCD
HDMI
X
X
V
X
X
X
X
X
X
X
X
X
V
X
X
X
X
X
G-Sensor
X
X
X
X
X
X
X
V
X
om
l.c
ai
tm
ho
S0
Rev
0.2
f@
State
in
+3VALW
Sheet
E
xa
+1.8V
he
+5VALW
Layout Notes
of
48
VLDT CAP.
+1.2V_HT
250 mil
1
<10>
<10>
H_CADIP[0..15]
H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADON[0..15]
H_CADOP[0..15]
H_CADON[0..15]
<10>
C1
4.7U_0805_10V4Z
<10>
C2
4.7U_0805_10V4Z
C3
0.22U_0603_16V4Z
C4
0.22U_0603_16V4Z
C5
180P_0402_50V8J
C6
180P_0402_50V8J
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
J3
J2
J5
K5
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
N1
P1
P3
P4
<10>
<10>
<10>
<10>
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
AE2 +VLDT_B 1
C7
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
Y1
W1
Y4
Y3
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
R2
R3
T5
R5
2
4.7U_0805_10V4Z
If VLDT is connected only on one side, one
4.7uF cap should be added to the island
side.
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
+5VS
11/14 update
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
<10>
<10>
<10>
<10>
JP2
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
<10>
<10>
<10>
<10>
HT LINK
D1
D2
D3
D4
1
D1
CH751H-40PT_SOD323-2
<10>
<10>
<10>
<10>
C8
4.7U_0805_10V4Z
C9
0.1U_0402_16V4Z
VLDT=500mA
1
2
5
6
Athlon 64 S1
Processor Socket
D Q1
@ D2
G
FAN_PWM
RLZ5.1B_LL34
SI3456BDV-T1-E3_TSOP6
<33>
GND
GND
9/20 SP07000DM00/SP07000EQ00
1
2
3
4
ACES_88231-02001
CONN@
+VCC_FAN
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
1
2
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
of
48
<9>
1
DDR_A_CLK#0
C10
1.5P_0402_50V9C
DDR_A_CLK1
1
DDR_A_CLK#1
C11
1.5P_0402_50V9C
+1.8V
R1
C14
1.5P_0402_50V9C
1K_0402_1%
1
DDR_B_CLK#0
+MCH_REF
DDR_B_CLK1
1
R2
C15
1.5P_0402_50V9C
C12
1K_0402_1%
1
DDR_B_CLK#1
09/13 update
DDR_B_CLK0
C13
2
2
1000P_0402_25V8J
0.1U_0402_16V4Z
+0.9V
+0.9V
JCPUB
+1.8V
R4
1
1
R3
39.2_0402_1%
2
2
39.2_0402_1%
DDR_A_ODT0
DDR_A_ODT1
<8>
<8>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
<8>
<8>
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
<8> DDR_A_CLK0
<8> DDR_A_CLK#0
<8> DDR_A_CLK1
<8> DDR_A_CLK#1
<8>
DDR_A_MA[15..0]
<8>
<8>
<8>
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
<8>
<8>
<8>
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
VTT1
VTT2
VTT3
VTT4
AF10
AE10
MEMZP
MEMZN
MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9
H16
RSVD_M1
T19
V22
U21
V19
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
T20
U19
U20
V20
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
J22
J20
MA_CKE0
MA_CKE1
T2
<8>
<8>
D10
C10
B10
AD10
PAD
DDR_A_ODT0
DDR_A_ODT1
W10
AC10
AB10
AA10
A10
VTT_SENSE
Y10
MEMVREF
W17
VTT_SENSE
+MCH_REF
RSVD_M2
B18
MB0_ODT0
MB0_ODT1
MB1_ODT0
W26
W23
Y26
DDR_B_ODT0
DDR_B_ODT1
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
V26
W25
U22
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
MB_CKE0
MB_CKE1
J25
H26
DDR_CKE0_DIMMB
DDR_CKE1_DIMMB
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
P22
R22
A17
A18
AF18
AF17
R26
R25
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
R20
R23
J21
MA_BANK0
MA_BANK1
MA_BANK2
MB_BANK0
MB_BANK1
MB_BANK2
R24
U26
J26
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
R19
T22
T24
MA_RAS_L
MA_CAS_L
MA_WE_L
MB_RAS_L
MB_CAS_L
MB_WE_L
U25
U24
U23
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
T1
09/13 update
PAD
N19
N20
E16
F16
Y16
AA16
P19
P20
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
PAD
T3
DDR_B_ODT0
DDR_B_ODT1
<9>
<9>
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
<9>
<9>
DDR_CKE0_DIMMB
DDR_CKE1_DIMMB
<9>
<9>
DDR_B_CLK0 <9>
DDR_B_CLK#0 <9>
DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>
DDR_B_MA[15..0]
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
<9>
<9>
<9>
DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
DDR_B_DM[7..0]
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
MEM:DATA
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
A12
B16
A22
E25
AB26
AE22
AC16
AD12
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor
Socket
JCPUC
DDR_B_D[63..0]
DDR_A_CLK0
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
DDR_A_D[63..0]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
E12
C15
E19
F24
AC24
Y19
AB16
Y13
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
<8>
DDR_A_DM[7..0]
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor Socket
CONN@
l.c
ai
Rev
0.2
f@
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
he
2007/08/02
Issued Date
tm
Security Classification
om
CONN@
of
48
+2.5VDDA
VDDA=300mA
L1
3300P_0402_50V7K
1
2
FBM_L11_201209_300L_0805
1
1
1
1
+
4.7U_0805_10V4Z
C17
C18
C19
0.22U_0603_16V4Z
2
2
2
2
+2.5VS
+1.8V
R10
1
R5
2
10K_0402_5%
2
300_0402_5%
@ R6
1
C16
100U_D2_10VM
11/13 update
0_0402_5%
2
ENTRIP2
<37,39>
Q3
CPU_THERMTRIP#_R
3
1
MMBT3904_NL_SOT23-3
C
1
R16
1
R7
2
0_0402_5%
2
0_0402_5%
H_THERMTRIP#_EC
H_THERMTRIP#
<33>
<20>
JCPUD
C20
LDT_RST#
H_PWRGD_CPU
LDT_STOP#
CPU_LDT_REQ#
B7
A7
F10
C6
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
CPU_SIC
CPU_SID
AF4
AF5
AE6
SIC
SID
ALERT_L
R6
P6
HT_REF0
HT_REF1
R8
169_0402_1%
CLK_CPU_BCLK#
C21
2
3900P_0402_50V7K
Address:100_1100
+1.2V_HT
R13
R14
1
1
2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1
R15
300_0402_5%
<19>
LDT_RST#
1
T4
+CPU_CORE_0
R487 10_0402_5%
1
2CPU_VDD0_FB_H
1
2CPU_VDD0_FB_L
R486 10_0402_5%
C22
0.01U_0402_25V4Z
@
CPU_VDD1_FB_H
CPU_VDD1_FB_L
CPU_VDD1_FB_H Y6
CPU_VDD1_FB_L AB6
VDD1_FB_H
VDD1_FB_L
VDDNB_FB_H
VDDNB_FB_L
H6
G6
PAD
T9 PAD
T11 PAD
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN
R25
2 0_0402_5%
+1.8VS
2
1
H_PWRGD_CPU
+3VS
H_PWRGD_CPU
E9
E8
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
C2
AA6
TEST9
TEST6
A3
A5
B3
B5
C1
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
+1.8V
CPU_SVC
CPU_SVD
09/11 update
09/19 update
PAD
PAD
T42
T43
VDD_NB_FB_H
VDD_NB_FB_L
DBREQ_L
E10
CPU_DBREQ#
TDO
AE9
CPU_TDO
R22
1
1
R23
1K_0402_5%
2
2
1K_0402_5%
+CPU_CORE_NB
R484 10_0402_5%
VDD_NB_FB_H 1
2
VDD_NB_FB_L 1
2
R485 10_0402_5%
Close to CPU
J7
H8
CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N
TEST17
TEST16
TEST15
TEST14
D7
E7
F7
C7
CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0
TEST7
TEST10
C3
K8
TEST8
C4
TEST29_H
TEST29_L
C9
C8
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
VDD_NB_FB_H <43>
VDD_NB_FB_L <43>
TEST28_H
TEST28_L
TEST25_H
TEST25_L
AB8
AF7
AE7
AE8
AC8
AF8
+1.8V
R17
2
THERMDC_CPU
THERMDA_CPU
<19>
PAD
PAD
PAD
PAD
PAD
PAD
T5
T6
route as differential
as short as possible
testpoint under package
T7
T8
T10
T12
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
PAD
PAD
T13
T14
H18
H19
AA7
D5
C5
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
34.8K_0402_1%~N
C23
G
TEST18
TEST19
CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
CPU_MEMHOT#_1.8V
3
1
R59
TEST23
H10
G9
R814
1
20K_0402_5%
11/30 update
C939 0.1U_0402_16V4Z
AD7
CPU_PROCHOT#_1 .8
0.1U_0402_16V7K
+1.8VS
2
CPU_SIC
SMB_EC_DA2
SMB_EC_DA2
<33>
SMB_EC_CK2
<33>
Q127
FDV301N_NL_SOT23-3
G
+1.8V
FDV301N_NL_SOT23-3
Q129 3
1 SMB_EC_CK2
D
R36
300_0402_5%
CPU_SID
R18
2
1
390_0402_5%
R19
2
1
390_0402_5%
+1.8V
<19>
CPU_TEST23_TSTUPD
@ MMBT3904_NL_SOT23-3
Q2
1
H_PROCHOT#
2
0_0402_5%
<43>
<43>
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
W7
W8
W9
Y9
R175
THERMDC
THERMDA
VDDIO_FB_H
VDDIO_FB_L
DBRDY
TMS
TCK
TRST_L
TDI
<43>
<43>
@ 300_0402_5%
VDD0_FB_H
VDD0_FB_L
+CPU_CORE_1
R489 10_0402_5%
1
2CPU_VDD1_FB_H
1
2CPU_VDD1_FB_L
R21
300_0402_5%
AF6
AC7
AA8
F6
E6
R488 10_0402_5%
09/13 update
THERMTRIP_L
PROCHOT_L
MEMHOT_L
CPU_VDD0_FB_H
CPU_VDD0_FB_L
G10
AA9
AC9
AD9
AF9
CPU_SVC
CPU_SVD
1
@ 10K_0402_5%
2
300_0402_5%
11/22 update
CPU_VDD0_FB_H
CPU_VDD0_FB_L
Close to CPU
LDT_RST#
SVC
SVD
<43>
<43>
CPU_ DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
+1.8VS
CLKIN_H
CLKIN_L
CPU_SVC
CPU_SVD
A6
A4
2
R11
1
R9
+1.8V
M11
W18
CLK_CPU_BCLK
A9
A8
KEY1
KEY2
<15>
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
2 3900P_0402_50V7K
VDDA1
VDDA2
F8
F9
+1.8V
+3VS
+1.8VS
R30
300_0402_5%
CPU_LDT_REQ#
C27
1
CPU_LDT_REQ#
C24
0.01U_0402_25V4Z
@
<11,19>
+1.8V
C26
2
U2
1
THERMDC_CPU 3
2
2200P_0402_50V7K
4
2200p change to
1000p for ADT7421
SCLK
SMB_EC_CK2
D+
SDATA
SMB_EC_DA2
D-
ALERT#
GND
VDD
THERM#
R24
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
R26
R27
R28
R29
R31
R32
R33
R34
R35
1
2
2
2
2
2
2
2
2
2 @ 300_0402_5%
09/11 update
THERMDA_CPU 2
CPU_TEST27_SINGLECHAIN
ADM1032ARMZ-2REEL_MSOP8
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
HDT Connector
JP3
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
26
2
1
1
1
1
1
1
1
1
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
+3VS
5
C25
0.01U_0402_25V4Z
@
U1
HDT_RST#
LDT_STOP#
Y
3
LDT_STOP#
2
1
@ 220_0402_5% R37
2
1
@ 220_0402_5% R38
2
1
@ 220_0402_5% R39
2
1
@ 220_0402_5% R40
2
1
@ 220_0402_5% R41
<11,19>
0.1U_0402_16V4Z
EC is PU to 5VALW
@ SAMTEC_ASP-68200-07
LDT_RST#
SB_PWRGD
<20,33,43>
@ NC7SZ08P5X_NL_SC70-5
9/20 SP020016900
Address:100_1101
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
E
of
48
VDD(+CPU_CORE) decoupling.
+CPU_CORE_0
18A/720mil/36vias
C30
330U_X_2VM_R6M
C28
330U_X_2VM_R6M
1
C31
330U_X_2VM_R6M
C29
330U_X_2VM_R6M
+CPU_CORE_1
?A/?mil/?vias
+CPU_CORE_NB
C32
22U_0805_6.3V6M
C33
22U_0805_6.3V6M
C34
22U_0805_6.3V6M
C35
22U_0805_6.3V6M
C36
22U_0805_6.3V6M
+CPU_CORE_0
C38
22U_0805_6.3V6M
C39
22U_0805_6.3V6M
+1.8V
+CPU_CORE_1
C40
0.22U_0603_16V4Z
C37
22U_0805_6.3V6M
C41
0.01U_0402_25V4Z
C42
180P_0402_50V8J
C43
0.22U_0603_16V4Z
C44
0.01U_0402_25V4Z
?A/?mil/?vias
+CPU_CORE_0
+CPU_CORE_1
1
1
C45
180P_0402_50V8J
18A/720mil/36vias
JCPUE
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
K16
M16
P16
T16
V16
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
+CPU_CORE_1
+1.8V
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor Socket
CONN@
+CPU_CORE_NB
VDDIO decoupling.
+CPU_CORE_NB
+1.8V
C52
22U_0805_6.3V6M
2
1
C46
22U_0805_6.3V6M
C47
22U_0805_6.3V6M
C48
C49
C50
C53
22U_0805_6.3V6M
C54
22U_0805_6.3V6M
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor Socket
C51
CONN@
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2
2
2
2
+0.9V
decoupling.
JCPUF
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
VTT decoupling.
+ C59
220U_Y_4VM
2
C55
0.22U_0603_16V4Z
C56
0.22U_0603_16V4Z
C57
0.22U_0603_16V4Z
+1.8V
C61
0.01U_0402_25V4Z
C58
0.22U_0603_16V4Z
1
+1.8V
C60
0.01U_0402_25V4Z
C62
180P_0402_50V8J
C63
180P_0402_50V8J
C64
180P_0402_50V8J
C67
4.7U_0805_10V4Z
C68
0.22U_0603_16V4Z
C69
0.22U_0603_16V4Z
C70
1000P_0402_25V8J
C71
1000P_0402_25V8J
C72
180P_0402_50V8J
C73
180P_0402_50V8J
+0.9V
+1.8V
C66
4.7U_0805_10V4Z
C79
4.7U_0805_10V4Z
C80
4.7U_0805_10V4Z
C81
0.22U_0603_16V4Z
C82
0.22U_0603_16V4Z
C83
1000P_0402_25V8J
C84
1000P_0402_25V8J
C85
180P_0402_50V8J
C86
180P_0402_50V8J
+ C78
220U_Y_4VM
@
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
l.c
C77
4.7U_0805_10V4Z
ai
tm
C76
4.7U_0805_10V4Z
Rev
0.2
f@
C75
4.7U_0805_10V4Z
in
Sheet
E
xa
C74
4.7U_0805_10V4Z
he
om
1
1
of
48
+V_DDR_MCH_REF
+1.8V
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DM[0..7]
<5>
DDR_A_DQS[0..7]
<5>
DDR_A_MA[0..15]
<5>
DDR_A_DQS#[0..7]
<5>
DDR_A_DM0
DDR_A_DQS[0..7]
DDR_A_D6
DDR_A_D7
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_D12
DDR_A_D13
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
<5>
8
7
6
5
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_DM1
DDR_A_CLK0 <5>
DDR_A_CLK#0 <5>
DDR_A_D14
DDR_A_D15
+1.8V
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
2
DDR_A_D26
DDR_A_D27
<5>
DDR_CKE0_DIMMA
<5>
DDR_A_BS#2
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<5>
<5>
DDR_A_BS#0
DDR_A_WE#
<5>
<5>
DDR_A_CAS#
DDR_CS1_DIMMA#
<5>
DDR_A_ODT1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
<9,15,20,30>
<9,15,20,30>
4
SMB_CK_DAT0
SMB_CK_CLK0
+3VS
1
C103
0.1U_0402_16V4Z
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
R43
1K_0402_1%
DDR_A_D20
DDR_A_D21
+V_DDR_MCH_REF
+V_DDR_MCH_REF
DDR_A_DM2
DDR_A_D22
DDR_A_D23
C95
C96
2
1000P_0402_25V8J
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
<9>
R44
1K_0402_1%
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA
<5>
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
C88
1
1
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
C90
C89
C91
C92
C93
C94
1
1
1
1
1
1
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
47_0804_8P4R_5%
RP5
8
1
7
2
6
3
5
4
DDR_A_ODT1
DDR_CS1_DIMMA#
DDR_A_WE#
DDR_A_CAS#
47_0804_8P4R_5%
RP6
8
1
7
2
6
3
5
4
1
C100
1
C99
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
47_0804_8P4R_5%
RP7
DDR_CS0_DIMMA#
8
1
DDR_A_RAS#
7
2
DDR_A_MA13
6
3
DDR_A_ODT0
5
4
1
C102
1
C101
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
C98
C97
1
1
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
47_0804_8P4R_5%
DDR_A_BS#1 <5>
DDR_A_RAS# <5>
DDR_CS0_DIMMA# <5>
DDR_A_ODT0
<5>
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
3
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
FOX_AS0A426-N8RN-7F
CONN@
9/20 SP07000BZ00/SP07000EU00
DDR2 SOCKET H9.2 (REV)
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
C87
DDR_A_BS#0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3
0.1U_0402_16V4Z
09/13 update
47_0804_8P4R_5%
RP2
8
1
7
2
6
3
5
4
47_0804_8P4R_5%
RP4
8
1
7
2
6
3
5
4
DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DDR_A_DQS#2
DDR_A_DQS2
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
1
2
3
4
47_0804_8P4R_5%
RP3
8
1
7
2
6
3
5
4
DDR_A_MA4
DDR_A_MA2
DDR_A_BS#1
DDR_A_MA0
DDR_A_D16
DDR_A_D17
+1.8V
+0.9V
RP1
DDR_A_D[0..63]
DDR_A_D4
DDR_A_D5
DDR_A_D10
DDR_A_D11
+1.8V
JP4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Title
Rev
0.2
Sheet
of
48
+1.8V
+1.8V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
+V_DDR_MCH_REF
DDR_B_D0
DDR_B_D1
C104
2
1000P_0402_25V8J
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D13
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
+1.8V
+0.9V
JP5
<8>
RP8
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DDR_B_D[0..63]
DDR_B_D4
DDR_B_D5
DDR_B_DM[0..7]
DDR_B_DM0
DDR_B_DQS[0..7]
DDR_B_D6
DDR_B_D7
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
DDR_B_D12
DDR_B_D9
DDR_B_D[0..63]
DDR_B_MA6
DDR_B_MA2
DDR_B_MA0
DDR_CS0_DIMMB#
<5>
DDR_B_DM[0..7]
<5>
DDR_B_DQS[0..7]
<5>
DDR_B_MA[0..15]
<5>
DDR_B_DQS#[0..7]
<5>
8
7
6
5
1
2
3
4
2
C105
1
C106
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C108
1
C107
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C109
1
C110
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C111
1
C112
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C114
1
C113
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C116
1
C115
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C118
1
C117
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
47_0804_8P4R_5%
RP9
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA4
8
7
6
5
DDR_B_DM1
1
2
3
4
47_0804_8P4R_5%
DDR_B_CLK0 <5>
DDR_B_CLK#0 <5>
RP10
DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_B_MA15
DDR_CKE1_DIMMB
DDR_B_D14
DDR_B_D15
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
DDR_B_D21
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
2
<5>
<5>
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<5>
<5>
DDR_B_BS#0
DDR_B_WE#
<5>
<5>
DDR_B_CAS#
DDR_CS1_DIMMB#
<5>
DDR_B_ODT1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
<8,15,20,30>
<8,15,20,30>
SMB_CK_DAT0
SMB_CK_CLK0
+3VS
C119
0.1U_0402_16V4Z
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
DDR_B_D20
DDR_B_D16
RP11
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12
DDR_B_DM2
DDR_B_D22
DDR_B_D23
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
RP12
DDR_B_D28
DDR_B_D29
DDR_B_MA10
DDR_B_BS#0
DDR_B_MA1
DDR_B_MA3
DDR_B_DQS#3
DDR_B_DQS3
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
DDR_B_D30
DDR_B_D31
RP13
DDR_CKE1_DIMMB
DDR_CKE1_DIMMB
DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#
<5>
DDR_B_MA15
DDR_B_MA14
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
RP14
DDR_B_RAS#
DDR_B_BS#1
DDR_B_ODT0
DDR_B_MA13
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_MA13
DDR_B_BS#1 <5>
DDR_B_RAS# <5>
DDR_CS0_DIMMB# <5>
DDR_B_ODT0
<5>
DDR_B_D36
DDR_B_D37
DDR_B_DM4
09/26 update
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_CLK1 <5>
DDR_B_CLK#1 <5>
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+3VS
TYCO_292527-4
CONN@
DDRII SO-DIMM 1
Date:
l.c
ai
Rev
0.2
f@
tm
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
he
2007/08/02
Issued Date
ho
Security Classification
om
9/20 SP07000ET00/SP07000GN00
of
48
U3B
PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0
PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3
<26>
<26>
PCIE_PTX_C_IRX_P5
PCIE_PTX_C_IRX_N5
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
PART 2 OF 6
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
AC8
AB8
PCIE I/F
PCIE I/F SB
TMDS_B_DATA2 <18>
TMDS_B_DATA2# <18>
TMDS_B_DATA1 <18>
TMDS_B_DATA1# <18>
TMDS_B_DATA0 <18>
TMDS_B_DATA0# <18>
TMDS_B_CLK <18>
TMDS_B_CLK# <18>
1
PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3
C152
C153
C154
C155
C156
C157
C158
C159
PCIE_ITX_PRX_P5
PCIE_ITX_PRX_N5
C160 1
C161
1
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
R55
R56
C162
C163
C164
C165
C166
C168
C169
C167
1
1
1
1
1
1
1
1
1
1
2
2
0.1U_0402_16V7K
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3
<26>
<26>
<27>
<27>
<26>
<26>
<25>
<25>
0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCIE_ITX_C_PRX_P5
PCIE_ITX_C_PRX_N5
<26>
<26>
2
1
2
1
1
1
1
1
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1.27K_0402_1%
2K_0402_1%
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
New Card
CardReader
WLAN
LAN10/100
<4>
H_CADOP[0..15]
TV Tuner<4>
H_CADON[0..15]
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
H_CADOP[0..15]
H_CADIP[0..15]
H_CADON[0..15]
H_CADIN[0..15]
H_CADIP[0..15]
<4>
H_CADIN[0..15]
<4>
U3A
+1.1VS
RS780M_FCBGA528
RS780M Display Port Support (muxed on GFX)
GFX_TX0,TX1,TX2 and TX3
DP0
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
DP1
AUX1 and HPD1
<4>
<4>
<4>
<4>
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<4>
<4>
<4>
<4>
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
1 R57
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
T22
T23
AB23
AA22
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
M22
M23
R21
R20
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
2 301_0402_1% C23
A24
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
H24
H25
L21
L20
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
M24
M25
P19
R18
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
B24
B25
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
PART 1 OF 6
<26>
<26>
<27>
<27>
<26>
<26>
<25>
<25>
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
RS780M_FCBGA528
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
<4>
<4>
<4>
<4>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
<4>
<4>
<4>
<4>
1 R58
2 301_0402_1%
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
10
of
48
+3VS
L2
AVDD=100mA
1
2 +AVDD1
BLM18PG121SN1D_0603
1
L4
+AVDD2
C170
+1.8VS
2.2U_0603_6.3V4Z
0_0603_5%
1
2
L6
+AVDDQ
C172
1
2
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
U3C
2
F12 AVDD1(NC)
1
E12 AVDD2(NC)
C175
F14 AVDDDI(NC)
2.2U_0603_6.3V4Z
G15 AVSSDI(NC)
2
H15 AVDDQ(NC)
H14 AVSSQ(NC)
+1.8VS
R68
<6,19>
CPU_LDT_REQ#
NB_ALLOW_LDTSTOP
0_0402_5%
T46
T47
T48
PAD
PAD
PAD
11/05 update
+1.1VS
+1.8VS
1
R62
1
R63
1
R64
RED
2
150_0402_1%
GREEN
2
150_0402_1%
BLUE
2
150_0402_1%
L9
1
2
BLM18PG121SN1D_0603
1
L7
C178
<16>
RED
<16>
GREEN
<16>
BLUE
1
2
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
1
2
L10
C176
+NB_PLLVDD
1
2
+NB_HTPVDD
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
1
2
+1.8VS
L11
C179
1
2
+VDDA18HTPLL
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
1
2
C180
2.2U_0603_6.3V4Z
CRT_HSYNC
CRT_VSYNC
R65
11/13 update
1
2
R71
4.7K_0402_5%
1
2
R72
4.7K_0402_5%
<15>
<15>
G18
G17
E18
F18
E19
F19
RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)
A11
B11
F8
E8
DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)
2 715_0402_1% G14
PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
H17
VDDA18HTPLL
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
CLK_NBHT
CLK_NBHT#
C25
C24
HT_REFCLKP
HT_REFCLKN
NB_OSC_14.318M
E11
F11
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
1
R371
NBGFX_CLK
NBGFX_CLK#
CLK_SBLINK_BCLK
CLK_SBLINK_BCLK#
<17> LCD_DDC_CLK
<17> LCD_DDC_DAT
<18> HDMIDAT_UMA
<18> HDMICLK_UMA
<14> RS780_DFT_GPIO_0
+3VS
<14>
Strap pin
2
1
R88 10K_0402_5%
AUX_CAL
T2
T1
GFX_REFCLKP
GFX_REFCLKN
U1
U2
GPP_REFCLKP
GPP_REFCLKN
V4
V3
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
B9
A9
B8
A8
B7
A7
I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
Strap pin
A22
B22
A21
B21
B20
A20
A19
B19
LVDS_A0+ <17>
LVDS_A0- <17>
LVDS_A1+ <17>
LVDS_A1- <17>
LVDS_A2+ <17>
LVDS_A2- <17>
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
B18
A18
A17
B17
D20
D21
D18
D19
LVDS_B0+ <17>
LVDS_B0- <17>
LVDS_B1+ <17>
LVDS_B1- <17>
LVDS_B2+ <17>
LVDS_B2- <17>
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
B16
A16
D16
D17
LVDS_ACLK+ <17>
LVDS_ACLK- <17>
LVDS_BCLK+ <17>
LVDS_BCLK- <17>
VDDLTP18(NC)
VSSLTP18(NC)
A13
B13
+VDDLTP18
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
A15
B15
A14
B14
+VDDLT18
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
C14
D15
C16
C18
C20
E20
C22
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
E9
F7
G12
DAC_RSET(PWM_GPIO1)
A12
D14
B12
D8
A10
C10
C12
R66 0_0402_5%
1
2 NB_RESET#
NB_PW RGD
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
2
10K_0402_5%
<15>
<15>
C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
VDDA18PCIEPLL1
VDDA18PCIEPLL2
+1.8VS
<15>
E17
F17
F15
D7
E7
<15>
<15>
+1.1VS
GREEN
BLUE
+VDDA18PCIEPLL
2
<14,19,25,26,27,32,33> PLT_RST#
<20> NB_PWRGD
RED
<14,16> CRT_HSYNC
<14,16> CRT_VSYNC
<16> UMA_CRT_CLK
<16> UMA_CRT_DAT
+1.8VS
TV_CRMA
TV_LUMA
TV_COMPS
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
PART 3 OF 6
CRT/TVOUT
NB_LDTSTOP#
0_0402_5%
PLL PWR
LVTM
LDT_STOP#
PM
R67
<6,19>
CLOCKs
11/13 update
L3
1
2
BLM18PG121SN1D_0603
1
C173
0.1U_0402_16V4Z
C171
2.2U_0603_6.3V4Z
2
L5
1
2
BLM18PG121SN1D_0603
1
+1.8VS
C174
4.7U_0805_10V4Z
0.08A/10mil/1vias
1
R69 1
R70
+1.8VS
2
20_0402_5%
0_0402_5%
UMA_ENVDD <17>
ENBKL <33>
PA_RS780A4
placement close to NB ball
3
TMDS_HPD(NC)
HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
TESTMODE
D9
D10
HPD
1
2
D12
R77 0_0402_5%
AE8 NB_THERMAL_DA
AD8 NB_THERMAL_DC
D13
AUX_CAL(NC)
<18>
SUS_STAT_R# <14>
SUS_STAT# <20>
PAD
PAD
T49
T50
Strap pin
NB temp to SB
1
2
R80
1.8K_0402_5%
RS780M_FCBGA528
l.c
ho
Rev
0.2
f@
ai
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
11
he
2007/08/02
Issued Date
tm
Security Classification
om
of
48
U3D
U61
L2
L3
BA0
BA1
MEM_A12
MEM_A11
MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2
MEM_A1
MEM_A0
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MEM_CLKN
MEM_CLKP
K8
J8
CK
CK
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD
VDD
VDD
VDD
VDD
A1
E1
J9
M9
R1
MEM_DQ15
MEM_DQ11
MEM_DQ13
MEM_DQ12
MEM_DQ8
MEM_DQ10
MEM_DQ9
MEM_DQ14
MEM_DQ3
MEM_DQ7
MEM_DQ1
MEM_DQ6
MEM_DQ5
MEM_DQ0
MEM_DQ4
MEM_DQ2
100_0402_1%
SIDE@
R91
MEM_CKE
K2
CKE
MEM_CS#
L8
CS
MEM_WE#
K3
WE
MEM_RAS#
K7
RAS
MEM_CAS#
L7
MEM_DM0
MEM_DM1
F3
B3
MEM_ODT
CAS
LDM
UDM
VDDL
VSSDL
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
L96
1
2
SIDE@0_0603_5%
+VDDL
J1
J7
ODT
MEM_DQS_P0
MEM_DQS_N0
F7
E8
LDQS
LDQS
MEM_DQS_P1
MEM_DQS_N1
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
NC
NC
NC
NC
NC
NC
+MEM_VREF
MEM_BA2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS
VSS
VSS
VSS
VSS
A3
E3
J3
N1
P9
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
MEM_BA0
MEM_BA1
MEM_BA2
AD16
AE17
AD17
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT
W12
Y12
AD18
AB13
AB18
V14
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
MEM_CLKP
MEM_CLKN
K9
PAR 4 OF 6
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
2
R92
2
R93
V15
W14
MEM_COMP_P
1
SIDE@40.2_0402_1%
MEM_COMP_N
1
SIDE@40.2_0402_1%
AE12
AD12
SBD_MEM/DVO_I/F
MEM_BA0
MEM_BA1
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
Y17
W18
AD20
AE21
MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
W17
AE19
MEM_DM0
MEM_DM1
IOPLLVDD18(NC)
IOPLLVDD(NC)
AE23
AE24
IOPLLVSS(NC)
AD23
MEM_VREF(NC)
AE18
MEM_CKP(NC)
MEM_CKN(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
+NB_IOPLLVDD
1
+MEM_VREF1
1
2
BLM18PG121SN1D_0603
C181
2.2U_0603_6.3V4Z
SIDE@
RS780M_FCBGA528
+1.8VS
L12
1
2
BLM18PG121SN1D_0603
+1.8V_IOPLLVDD
L13
+1.1VS
1
1
C182
0.1U_0402_16V4Z
2
SIDE@
C183
2.2U_0603_6.3V4Z
SIDE@
+1.8V_MEM_VDDQ
09/19 update
2
C184
SIDE@1U_0603_10V6K
09/19 update
Del SI3456 and MEM related Pull-high.
HY5PS561621AFP-25_FBGA84
SIDE@
1
C203
SIDE@
2
22U_0805_6.3V6M
1
C202
SIDE@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SIDE@
C201
1U_0402_6.3V4Z
SIDE@
C607
C608
2
1
1K_0402_1%
SIDE@
2
SIDE@
R99
SIDE@
0.1U_0402_16V4Z
10/8 update
+1.8VS
L15
+MEM_VREF1
C200
1K_0402_1%
SIDE@
C199
0.1U_0402_16V4Z
R98
1
2
+MEM_VREF
+1.8V_MEM_VDDQ
SIDE@
1U_0402_6.3V4Z
2
R97
1
10/8 update
1K_0402_1%
SIDE@
0.1U_0402_16V4Z
1
SIDE@
C196
+1.8V_MEM_VDDQ
1K_0402_1%
C195
1
SIDE@
0.1U_0402_16V4Z
R96
1
2
+1.8V_MEM_VDDQ
1
SIDE@
2
0_0805_5%
SIDE@
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
E
12
of
48
U3F
0.6A/50mil/4vias
2A
4.7U_0805_10V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
L22
0.25A/30mil/2vias
2A
+1.8VS
+VDDA18PCIE
FBMA-L11-201209-221LMA30T_0805
C235
4.7U_0805_10V4Z
1
C246
1
C236
1
C237
1
C238
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
1
C239
4.7U_0805_10V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
F9
G9
AE11
AD11
+1.8VS
+1.8VS
3
C251
1U_0402_6.3V4Z
2 +1.8V_VDD_SP
0_0603_5%
1
R1051
11/13 update
+1.8VS
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD33_1(NC)
VDD33_2(NC)
AE10
AA11
Y11
AD10
AB10
AC10
H11
H12
RS780M_FCBGA528
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
L20 1
2
FBMA-L11-201209-221LMA30T_0805
L21 1
2
FBMA-L11-201209-221LMA30T_0805
+1.1VS
+NB_VDDC
7A/280mil/16vias VDD_CORE=5A
330U_D2E_2.5VM_R15
C245
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
C233
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
10U_0805_10V4Z
1
C229
C232
1
C228
10U_0805_10V4Z
1
C227
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C244
1
C226
2
2
2
2
1
1
0.1U_0402_16V4Z
1
1
1
1
2
2
C231
L95
C225
2
1
@ FBMA-L11-201209-221LMA30T_0805
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
C220
C219
C222
C221
C224
C223
0.1U_0402_16V4Z
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
10U_0805_10V4Z
C212
C230
+VDDHTTX
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
10U_0805_10V4Z
C211
0.1U_0402_16V4Z
0.5A/50mil/4vias
L
2A
H18
G19
F20
E21
D22
B23
A23
+1.1VS
+VDDA11PCIE
C243
0.1U_0402_16V4Z
PART 5/6
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
0.1U_0402_16V4Z
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
C242
C216
2
2
2
0.1U_0402_16V4Z
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
0.1U_0402_16V4Z
0.45A/40mil/3vias
J17
K16
L16
M16
P16
R16
T16
L17
1
2
FBMA-L11-201209-221LMA30T_0805
0.7A/60mil/4vias
VDDA_12=2.5A
C241
U3E
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C240
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
1
1 C217 1
1
C214
C218
C215
4.7U_0805_10V4Z
+1.35VS
2
2
0.1U_0402_16V4Z
+VDDHTRX
2A
L19
2
1
FBMA-L11-201209-221LMA30T_0805
C207
0.1U_0402_16V4Z
FBMA-L11-201209-221LMA30T_0805
11/20 update
L18
2
+1.2V_HT
C247
C209
4.7U_0805_10V4Z
POWER
FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z
+VDDHT
0.1U_0402_16V4Z 0.1U_0402_16V4Z
C2081
1 C206 1
1
1
C210
0.1U_0402_16V4Z
L
L16
2
+1.1VS
C234
+
2
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
PART 6/6
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
RS780M_FCBGA528
+1.8VS
10/04 update
SIDE@0_0603_5%
+1.8V_VDD_MEM 1
2
R1054
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
GROUND
0.15A/30mil/2vias
C249
C248
C597
C598
C599
2
2
2
2
2
1
1
1
1
1
SIDE@4.7U_0805_10V4Z
SIDE@0.1U_0402_16V4Z
SIDE@0.1U_0402_16V4Z
SIDE@0.1U_0402_16V4Z
SIDE@0.1U_0402_16V4Z
3
+3VS
C252
1U_0402_6.3V4Z
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
2
C250
C253
GND
NC
R1015
1K_0402_1%
VREF
NC
VOUT
NC
@ 10U_0805_10V4Z
VIN
+3VS
C1064
TP
C1065
@ 1U_0603_10V6K
@ G2992F1U_SO8
+VREF1.35V
+1.35VS
C1067
@ 10U_0805_10V4Z
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
Title
ai
2007/08/02
Issued Date
tm
Security Classification
l.c
@ 0.1U_0402_16V7K
11/20 update
om
ho
C1068
@ 0.1U_0402_16V7K
C1066
Rev
0.2
f@
@ 3K_0402_5%
in
2
G
Sheet
E
xa
10/8 update
2
@ 0_0402_5%
1
R1017
VLDT_EN#
<36>
13
he
R1016
1
Q163
@ 2N7002_SOT23-3
of
48
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
2
R101
2
R102
CRT_VSYNC
1
1K_0402_5%
1
@ 1K_0402_5%
+3VS
11/28 update
11/28 update
DFT_GPIO1: LOAD_EEPROM_STRAPS
<11>
1
@ R104
AUX_CAL
D4
2
SUS_STAT_R#
2
150_0402_1%
@ CH751H-40PT_SOD323-2
1
PLT_RST#
RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.
DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb
<11>
RS780_DFT_GPIO_0
2
@ R105
1
1K_0402_5%
2
1
R107 SIDE@3K_0402_5%
CRT_HSYNC
10/09 update
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
14
of
48
+3VS_CLK
+3VS
R167
1
2
0_0805_5%
+VDDCLK_IO
+1.2V_HT
R168
1
2
0_0805_5%
0.1U_0402_16V4Z
1
C452
10U_0805_10V4Z
0.1U_0402_16V4Z
1
C453
2
C454
C455
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C456
C457
2
0.1U_0402_16V4Z
1
C444
10U_0805_10V4Z
C445
0.1U_0402_16V4Z
C446
0.1U_0402_16V4Z
C447
0.1U_0402_16V4Z
C448
0.1U_0402_16V4Z
C449
0.1U_0402_16V4Z
1
@ C451
C450
0.1U_0402_16V4Z
1U_0402_6.3V4Z
2
1
C458
C459
C460
C461
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
22P_0402_50V8J
2
22P_0402_50V8J
09/29 update
U10
GND
<8,9,20,30>
<8,9,20,30>
SMB_CK_CLK0
SMB_CK_DAT0
+3VS_CLK
PA_RS7X0A1
<11>
SB LINK <11>
CLK_SBLINK_BCLK#
CLK_SBLINK_BCLK
+VDDCLK_IO
<26> CLK_PCIE_MCARD1#
<26> CLK_PCIE_MCARD1
<26> CLK_PCIE_MCARD2#
MiniCard_2 <26> CLK_PCIE_MCARD2
MiniCard_1
1.1V 200R/100R
2
+3VS_CLK
8.2K_0402_5%
@ 5P_0402_50V8C
CLK_CPU_BCLK
2
0_0402_1%
2
0_0402_1%
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
CLK_CPU_BCLK#
+3VS_CLK
+VDDCLK_IO
CLKREQ_NCARD#
CLKREQ_MCARD2#
CLKREQ_NCARD# <26>
CLKREQ_MCARD2# <26>
+3VS_CLK
CLK_SBSRC_BCLK <19>
CLK_SBSRC_BCLK# <19>SB
+3VS_CLK
CLKREQ_MCARD1#
CLKREQ4
1
2
R372
10K_0402_5%
CLKREQ_MCARD1#
+3VS_CLK
SRC
PA_RS7X0A1
<26>
+3VS_CLK
+VDDCLK_IO
3
SLG8SP626VTR_QFN72_10x10
+3VS_CLK
+VDDCLK_IO
CLKREQ4
NBGFX_CLK <11>
NBGFX_CLK# <11>
NB GFX
CLK_PCIE_MCARD0 <27>
CLK_PCIE_MCARD0# <27>
CLKREQ_LAN# <25>
CLK_PCIE_LAN <25>
CLK_PCIE_LAN# <25>
CLKREQ_LAN#
CLK_PCIE_NCARD <26>
CLK_PCIE_NCARD# <26>
27M_SEL
SEL_SATA
0
1 *
* default
+3VS_CLK
Card Reader
GLAN
NB CLOCKS
New Card
RX780
RS780
HT_REFCLKP
100M DIFF
100M DIFF
100M DIFF
100M DIFF
REFCLK_N
14M SE (1.8V)
NC
14M SE (1.1V)
vref
GFX_REFCLK
100M DIFF
100M DIFF(IN/OUT)*
REFCLK_P
27M_SEL
configure as normal SRC(SRC_6) output
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
@ 8.2K_0402_5%
11/28 update
HT_REFCLKN
1
Clock generator
Size Document Number
Custom
LA-4111P
Date:
l.c
ai
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Rev
0.2
f@
2008/08/02
Deciphered Date
in
2007/08/02
Issued Date
tm
Security Classification
0*
configure as differential 100MHz output
* default
Sheet
E
xa
1
NB_OSC_14.318M
om
15
he
1
R324
1
R325
1
R326
1
R1039
1
R1045
CLKREQ_MCARD2#
CLKREQ_LAN#
R180
8.2K_0402_5%
1
R181
8.2K_0402_5%
<6>
2
1
2
SEL_SATA
@ 5P_0402_50V8C
CPU
10/03 update
CLKREQ_MCARD1#
+3VS_CLK
C1074
@ 5P_0402_50V8C
C1075
@ R179
8.2K_0402_5%
<6>
CLKREQ_NCARD#
+3VS_CLK
R186
@ 261_0402_1%
09/21 update
VDD_CPU
VDD_CPU_I/O
VSS_CPU
CLKREQ_1#
CLKREQ_2#
VDD_A
VSS_A
VSS_SATA
SRC_6/SATA
SRC_6#/SATA#
VDD_SATA
CLKREQ_3#
CLKREQ_4#
SB_SRC_SLOW#
SB_SRC_0
SB_SRC_0#
VDD_SB_SRC
VDD_SB_SRC_IO
CLK_14M_SIO
CLK_14M_SIO <32>
CLK_NBHT <11>
CLK_NBHT# <11> NB
1
R946
CLK_CPU_BCLK#_R 1
R945
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1.8V 75R/100R
RS780
C1076
CLK_CPU_BCLK_R
SCL
SDA
VDD_DOT
SRC_7#/27M
SRC_7/27M_SS
VSS_DOT
SRC_5#
SRC_5
SRC_4#
SRC_4
VSS_SRC
VDD_SRC_IO
SRC_3#
SRC_3
SRC_2#
SRC_2
VDD_SRC
VDD_SRC_IO
RX780
1
R174
<11>
2
100_0402_1%
R220 33_0402_5%
1
2
NB_OSC_14.318M
OSC_14M_NB
<20>
NB_OSC_14.318M
1
R380
VSS_SRC
SRC_1#
SRC_1
SRC_0#
SRC_0
CLKREQ_0#
ATIGCLK_2#
ATIGCLK_2
VSS_ATIG
VDD_ATIG_IO
VDD_ATIG
ATIGCLK_1#
ATIGCLK_1
ATIGCLK_0#
ATIGCLK_0
SB_SRC_1#
SB_SRC_1
VSS_SB_SRC
+3VS_CLK
+VDDCLK_IO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK_XTAL_OUT
CLK_XTAL_IN
14.31818MHZ_20P_6X1430004201
1
C465
2
200_0402_1%
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
CLK_48M_USB
VSS_48
48MHz_0
48MHz_1
VDD_48
XTAL_OUT
XTAL_IN
VSS_REF
REF_0/SEL_HTT66
REF_1/SEL_SATA
REF_2/SEL_27
VDD_REF
VDD_HTT
HTT_0/66M_0
HTT_0#/66M_1
VSS_HTT
PD#
CPU_K8_0
CPU_K8_0#
C464
73
CLK_48M_USB_R
Y2
NB_OSC_14.318M_R
SEL_SATA
27M_SEL
+3VS_CLK
+3VS_CLK
CLK_XTAL_IN
R379
+3VS_CLK
CLK_XTAL_OUT
33_0402_5%
R170 1
of
48
CRT CONNECTOR
+5VS
+R_CRT_VCC
@ D35
@ D37
@ D34
+CRT_VCC
F2
D36
2
1
RB491D_SOT23 1A_6VDC_MINISMDC110
C475
0.1U_0402_16V4Z
+3VS
R211
R217
C471
2
1
C859
2
1
C469
2
C858
HSYNC
BLUE_L
1
C476
2
1
C472
2
22P_0402_50V8J
R214
2
D_DDCDATA
GREEN_L
22P_0402_50V8J
<11>
RED_L
22P_0402_50V8J
BLUE
BLUE
L47
1
2
BLM15AG121SN1D_0402
L48
1
2
BLM15AG121SN1D_0402
L49
1
2
BLM15AG121SN1D_0402
6P_0402_50V8K
GREEN
6P_0402_50V8K
GREEN
2
1
150_0402_1%
<11>
2
1
150_0402_1%
RED
2
1
150_0402_1%
RED
6P_0402_50V8K
JCRT
<11>
DAN217_SC59DAN217_SC59
DAN217_SC59
+CRT_VCC
VSYNC
D_DDCCLK
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND
16
17
GND
GND
11/14 update
Update PCB
Footprint SUYIN_070546FR015S263ZR_15P-T
: Change back
JCRT.5<->JCRT.15 ;
JCRT.14<->JCRT.4 ;
JCRT.13<->JCRT.3 ;
JCRT.12<->JCRT.2 ;
JCRT.11<->JCRT.1
CONN@ SUYIN_070546FR015S263ZR
RED_L
<35>
GREEN_L
BLUE_L
+3VS
<35>
<35>
+CRT_VCC
UMA_CRT_CLK
6.8K_0402_5%
6.8K_0402_5%
D_DDCDATA
Q10A
2N7002DW-7-F_SOT363-6
<11,14>
D_DDCDATA
CRT_HSYNC
<35>
5
1
A
D_HSYNC
R240 1
HSYNC
2 0_0603_5%
U14
SN74AHCT1G125GW_SOT353-5
<35>
3
<11>
<35>
D_HSYNC
UMA_CRT_DAT
R218
P
OE#
R100
1
2
C473
0.1U_0402_16V4Z
R238
4.7K_0402_5%
2
<11>
D_VSYNC
+CRT_VCC
R237
4.7K_0402_5%
CRT_VSYNC
2 470P_0402_50V8J
11/07 update
Y
D_ VSYNC
R241 1
VSYNC
2 0_0603_5%
U13
SN74AHCT1G125GW_SOT353-5
1
@ C474
@ C470
10P_0402_50V8J
<11,14>
@ C856
470P_0402_50V8J
1
2
@ C477
0.1U_0402_16V4Z
2 A
5
1
<35>
@ C857
D_DDCCLK
10P_0402_50V8J
P
OE#
D_DDCCLK
4
3
Q10B
2N7002DW-7-F_SOT363-6
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
16
of
48
10U_0805_10V4Z
G2
C720
ACES_88231-06001
CONN@
10U_0805_10V4Z
L
D52
+USB_CAM
USB20N5
09/26 update
VIN
IO1
IO2 GND
VIN
VOUT
GND
EN
R891
@ 215K_0402_1%
2
C719
Place R1027~R1030
close to JLVDS
R1027
USB20_P5 1
USB20_N51
R1028
@ 0_0402_5%
2 USB20P5
2 USB20N5
@ 0_0402_5%
R1029
DMIC_DAT1
DMIC_CLK1
R1030
@ 0_0402_5%
2 DMICDAT
2 DMICCLK
@ 0_0402_5%
DMICCLK
DMICDAT
BP
@ C1072
U54
PJP4
PAD-OPEN 2x2m
G1
RT9193-39GB_SOT23-5
C718
0.1U_0402_16V4Z
R1013
R892
10U_0805_10V4Z
@ 100K_0402_1%
0_0402_5%
Close to JLVDS
D22
Close to JP7
1
2
3
4
5
6
+USB_CAM
1
2
3
4
5
6
USB20P5
USB20N5
+USB_CAM
+5VALW
11/13 update
JP7
1
@ R1014
1
2
0_0402_5%
+USB_CAM
CAM_SHDN#
<21>
USB20_N5
USB20P5
VIN
IO1
IO2 GND
USB20_P5
@ PRTR5V0U2X_SOT143-4
@ PRTR5V0U2X_SOT143-4
11/09 update
80mil
UMA_ENVDD
B+
L44
1
2
FBMA-L11-201209-221LMA30T_0805
LVDS_A1-
C1057
2 @ 10P_0402_50V8J
LVDS_A1+
LVDS_A0-
C1058
2 @ 10P_0402_50V8J
LVDS_A0+
2 @ 10P_0402_50V8J
LVDS_ACLK+
LVDS_B2-
C1060
2 @ 10P_0402_50V8J
LVDS_B2+
LVDS_B1-
C1061
2 @ 10P_0402_50V8J
LVDS_B1+
LVDS_B0-
C1062
2 @ 10P_0402_50V8J
LVDS_B0+
LVDS_BCLK- C1063
2 @ 10P_0402_50V8J
LVDS_BCLK+
+3VS
C481
LVDS_ACLK- C1059
<20>
<20>
680P_0402_50V7K
09/19 update
80mil
11/07 update
+LCDVDD
1
C487
4.7U_0805_10V4Z
C491
0.1U_0402_16V4Z
1
Q45B
2N7002DW-7-F_SOT363-6
C480
LVDS CONN
680P_0402_50V7K
USB20_P5
USB20_N5
<11> LVDS_BCLK+
<11> LVDS_BCLK<11> LVDS_B0+
<11> LVDS_B0<11> LVDS_B1+
<11> LVDS_B1<11> LVDS_B2+
<11> LVDS_B2-
JLVDS
USB20_P5
USB20_N5
LVDS_BCLK+
LVDS_BCLKLVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2-
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
LVDS_A2LVDS_A2+
LVDS_A1LVDS_A1+
LVDS_A0LVDS_A0+
LVDS_ACLKLVDS_ACLK+
LVDS_A2- <11>
LVDS_A2+ <11>
LVDS_A1- <11>
LVDS_A1+ <11>
LVDS_A0- <11>
LVDS_A0+ <11>
LVDS_ACLK- <11>
LVDS_ACLK+ <11>
DMIC_DAT
DMIC_CLK
DMIC_DAT
DMIC_CLK
11/07 update
INV_PWM
BKOFF#
DAC_BRIG
9/20 SP02000EA00/SP02000BW00
<28>
<28>
+5VS
R491
1
2 200_0805_5%
INV_PWM <33>
BKOFF# <33>
DAC_BRIG <33>
LCD_DDC_CLK
LCD_DDC_DAT
ACES_88242-4001
CONN@
+USB_CAM
LCD_DDC_CLK
LCD_DDC_DAT
+3VS
10/08 update
<11>
<11>
2
@
C483
680P_0402_50V7K
LVDS_A2+
R276
2.2K_0402_5%
C482
680P_0402_50V7K
2 @ 10P_0402_50V8J
<11>
C867
680P_0402_50V7K
2
1
1
INVPWR_B+
C866
680P_0402_50V7K
2
1
C1056
LVDS_A2-
C863
1000P_0402_50V7K
R222
1
2
100K_0402_5%
680P_0402_50V7K
C479
SI2301BDS-T1-E3_SOT23-3
Q43
Q45A
2N7002DW-7-F_SOT363-6
+LCDVDD
+3VS
R224
1M_0402_5%
6 2
R225
470_0805_5%
+5VALW
+LCDVDD
BKOFF#
1
@ 4.7K_0402_5%
2
R483
LCD_DDC_CLK 1
4.7K_0402_5%
2
R274
LCD_DDC_DAT 1
4.7K_0402_5%
2
R275
Rev
0.2
f@
l.c
ho
ai
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
17
he
2007/08/02
Issued Date
tm
Security Classification
om
of
48
+HDMI_5V_OUT
+3VS
R176
4.7K_0402_5%
HDMI_HPD
2
2.2K_0402_5%
Y
HPD
<11>
R628
100K_0402_5%
U39
SN74AHCT1G125GW_SOT353-5
<11>
HDMIDAT_UMA
<11>
HDMICLK_UMA
R236
6.8K_0402_5%
HDMI_SDATA
1
6
Q134A
2N7002DW-7-F_SOT363-6
+3VS
R210
6.8K_0402_5%
1
R615
C850
0.1U_0402_16V4Z
HDMI_SCLK
4
3
Q134B
2N7002DW-7-F_SOT363-6
P
OE#
0.1U_0402_16V4Z
5
1
+HDMI_5V_OUT
C851
R209
4.7K_0402_5%
2
C:Chg. PN to SB770020010.
11/13 update
MP:Update D10 to meet HDMI.
HDMI_CLK+
R112
2
0_0402_5%
HDMI_R_CK+
D10
2
+5VS
L85
1
+HDMI_5V_OUT
RB491D_SOT23
1
C507 1
C508 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_CLKHDMI_CLK+
<10> TMDS_B_DATA0#
<10> TMDS_B_DATA0
C655 1
C675 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX0HDMI_TX0+
<10> TMDS_B_DATA1#
<10> TMDS_B_DATA1
C804 1
C827 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX1HDMI_TX1+
C852 1
C853 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_TX2HDMI_TX2+
<10>
<10>
TMDS_B_CLK#
TMDS_B_CLK
HDMI_CLK-
@ WCM-2012-900T_4P
1
2
R113
0_0402_5%
HDMI_TX0+
R115
<10>
<10>
TMDS_B_DATA2#
TMDS_B_DATA2
HDMI_TX1HDMI_TX1+
1
1
R297
750_0402_1%
R139
750_0402_1%
R141
750_0402_1%
@ WCM-2012-900T_4P
1
2
R116
0_0402_5%
2
0_0402_5%
@ WCM-2012-900T_4P
1
2
R118
0_0402_5%
Q162B
2N7002DW-7-F_SOT363-6
HDMI_TX2+
R119
2
0_0402_5%
0.1U_0402_16V4Z
HDMI Connector
+HDMI_5V_OUT
JHDMI
18 +5V
16 SDA
15 SCL
19 HP_DET
HDMI_R_D0-
HDMI_R_D1+
HDMI_SDATA
HDMI_SCLK
HDMI_HPD
CEC
Reserved
13
14
HDMI_R_CKHDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+
GND
GND
GND
GND
GND
GND
GND
GND
DDC/CEC_GND
2
5
8
11
20
21
22
23
17
12
10
9
7
6
4
3
1
CKCK+
D0D0+
D1D1+
D2D2+
CONN@ SUYIN_100042MR019S153ZL
HDMI_R_D1-
11/14 update
Q136A
Q136B
Q162A
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
1
L87
R117
HDMI_TX1-
11/13 update
HDMI_TX1+
+5VS
6
+5VS
2
2
R304
750_0402_1%
C468
HDMI_R_D0+
1
1
R172
750_0402_1%
+5VS
6
+5VS
R173
750_0402_1%
1
1
2
2
R307
750_0402_1%
1
2
R315
750_0402_1%
HDMI_TX2HDMI_TX2+
2
2
HDMI_TX0HDMI_TX0+
2
1
HDMI_CLKHDMI_CLK+
2
0_0402_5%
L86
HDMI_TX03
HDMI_R_CK-
HDMI_R_D2+
L88
HDMI_TX2-
@ WCM-2012-900T_4P
1
2
R120
0_0402_5%
HDMI_R_D2-
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
18
of
48
U22
U21
U19
V19
R20
R21
R18
R17
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
R305
R306
+PCIE_VDDR
L53
1
2
BLM18PG121SN1D_0603
1
C504
10U_0805_10V4Z
1 562_0402_1%
1 2.05K_0402_1%
2
2
+SB_PCIEVDD
T25
T24
PCIE_CALRP
PCIE_CALRN
P24
PCIE_PVDD
P25
PCIE_PVSS
C505
1U_0402_6.3V4Z
Part 1 of 5
@ R314 20M_0402_5%
1
2
C643
SB_32KHI
18P_0402_50V8J
11/23 update
Y3
R389
20M_0402_5%
NC
OSC
NC
K23
K22
NB_DISP_CLKP
NB_DISP_CLKN
M24
M25
NB_HT_CLKP
NB_HT_CLKN
P17
M18
CPU_HT_CLKP
CPU_HT_CLKN
M23
M22
SLT_GFX_CLKP
SLT_GFX_CLKN
J19
J18
GPP_CLK0P
GPP_CLK0N
L20
L19
GPP_CLK1P
GPP_CLK1N
M19
M20
GPP_CLK2P
GPP_CLK2N
N22
P22
GPP_CLK3P
GPP_CLK3N
L18
25M_48M_66M_OSC
J21
PCI INTERFACE
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
25M_X1
32.768KHZ_12.5PF_Q13MC14610050_10PPM
C652
11/29 update
OSC
N25
N24
CLOCK GENERATOR
CLK_SBSRC_BCLK
CLK_SBSRC_BCLK#
SB_32KHO
J20
N1
25M_X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
X1
SB_32KHO
B3
X2
09/11 update
+1.8VS
2
R318
1 CPU_LDT_REQ#
@ 10K_0402_5%
+3VS
2
R319
H_PROCHOT#
1
10K_0402_5%
11/13 update
CPU_LDT_REQ#
H_PROCHOT#
H_PWRGD
F23
F24
F22
G25
G24
ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
<6>
H_PWRGD_CPU
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ
2 @ 22_0402_5%CLK_PCI_SIO
H_PWRGD
0_0402_5%
CLK_PCI_SIO2
U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
<23>
<23>
<23>
<23>
<23>
<23>
PCI_SERR#
PAD
T15
PAD
PAD
T16
T17
AD3
AC4
AE2
AE3 PCI_PIRQH#
<33>
LPCCLK1
R308 1
22_0402_5%
R967 2
1 0_0402_5%
ACCEL_INT
<30>
STRAP PIN
EC & Debug
C3
C2
B2
RTC_CLK
+SB_VBAT
ZZZ
STRAP PIN
<23>
+SB_VBAT
09/29 update
+RTCVCC_R
R316
120_0402_5%
1
2
218S7EALA11FG_BGA528_SB700
1
C509
1
C510
2
1U_0402_6.3V4Z
+RTCVCC
R876
1
3
1
2
W=20mils
1K_0402_5%
DAN202U_SC70
2007/08/02
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
1
2
GND
GND
CONN@ ACES_85205-02001
2008/08/02
Deciphered Date
1
2
3
4
+RTCBATT_R
9/20 SP020008T00
09/29 update
Security Classification
JBATT1
W=20mils
J1
@ JUMP_43X39
+RTCBATT
D42
+3VL
R317
120_0402_5%
1
2
W=20mils
0.1U_0402_16V4Z
CLK_PCI_SIO
11/22 update
22_0402_5%
09/29 update
2 CLK_PCI_EC
G22 CLK_PCI_EC_R R302 1
CLK_PCI_EC <23,33>
E22 LPCCLK1
LPCCLK1 <23>
H24
LPC_AD0 <32,33>
H23
LPC_AD1 <32,33>
J25
LPC_AD2 <32,33>
J24
LPC_AD3 <32,33>
H25
LPC_FRAME# <32,33>
PAD T18
H22
AB8
11/13 update
LPC_DRQ# <32>
AD7
V15
SIRQ <32,33>
<32>
CLK_PCI_SIO <23,32>
PCI_CLK4 <23>
PCI_CLK5 <23>
PCB-MB
RTCCLK
INTRUDER_ALERT#
VBAT
R311
1
2 @ 22_0402_5%CLK_PCI_SIO2
R301 1
RTC
<6,11> CPU_LDT_REQ#
<6> H_PROCHOT#
H_PWRGD
<6,11> LDT_STOP#
<6> LDT_RST#
L PC
A3
CPU
SB_32KHI
RTC XTAL
18P_0402_50V8J
Close to SB
R303 1
Close to SB
<15>
<15>
PCIRST#
CLK_PCI_SIO_R
Title
om
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
l.c
V23
V22
V24
V25
U25
U24
T23
T22
ai
SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C
tm
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
<23>
11/09 update
SB700-PCIE/PCI/ACPI/LPC/RTC
ho
+1.2V_HT
2
2
2
2
2
2
2
2
P4
P3
P1
P2
T4
T3
Rev
0.2
f@
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
1
1
1
1
1
1
1
1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41
in
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
C492
C493
C494
C495
C496
C497
C498
C499
A_RST#
Sheet
E
xa
1
33_0402_5%
11/30 update
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
SB700
N2
@ NC7SZ08P5X_NL_SC70-5
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
PCICLK2
U15A
NB_RST#_R
19
he
2 NB_RST#_R
@ 8.2K_0402_5%
1
R300
<11,14,25,26,27,32,33>
PLT_RST#
PCI CLKS
4PLT_RST#
U16
2
R312
1
NB_RST#_R
@ 0.1U_0402_16V4Z
2
+3VALW
C506
of
48
<11>
R1052
NB_PWRGD
1 NBPWRGD
0_0402_5%
R1053 2
1
@ 100_0402_5%
U15D
11/13 update
+3VALW
1
R320
1
R321
1
R322
2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%
<33>
<33>
<33>
<33>
SB_TEST2
SB_TEST1
GATEA20
KB_RST#
EC_SCI#
EC_SMI#
11/13 update
SB_TEST0
10/08 update
<6>
+3VS
R328
2 2.2K_0402_5%
SMB_CK_CLK0
R329
2 2.2K_0402_5%
SMB_CK_DAT0
<33>
H_THERMTRIP#
EC_RSMRST#
EC_RSMRST#
D3
+3VALW
R331
2 2.2K_0402_5%
SMB_CK_CLK1
R332
2 2.2K_0402_5%
SMB_CK_DAT1
<28> SB_SPKR
<8,9,15,30> SMB_CK_CLK0
<8,9,15,30> SMB_CK_DAT0
<26> SMB_CK_CLK1
<26> SMB_CK_DAT1
+3VS
R83
SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1
+3VALW
SB_GPIO5
1
2
@ 10K_0402_5%
R540
10K_0402_5%
G8
USB_FSD13P
USB_FSD13N
E6
E7
USB_FSD12P
USB_FSD12N
F7
E8
USB MISC
SUS_STAT#
C8
USB_RCOMP
USB 1.1
2
4.7K_0402_5%
USBCLK/14M_25M_48M_OSC
AE18
AD18
AA19
W17
V17
W20
W21
AA18
W18
K1
K2
AA20
Y18
C1
Y19
G5
PCIE_WAKE#
1
0_0402_5%
1
@ 0_0402_5%
11/13 update
11/13 update
<28>
<34>
<34>
<28>
<28>
<34>
<34>
<28>
<28>
<34>
HDA_BITCLK_CODEC
HDA_BITCLK_MDC
HDA_SDOUT_MDC
HDA_SDOUT_CODEC
HDA_SDIN0
HDA_SDIN1
HDA_SYNC_MDC
HDA_SYNC_CODEC
HDA_RST#_CODEC
HDA_RST#_MDC
<23,33>
HDARST#
R333
R334
R335
R336
<33> EC_LID_OUT#
<26> EXP_CPPE#
<27> CR_CPPE#
33_0402_5%
1
2
33_0402_5%
1
2
33_0402_5%
1
2
33_0402_5%
1
2
R337
R338
33_0402_5%
33_0402_5%
1
1
2
2
R339
R340
33_0402_5%
33_0402_5%
1
1
2
2
R82
EXP_CPPE#
1
CR_CPPE#
1
R81
HDA_BITCLK
B9
B8
A8
0_0402_5%
A9
E5
2
F8
2
D3E@ 0_0402_5% E4
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
HDA_SYNC
HDARST#
M1
M2
J7
J8
L8
M3
L6
M4
L5
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#
INTEGRATED uC
MINI_PCIE_WAKE#
2
R993
2
R994
HD AUDIO
<26>
LAN_PCIE_WAKE#
PAD T41
STRAP PIN
H19
H20
H21
F25
IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3
D22
E24
E25
D23
IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7
INTEGRATED uC
<25>
USB OC
11/16 update
<15>
2
R323
09/04 update
Touch Screen (delete)
USB_HSD11P
USB_HSD11N
H11
J10
USB_HSD10P
USB_HSD10N
E11
F11
USB20_P10
USB20_N10
USB_HSD9P
USB_HSD9N
A11
B11
USB_HSD8P
USB_HSD8N
C10
D10
USB20_P8
USB20_N8
USB_HSD7P
USB_HSD7N
G11
H12
USB20_P7
USB20_N7
USB_HSD6P
USB_HSD6N
E12
E14
USB20_P6
USB20_N6
USB_HSD5P
USB_HSD5N
C12
D12
USB20_P5
USB20_N5
USB_HSD4P
USB_HSD4N
B12
A12
USB_HSD3P
USB_HSD3N
G12
G14
USB20_P3
USB20_N3
USB_HSD2P
USB_HSD2N
H14
H15
USB20_P2
USB20_N2
USB_HSD1P
USB_HSD1N
A13
B13
USB20_P1
USB20_N1
USB_HSD0P
USB_HSD0N
B14
A14
USB20_P0
USB20_N0
IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17
A18
B18
F21
D21
F19
E20
E21
E19
D19
E18
IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25
G20
G21
D25
D24
C25
C24
B25
C23
IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41
B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18
RSMRST#
SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT1/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SMARTVOLT2/SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#
CLK_48M_USB
USB_RCOMP 1
11.8K_0402_1%
USB20_P11
USB20_N11
USB 2.0
1
R388
Part 4 of 5
SB700
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD
GPIO
demo circuit
<33> SLP_S3#
<33> SLP_S5#
<33> PWRBTN_OUT#
<6,33,43> SB_PWRGD
<11> SUS_STAT#
+3VS
E1
E2
LID use RI#
H7
F5
G1
H2
H1
SUS_STAT#
K3
SB_TEST2
H5
SB_TEST1
H4
SB_TEST0
H3
Y15
W15
K4
K24
F1
PAD T19
J2
PCIE_WAKE#
H6
F2
H_THERMTRIP# J6
NBPWRGD
W14
USB20_P11
USB20_N11
<26>
<26>
USB20_P10
USB20_N10
<26>
<26>
USB-10 MiniCard(TV)
USB-9 Card Reader (delete)
USB20_P8
USB20_N8
<26>
<26>
USB-8 MiniCard(WWAN)
USB20_P7
USB20_N7
<31>
<31>
USB-7 Fingerprint
USB20_P6
USB20_N6
<31>
<31>
USB-6 Bluetooth
USB20_P5
USB20_N5
<17>
<17>
<35>
<35>
USB-3 Dock
USB20_P2
USB20_N2
<31>
<31>
USB20_P1
USB20_N1
<31>
<31>
USB20_P0
USB20_N0
<31>
<31>
GPIO16
GPIO17
STRAP PIN
STRAP PIN
<23>
<23>
218S7EALA11FG_BGA528_SB700
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
20
of
48
Y4
R341
10M_0402_5%
2
25MHz_20pF_6X25000017
10P_0402_50V8J 2
SATA_X1
1 C516
1
10P_0402_50V8J 2
1 C517
SATA_X2
10/09 update
U15B
<24>
<24>
SATA_TXP1
SATA_TXN1
C514
C515
1
1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
<31>
<31>
SATA_TXP2
SATA_TXN2
C520
C521
1
1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
<24>
<24>
<24>
<24>
11/05 update
<24>
<24>
<31>
<31>
C518
C519
SATA_TXP3
SATA_TXN3
SATA_STX_DRX_P0
SATA_STX_DRX_N0
SATA_RXN0_C
SATA_RXP0_C
SATA_STX_DRX_P1
SATA_STX_DRX_N1
SATA_RXN1_C
SATA_RXP1_C
SATA_STX_DRX_P2
SATA_STX_DRX_N2
SATA_RXN2_C
SATA_RXP2_C
SATA_STX_DRX_P3
SATA_STX_DRX_N3
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
1
1
<24>
<24>
11/06 update
SATA_RXN3_C
SATA_RXP3_C
2
R342
11/05 update
+3VS
<34>
+1.2V_HT
R343 10K_0402_5%
1
2
L54
2
1
BLM18PG121SN1D_0603
+PLLVDD_SATA
2
C522
1U_0402_6.3V4Z
C523
1U_0402_6.3V4Z
+3VS
L55
2
1
BLM18PG121SN1D_0603
3
C524
1U_0402_6.3V4Z
SATA_TX0P
SATA_TX0N
AB10
AC10
SATA_RX0N
SATA_RX0P
AE10
AD10
SATA_TX1P
SATA_TX1N
AD11
AE11
SATA_RX1N
SATA_RX1P
AB12
AC12
SATA_TX2P
SATA_TX2N
AE12
AD12
SATA_RX2N
SATA_RX2P
AD13
AE13
SATA_TX3P
SATA_TX3N
AB14
AC14
SATA_RX3N
SATA_RX3P
AE14
AD14
SATA_TX4P
SATA_TX4N
AD15
AE15
SATA_RX4N
SATA_RX4P
AB16
AC16
SATA_TX5P
SATA_TX5N
AE16
AD16
SATA_RX5N
SATA_RX5P
SATA_CAL
1
1K_0402_1%
SATA_X1
V12
SATA_CAL
Y12
SATA_X1
SATA_X2
AA12
SATA_X2
W11
SATA_LED#
+XTLVDD_SATA
2
SB700
AD9
AE9
Part 2 of 5
ATA 66/100/133
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
PLLVDD_SATA
W12
XTLVDD_SATA
AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24
IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30
AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23
SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS1#/GPIO32
G6
D2
D1
F4
F3
LAN_RST#/GPIO13
ROM_RST#/GPIO14
U15
J1
FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49
M8
M5
M7
FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52
P5
P8
R8
TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64
C6
B6
A6
A5
B5
VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60
A4
B4
C4
D4
D5
D6
A7
B7
AVDD
F6
AVSS
G7
SATA_ACT#/GPIO67
AA11
IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#
Qimonda
Samsung
LFB_ID2
R344 1
2 1K_0402_5%
LFB_ID1
R367 1
2 1K_0402_5%
LFB_ID0
R345 1
2 1K_0402_5%
R1032
SPI ROM
1
1
HW MONITOR
C512
C513
SERIAL ATA
SATA_TXP0
SATA_TXN0
SATA PWR
<24>
<24>
+3VALW
+3VALW
11/13 update
CR_WAKE#
<27>
11/13 update
HDD_HALTLED# <34>
SB_INT_FLASH_SEL <32>
THERMAL_DC R1062
2 0_0402_5%
WLOFF# <26>
BT_COMBO_EN# <26>
WWOFF# <26>
EC_THERM# <33>
11/05 update
AC_IN_D <33>
BT_OFF <31>
CAM_SHDN# <17>
11/13 update
LFB_ID0
LFB_ID1
LFB_ID2
+SB_AVDD
1
1
2
C525
0.1U_0402_16V4Z
218S7EALA11FG_BGA528_SB700
1
2
@ 10K_0402_5%
1
2
@ 10K_0402_5%
R1033
+3VALW
L56
2
1
BLM18PG121SN1D_0603
C526
2.2U_0603_6.3V4Z
Rev
0.2
f@
l.c
ho
SB700 SATA/IDE/SPI
ai
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
21
he
2007/08/02
Issued Date
tm
Security Classification
om
of
48
11/20 update
CORE S0
PCI/GPIO I/O
2
2
2
2
2
2
2
@ 0_0805_5%
2
0_0805_5%
2
C529
C532
1
C534
1
C538
1
C537
1
C527
1
C540
1
C546
C545
C548
C551
C550
1
1
2
2
1
2
2
1
1
2
U15E
+1.2VALW
SB700
+1.2V_HT
L60
2
1
BLM18PG121SN1D_0603
+1.2V_CKVDD
+1.2V_HT
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8
AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20
A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15
AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7
A17
A24
B17
J4
J5
L1
L2
+S5_3V
S5_1.2V_1
S5_1.2V_2
G2
G4
+S5_1.2V
1
R564
1
22U_A_4VM
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
0_0805_5%
2
2
2
2
2
2
2
1
1
1
1
1
1
C556
C559
C561
C562
C563
C564
C565
+1.2VALW
L64
+1.2VALW
+1.2_USB
A10
B10
L65
1U_0402_6.3V4Z
2
0.1U_0402_16V4Z 2
0_0603_5%
1
22U_A_4VM
1U_0402_6.3V4Z 2
1U_0402_6.3V4Z 2
0_0603_5%
1 C569
1 C570
C573
C574
C575
1
1
+AVDD_USB
L66
2
1
FBMA-L11-201209-221LMA30T_0805
1
1
1
1
1
1
1
2
2
2
2
2
2
2
A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5
V5_VREF
AE7
+V5_VREF
AVDDCK_3.3V
J16
+AVDDCK_3.3V
AVDDCK_1.2V
AVDDC
1K_0402_5% 2
K17
C578
+AVDDCK_1.2V0.1U_0402_16V4Z
E9
+AVDDC
C579
1U_0603_10V4Z
1
L67
2
1
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z 2
0.1U_0402_16V4Z
218S7EALA11FG_BGA528_SB700
+AVDDCK_1.2V
C585
C586
+AVDDCK_3.3V
0.1U_0402_16V4Z
+3VS
H18
J17
J22
K25
M16
M17
M21
P16
F9
PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21
Part 5 of 5
AVSSCK
A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24
P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
3
L17
218S7EALA11FG_BGA528_SB700
+1.2V_HT
C587
C588
L69
2
1
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z 2
+5VS
+3VALW
L68
2
1
BLM18PG121SN1D_0603
0.1U_0402_16V4Z
1 R346
CH751H-40PT_SOD323-2
2.2U_0603_6.3V4Z 2
D14
GROUND
AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7
+3VALW
0.1A/30mil/2vias ?
+
USB_PHY_1.2V_1
USB_PHY_1.2V_2
<1.25A/50mil/4vias?
+3VALW
0.3A/30mil/2vias
C576
C577
C580
C581
C583
C582
C584
1
1
1
1
1
22U_A_4VM
2 1U_0805_16V7K
2 1U_0805_16V7K
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
PLL
AA14
AB18
AA15
AA17
AC18
AD17
AE17
C566
C567
C568
C571
C572
1
22U_A_4VM
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.2V_SATA
L63
2
1
FBMA-L11-201209-221LMA30T_0805
<1.25A/50mil/4vias
P18
P19
P20
P21
R22
R24
R25
1
22U_A_4VM
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
1
1
1
1
1
1
L21
L22
L24
L25
1
R592
1
R593
POWER
CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4
+1.2V_SB_CORE
+PCIE_VDDR
L61
2
1
FBMA-L11-201209-221LMA30T_0805
C552
C553
C555
C554
C558
C557
C560
+1.2V_HT
1
@ 22U_A_4VM
2 @ 1U_0402_6.3V4Z
2 @ 1U_0402_6.3V4Z
2 @ 1U_0402_6.3V4Z
1
1
1
0.8A/50mil/4vias
+3.3V_SB_IDE
USB I/O
+1.2V_HT
VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4
0.45A/30mil/3vias
C543
C544
C547
C536
Y20
AA21
AA22
AE25
Part 3 of 5
CLKGEN I/O
@ 0_0603_5%
1
2
L15
M12
M14
N13
P12
P14
R11
R15
T16
3.3V_S5 I/O
R12
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
CORE S5
11/20 update
2
2
2
2
2
2
2
2
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
IDE/FLSH I/O
1
1
1
1
1
1
1
1
1
22U_A_4VM
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SB700
L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21
A-LINK I/O
C528
C531
C530
C533
C549
C535
C539
C541
C542
+3VS
0.45A/40mil/3vias ?
SATA I/O
+3VS
0.6A/50mil/4vias
U15C
+3VS
1 C589
1 C590
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
22
of
48
REQUIRED STRAPS
PCI_CLK3
PCI_CLK4
PCI_CLK5
AZ_RST_CD#
BOOTFAIL
TIMER
ENABLED
USE
DEBUG
STRAPS
RESERVED
RESERVED
ENABLE PCI
MEM BOOT
LPC_CLK1
RTC_CLK
LPC_CLK0
CLKGEN
ENABLED
INTERNAL
RTC
EC
ENABLED
GP17
BOOTFAIL
TIMER
DISABLED
IGNORE
DEBUG
STRAPS
DISABLE PCI
MEM BOOT
CLKGEN
DISABLED
DE FAULT
DE FAULT
DE FAULT
DE FAULT
Internal pull up
R354
10K_0402_5%
2
1
R355
10K_0402_5%
2
1
+3VALW
R353
10K_0402_5%
2
1
+3VALW
R352
10K_0402_5%
2
1
+3VALW
R351
10K_0402_5%
2
1
+3VALW
R350
10K_0402_5%
2
1
+3VALW
DE FAULT
R349
10K_0402_5%
2
1
+3VS
EC
DISABLED
R348
10K_0402_5%
2
1
+3VS
EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)
+3VALW
R356
2.2K_0402_5%
11/30 update
<19> PCICLK2
<19,32> CLK_PCI_SIO
<19> PCI_CLK4
<19> PCI_CLK5
<19,33> CLK_PCI_EC
<19> LPCCLK1
<19> RTC_CLK
<20,33> HDARST#
<20> GPIO17
<20> GPIO16
R365
2.2K_0402_5%
2
1
R364
10K_0402_5%
2
1
R363
2.2K_0402_5%
2
1
R362
10K_0402_5%
2
1
R360
10K_0402_5%
2
1
R361
10K_0402_5%
2
1
R359
10K_0402_5%
2
1
R357
10K_0402_5%
2
1
R358
10K_0402_5%
2
1
09/29 update
2
+3VS
H,H = Reserved
R347
10K_0402_5%
2
1
+3VS
GP16
PCI_CLK2
DE FAULT
PULL
LOW
PULL
HIGH
R366
2.2K_0402_5%
2
1
DEBUG STRAPS
PULL
LOW
PCI_AD24
PCI_AD23
USE IDE
PLL
USE DEFAULT
PCIE STRAPS
RESERVED
DE FAULT
DE FAULT
DE FAULT
DE FAULT
DE FAULT
USE
SHORT
RESET
BYPASS
PCI PLL
BYPASS
ACPI
BCLK
BYPASS IDE
PLL
USE EEPROM
PCIE STRAPS
R378
2.2K_0402_5%
2
1
R377
2.2K_0402_5%
2
1
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
R373
2.2K_0402_5%
2
1
<19>
<19>
<19>
<19>
<19>
<19>
PCI_AD25
USE ACPI
BCLK
R376
2.2K_0402_5%
2
1
PULL
HIGH
PCI_AD26
USE PCI
PLL
R375
2.2K_0402_5%
2
1
PCI_AD28
PCI_AD27
USE
LONG
RESET
R374
2.2K_0402_5%
2
1
l.c
ho
SB700 STRAPS
Rev
0.2
f@
ai
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
23
he
2007/08/02
Issued Date
tm
Security Classification
om
of
48
HDD Connector
JP9
1
C594
1
C591
2
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
10U_0805_10V4Z
C1032
@
1
@ C1033
2
0.1U_0402_16V4Z
1
@ C1034
C1035
0.1U_0402_16V4Z
+3VS_HDD1
@R1009
1
2
0_0805_5%
2
2 @
0.1U_0402_16V4Z
SATA_TXP0
SATA_TXN0
0.01U_0402_16V7K
SATA_RXN0
2
SATA_RXP0
2
0.01U_0402_16V7K
1 C592 SATA_RXN0_C
1 C596 SATA_RXP0_C
SATA_TXP0
SATA_TXN0
<21>
<21>
SATA_RXN0_C
SATA_RXP0_C
<21>
<21>
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
11/14 update
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
C595
0.1U_0402_16V4Z
C593
10U_0805_10V4Z
+5VS
+3VS_HDD1
+5VS
CONN@ SUYIN_127072FR022G523_RV
Multi-Bay Connector-option
2
1
C602
2
0.1U_0402_16V4Z
1
C603
C604
0.1U_0402_16V4Z
C601
10U_0805_10V4Z
+5VS
Max 3A
2
2
0.1U_0402_16V4Z
+3VS_HDD2
+5VS
JP10
@R1010
1
2
0_0805_5%
1
@ C1037
2
0.1U_0402_16V4Z
1
@ C1038
C1039
0.1U_0402_16V4Z
+3VS
16
15
14
13
12
11
10
9
VCC5
VCC5
VCC5
VCC3
VCC3
VCC3
GND
GND
GND
TX+
TXGND
RXRX+
GND
GND
1
2
3
4
5
6
7
8
18
GND
GND
17
SATA_TXP1
SATA_TXN1
0.01U_0402_16V7K
SATA_RXN1
2
SATA_RXP1
2
0.01U_0402_16V7K
1 C605SATA_RXN1_C
1 C606 SATA_RXP1_C
SATA_TXP1
SATA_TXN1
<21>
<21>
SATA_RXN1_C
SATA_RXP1_C
<21>
<21>
CONN@ TYCO_2023087
2
2 @
0.1U_0402_16V4Z
11/14 update
CD-ROM Connector
JP11
+5VS
1
C615
10U_0805_10V4Z
1U_0603_10V4Z
1
C614
C613
0.1U_0402_16V4Z
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
V5
V5
MD
GND
GND
8
9
10
11
12
13
C616
10U_0805_10V4Z
SATA_TXP3
SATA_TXN3
0.01U_0402_16V7K
SATA_RXN3
2
SATA_RXP3
2
0.01U_0402_16V7K
R970 0_0402_5%
1
2
1 C612 SATA_RXN3_C
1 C611 SATA_RXP3_C
SATA_TXP3
SATA_TXN3
<21>
<21>
SATA_RXN3_C <21>
SATA_RXP3_C <21>
+5VS
CONN@ SUYIN_127382FR013G509ZR
11/14 update
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
24
of
48
PJP605
1
+3VALW
2
PAD-OPEN 4x4m
1
R1055
2
3.6K_0402_5%
+3V_LAN
D
40 mils
GND
NC
NC
VCC
R1056
100K_0402_5%
C1078
1
0.1U_0402_16V4Z
DO
DI
SK
CS
5
6
7
8
+3V_LAN
C1077
1
+3V_LAN
Q144
SI2301BDS-T1-E3_SOT23-3
4
3
2
1
2
G
LAN_DO
LAN_DI
LAN_SK_LAN_LINK#
LAN_CS
3
U17
<33>
AT93C46-10SI-2.7_SO8
1
R1057
LAN_POWER_OFF
2
10K_0402_5%
0.1U_0402_16V4Z
2
R1058
C485 2
1 0.1U_0402_16V7K PCIE_PTX_IRX_P3
20
HSOP
<10>
PCIE_PTX_C_IRX_N3
C488 2
1 0.1U_0402_16V7K PCIE_PTX_IRX_N3
21
HSON
15
PCIE_ITX_C_PRX_P3
<10>
16
PCIE_ITX_C_PRX_N3
<15> CLK_PCIE_LAN
<15> CLK_PCIE_LAN#
<15>
CLKREQ_LAN#
<11,14,19,26,27,32,33>
+3VS
PLT_RST#
R1059 1
R1060
1K_0402_1%
<20>
2 2.49K_0402_1%
LAN_PCIE_WAKE#
ISOLATEB
LAN_X1
LAN_X2
ISOLATEB
HSIN
RTL8102EL
REFCLK_P
REFCLK_M
25
CLKREQB
27
PERSTB
46
RSET
26
28
LANWAKEB
ISOLATEB
LED0
38
LAN_ACTIVITY#
MDIP0
MDIN0
MDIP1
MDIN1
NC
NC
NC
NC
2
3
5
6
8
9
11
12
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
NC
CKXTAL1
CKXTAL2
R1061
15K_0402_5%
23
24
LAN_DO
LAN_DI
LAN_SK_LAN_LINK#
LAN_CS
HSIP
17
18
41
42
33
34
35
32
LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS
NC
NC
7
14
31
47
GND
GND
GND
GND
22
GNDTX
C628
0.1U_0402_16V4Z
LAN_X1
LAN_X2
0.1U_0402_16V4Z
C630
0.1U_0402_16V4Z
C631
C620
C621
C622
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
Close to Pin48
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to Pin45
VCTRL12A
48
VDDTX
DVDD12
DVDD12
DVDD12
DVDD12
19
30
36
13
10
NC
39
NC
VCTRL12D
44
45
VDD33
VDD33
29
37
AVDD33
NC
NC
1
40
43
VCTRL12
+LAN_VDD12
0.1U_0402_16V4Z
VCTRL12
1
+EVDD12
+LAN_VDD12
C1080
C1079
2
1
@ 10U_0805_10V4Z
1
C632
0.1U_0402_16V4Z
C633
@ 10U_0805_10V4Z
+LAN_VDD12
+3V_LAN
Close to Pin19
+EVDD12
11/13 update
Y5
+3V_LAN
C629
RTL8102EL-GR_LQFP48_7X7
10/09 update
Close to Pin1,37,29
+LAN_VDD12
Close to Pin10,13,30,36
U20
<10>
<10>
1
10K_0402_5%
2
C1081
1U_0402_6.3V4Z
C1082
0.1U_0402_16V4Z
25MHz_20pF_6X25000017
1
C653
C654
27P_0402_50V8J
2 27P_0402_50V8J
2
LAN Conn.
C648 1
2 0.01U_0402_16V7K
C647 1
2 0.01U_0402_16V7K
11/09 update
U19
10/29 update
LAN_MDI0+
LAN_MDI0LAN_CT0
LAN_CT1
LAN_MDI1+
LAN_MDI1-
1
2
3
4
5
6
7
8
RD+
RDCT
NC
NC
CT
TD+
TD-
RX+
RXCT
NC
NC
CT
TX+
TX-
16
15
14
13
12
11
10
9
RJ45_MIDI0+
RJ45_MIDI0RJ45_CT0
RJ45_CT1
RJ45_MIDI1+
RJ45_MIDI1-
RJ45_MIDI0+ <35>
RJ45_MIDI0- <35>
C1083 1
C1084 1
LAN_ACTIVITY#
2 0.01U_0603_100V7-M RJ45_CT0_C
2 0.01U_0603_100V7-M RJ45_CT1_C
RJ45_MIDI1+ <35>
RJ45_MIDI1- <35>
75_0402_1%
1 R394
2
1
2
R396
75_0402_1%
+3V_LAN
13
Yellow LED+
1 300_0402_5%
14
Yellow LED-
1
RJ45_GND
C658
1000P_1206_2KV7K
LEF8423A-R
R391
C656
@68P_0402_50V8K
PR4+
PR2-
PR3-
PR3+
RJ45_MIDI1+
PR2+
RJ45_MIDI0-
PR1-
RJ45_MIDI0+
PR1+
SHLD1
PR4-
7
RJ45_MIDI1-
11/05 update
JRJ45
11/09 update
@C657
+3V_LAN
68P_0402_50V8K
LAN_SK_LAN_LINK#1 R395
2
1 300_0402_5%
11
Green LED+
12
Green LED-
16
DETECT PIN1
DETCET PIN2
10
SHLD1
15
FOX_JM36113-P1122-7F
CONN@
1
1
C661
C662
4
0.1U_0402_16V4Z
LANGND
4.7U_0805_10V4Z
l.c
ai
Rev
0.2
f@
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
25
he
2007/08/02
Issued Date
tm
Security Classification
om
9/20 DC234001G00
of
48
+3VS_WLAN
Max 1A
+1.5VS
2 R407 1
0_0805_5%
+1.5VS_WLAN
Max 0.5A
+3VALW
+3VS_WLAN
@ R1043 0_0603_5%
1
2
R1042 0_0603_5%
1
2
C667
C665
0.1U_0402_16V4Z
C666
C668
4.7U_0805_10V4Z
0.01U_0402_16V7K
2
C669
C670
4.7U_0805_10V4Z
+3VALW
+3VS_MINI
+3VS
+3VALW_WWAN
R971 0_0603_5%
2
1
@ R972 0_0603_5%
2
1
1
C671
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
JP14
<31> CH_DATA
<31> CH_CLK
CLKREQ_MCARD2#
<15> CLK_PCIE_MCARD2#
<15> CLK_PCIE_MCARD2
<10>
<10>
<10>
<10>
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2
+3VS_WLAN
R47
2 0_0603_5%
11/09 update
1 R49
BT_COMBO_EN#
CH_CLK
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
0_0402_5%
2
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
53
54
55
56
R48
+3VS_WLAN
<20>
<15>
MINI_PCIE_WAKE#
CLKREQ_MCARD1#
<15> CLK_PCIE_MCARD1#
<15> CLK_PCIE_MCARD1
R52
WL_OFF#
PLT_RST#
1
2
0_0402_5%
WLOFF#
Max 0.3A
SMB_CK_CLK1
SMB_CK_DAT1
WL_LED#
WL_LED#
1
3
5
7
9
11
13
15
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
<20>
<20>
<10>
<10>
PCIE_PTX_C_IRX_N5
PCIE_PTX_C_IRX_P5
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
<10>
<10>
PCIE_ITX_C_PRX_N5
PCIE_ITX_C_PRX_P5
<34>
+3VS_MINI
R401 1
11/09 update
2 0_0603_5%
1
@C738
39P_0402_50V8J
CONN@
FOX_AS0B226-S99N-7F
4.7K_0402_5%
@ C781
@ C782
@ C783
2
1
0.01U_0402_16V7K
0.1U_0402_16V4Z
+3VS_MINI
+1.5VS_MINI
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
R53
WW_OFF# 1
2
PLT_RST#
0_0402_5%
WWOFF#
<21>
+3VALW_WWAN
Max 0.3A
SMB_CK_CLK1
SMB_CK_DAT1
USB20_N10
USB20_P10
WW_LED#
WW_LED#
<20>
<20>
<34>
CONN@
FOX_AS0B226-S99N-7F
53
54
55
56
9/20 SP01000HS00/SP01000LX00
09/29 update
4.7U_0805_10V4Z
<21>
+3VALW_WLAN
USB20_N8
USB20_P8
+1.5VS_MINI
Max 0.5A
2@ L79
1
0_0805_5%
JP13
+1.5VS_WLAN
G1
G2
G3
G3
<21>
1
3
5
7
9
11
13
15
+1.5VS
+3VS_MINI
Max 2.7A
4.7U_0805_10V4Z
1 L78
2 0.01U_0402_16V7K
0_1206_5%
1
1
1
C785
C786
C787
1
@ C784
0.1U_0402_16V7K
2
2
2
2
0.1U_0402_16V4Z
G1
G2
G3
G3
<15>
MINI_PCIE_WAKE#
CH_DATA
CH_CLK
+3VALW_WLAN
R406 2
1
0_0805_5%
1
New Card
+3VS
C679
2
1 0.1U_0402_16V4Z
<11,14,19,25,27,32,33>
PLT_RST#
<33,34,36,40>
<20>
17
PLT_RST#
11/22 update
1 R54
2
0_0402_5%
SYSON
<28,33,36,38,41>
2
4
1 0.1U_0402_16V4Z
2
C680
SUSP#
EXP_CPPE#
EXP_CPPE#
+3VS_MINI
U21
C681
2
1 0.1U_0402_16V4Z
Max 0.275A
+3VALW
11/09 update
1.5Vin
1.5Vin
1.5Vout
1.5Vout
11
13
3.3Vin
3.3Vin
3.3Vout
3.3Vout
3
5
AUX_IN
OC#
19
SHDN#
STBY#
NC
10
CPPE#
GND
9
18
PERST#
CPUSB#
THERMAL_PAD
RCLKEN
+3VS_PEC
Max 1.3A
15
SYSRST#
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
Max 0.65A
AUX_OUT
20
JP6
+1.5VS_PEC
+3V_PEC
1
2
3
4
5
6
7
1
2
3
4
5
6
7
9/20 SP02000IQ00
G1
G2
8
9
ACES_88266-07001
CONN@
PERST#
16
7
R1037
UIM_DATA
21
UIM_PWR
@ 10K_0402_5%
C1070
R5538D001-TR-F_QFN20_4X4~D
2
USE TI TPS2231MRGPR
Near to Express Card slot.
9/20 SP02000B000
<20>
<20>
<20>
<20>
USB20_N11
USB20_P11
EXP_CPPE#
SMB_CK_CLK1
SMB_CK_DAT1
+1.5VS_PEC
SMB_CK_CLK1
SMB_CK_DAT1
MINI_PCIE_WAKE#
+3V_PEC
PERST#
+3VS_PEC
<15>
CLKREQ_NCARD#
<15> CLK_PCIE_NCARD#
<15> CLK_PCIE_NCARD
<10>
<10>
PCIE_PTX_C_IRX_N0
PCIE_PTX_C_IRX_P0
<10>
<10>
PCIE_ITX_C_PRX_N0
PCIE_ITX_C_PRX_P0
CLKREQ_NCARD#
EXP_CPPE#
27
28
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND
GND
C1071
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C677
C678
2
2
0.1U_0402_16V4Z
+1.5VS_PEC
4.7U_0805_10V4Z
1
C683
C682
2
2
0.1U_0402_16V4Z
4
+3V_PEC
4.7U_0805_10V4Z
1
C684
1
C685
CONN@ SANTA_130801-5_LT
09/13 Update
A
+3VS_PEC
JEXP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
Rev
0.2
Sheet
26
of
48
+VCC_OUT
+VCC_4IN1
+VCC_4IN1
JREAD
U22
1
5
1
OUT
OUT
GND
@ G5250C2T1U_SOT23-5
@ C896
2
2
@ 0.1U_0402_16V4Z
IN
EN
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
1U_0603_10V4Z
@ R123
150K_0402_5%
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
SDCMD_MSBS_XDWE# 34
XDWP#_SDWP#
33
XD_ALE
35
XD_CD#
40
XD_RB#
39
XD_RE#
38
XDCE#
37
XD_CLE
36
11/06 update
+VCC_4IN1
11/06 update
21
28
+VCC_4IN1
SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW
20
14
12
30
29
27
23
18
16
25
1
SDCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
SDCMD_MSBS_XDWE#
XDCD0#_SDCD#
XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
SD-WP-SW
XDWP#_SDWP#
7IN1 GND
7IN1 GND
MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS
26
17
15
19
24
22
13
MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDCD1#_MSCD#
SDCMD_MSBS_XDWE#
41
42
7IN1 GND
7IN1 GND
SDCLK
C694
0.1U_0402_16V4Z
MSCLK
11/13 update
2
@ C901
100P_0402_25V8K
D40
XD_CD#
1
3
1
C696
270P_0402_50V7K
11/06 update
2
10K_0402_5%
2
10K_0402_5%
200K_0402_5%
1
R405
1
R122
XD_CLE
1
R86
XD_RE#
XD_ALE
+1.8VS
+1.8VS_OUT
1
2
@ C900
100P_0402_25V8K
C892
0.1U_0402_16V4Z
1
C688
1000P_0402_50V7K 2 R1020 1
0_0603_5%
1
1
C687
2 2
G
2
2
10U_0805_10V4Z
C893
2
2
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z C695
Q54
1
CPPE#
Power Circuit
D3E@ 0_0402_5%
1
2
R369
+3VS_CR
+3VS
2N7002_SOT23-3
CR_WAKE#
R111 4.7K_0402_5%
1
20mil
10K_0402_5%
<21>
XDCD1#_MSCD# 2
DAN202U_SC70
+3VS
R124
CR_CPPE#
2
1
R106 10K_0402_5%
@ R411
100_0402_5%
@ R412
100_0402_5%
2
@ C902
100P_0402_25V8K
+3VS_CR
R121 4.7K_0402_5%
XDCD0#_SDCD#2
1
XDCE#
2
@ R413
100_0402_5%
<20>
XD_RB#
CONN@ TAITW_R015-B10-LM
C689
10U_0805_10V4Z
7 IN 1 CONN
11
31
R383 2
1
0_0805_5%
SD-VCC
MS-VCC
XD-VCC
32
10
9
8
7
6
5
4
10K_0402_5%
1
3
4
1
C895
+VCC_4IN1
40mil
+3VS
R45
XDWP#_SDWP# 2
XDCD0#_SDCD#
<10>
<10>
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
<15> CLK_PCIE_MCARD0#
<15> CLK_PCIE_MCARD0
3
4
APCLKN
APCLKP
<10>
<10>
9
8
APRXN
APRXP
11
12
APTXN
APTXP
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1
C693 1
C697 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_PTX_IRX_N1
PCIE_PTX_IRX_P1
2 R114
1
10K_0402_1%
APREXT
12mil
2 R409
1
10K_0402_5%
+3VS_CR
+5VS_LED
7
38
39
PCIES_EN
PCIES
XRSTN
XTEST
2
2
CPPE#
PAD T45
D5
HT-F196BP5_WHITE
XDCD1#_MSCD#
XDCD0#_SDCD#
11/10 update
+VCC_OUT
D
Q53
2
G
2N7002_SOT23-3
At least 20mils
13
14
SEEDAT
SEECLK
15
16
CR1_CD1N
CR1_CD0N
17
CR1_PCTLN
Ripple 250mV
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
48
47
46
45
43
42
41
40
29
28
27
26
25
23
22
NC
NC
NC
34
35
36
APGND
19
20
44
18
37
21
GND
GND
GND
GND
CR1_LEDN
C691
C692
Ripple 100mV
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
Ripple 250mV
+1.8VS_OUT
1
XD_SD_MS_D0
C686
XD_SD_MS_D1
0.1U_0402_16V4Z
2
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDCE#
R457 2
XDWP#_SDWP#
R456 2
XD_CLE
R455 2
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
XD_RE#
11/07 update
XD_RB#
XD_ALE
C690
0.1U_0402_16V4Z
1 22_0402_5%
1 22_0402_5%
1 22_0402_5%
SDCLK
MSCLK
XDCE#
11/06 update
6
24
31
32
33
45mA DV33
DV33
DV33
25mA DV18
DV18
JMB385
1
2
PLT_RST#
Ripple 100mV
APREXT
R370
<11,14,19,25,26,32,33>
5
10
30
1mA
470_0402_5%
APVDD
APV18
TAV33
58mA
2 R1021 1
0_0603_5%
R454
JMB385-LGEZ0A_LQFP48_7X7
4.7K_0402_5%
2
11/06 update
4
l.c
ai
Rev
0.2
f@
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
27
he
2007/08/02
Issued Date
tm
Security Classification
om
of
48
CODEC POWER
+3VS_HDA
+3VDD_CODEC
+3VS
R885
1
2
BLM18BD601SN1D_0603
C734
+3VS
C733
+VDDA_CODEC
R978
1
2
BLM18BD601SN1D_0603
0.1U_0402_16V4Z
1
+VDDA_CODEC_R
R979
1
2
0_0603_5%
C1046
C730
0.1U_0402_16V4Z
1U_0603_10V4Z
+5VALW
W=40Mil
1
C728
C731
1U_0603_10V4Z
<26,33,36,38,41>
+VDDA_CODEC
U32
1
2
0.1U_0402_16V4Z
SUSP#
IN
GND
SHDN
OUT
BYP
G9191-475T1U_SOT23-5 1
0.1U_0402_16V4Z
(4.75V(4.56~4.94V))
300mA
C729
2.2U_0805_16V4Z
C732
0.1U_0402_16V4Z
U27
9
DVDD_CORE*
DVDD_CORE
25
+3VS_HDA
<20>
AVDD2**
DVDD_IO
HDA_SDOUT_CODEC
HDA_SDOUT_CODEC
SDO
R522 1
SDI_CODEC
<20>
HDA_SDIN0
HDA_SYNC_CODEC
10
SYNC
HDA_RST#_CODEC
HDA_RST#_CODEC
11
RESET#
46
DMIC_CLK
<20>
2
<17>
11/28 update
2 33_0402_5%
DMIC_CLK
<33>
EC_BEEP
R563 1
<20>
SB_SPKR
R524 1
2 47K_0402_5%
R523 1
2 10K_0402_5%
C956
2 @ 47K_0402_5%
+VDDA_CODEC_R
<35> SENSE_B#
2 0.1U_0402_16V4Z
R982 1
R910 1
22_0402_5%
2
R230 1
40
2 5.1K_0402_1%
2 39.2K_0402_1%
C979
0.1U_0402_16V4Z
31
GPIO 6
44
45
SPDIF OUT0
48
VREFOUT-B
28
VREFOUT-C
29
33
2
1
C913
1U_0603_10V4Z CAP2
MONO_INR
12 PCBEEP
2
0.1U_0402_16V4Z
C955
SENSEB#
SPDIF_OUT
SPDIF_OUT
PAD
<35>
T21
11/26 update
13
VREFOUT_B
VREFOUT_B
<29>
+VDDA_CODEC_R
R548
R569
R571
R570
C951
SENSE
41
HP_OUTR
PORTA_L
39
HP_OUTL
PORTB_R
22
MIC_EXTR
PORTB_L
21
MIC_EXTL
1
1
1
1
2
2
2
2
5.1K_0402_1%
20K_0402_1%
39.2K_0402_1%
10K_0402_1%
0.1U_0402_16V4Z
1
2
HP_OUTR <29>
HP_OUTL
1
C981
1
C982
2
2
EXTMIC_DET# <29>
JACK_DET# <29,35>
INTMIC_DET# <29>
<29>
MIC_EXT_R
1U_0603_10V6K
C983
1
1U_0603_10V6K
0.022U_0603_25V7K
2
SENSE_B / NC
37
NC
PORTC_R
24
MIC_INR
18
NC
PORTC_L
23
MIC_INL
@ R911
0_0603_5%
19
NC
PORTD_R
36
LINE_OUT_R
LINE_OUT_R
<29>
C984
1
PORTD_L
35
LINE_OUT_L
LINE_OUT_L
<29>
20
10U_0805_10V4Z
VC_REFA
C744 1
2
<33>
<17>
34
DMIC_DAT
PORTA_R
NC / OTP
EAPD_CODEC
43
SENSE_A
EAPD_CODEC
30
GPIO 5
BITCLK
HDA_SYNC_CODEC
1
@C745
33P_0402_50V8K
47
2
VREFOUT-E / GPIO 4
MONO_OUT
HDA_BITCLK_CODEC
<20>
2
<20>
GPIO 3
HDA_BITCLK_CODEC
@
R525
47_0402_5%
VOL_DN/DMIC_1/GPIO 2
AVDD1*
38
32
HDA_BITCLK_CODEC
VOL_UP/DMIC_0/GPIO 1
NC
<29>
Jack MIC
MIC_EXT_L <29>
MIC_IN_R <29>
+VDDA_CODEC_R
27
VREFFILT
PORTE_R
15
DOCK_MICR
26
AVSS1*
PORTE_L
14
DOCK_MICL
42
AVSS2**
PORTF_R
17
DVSS**
PORTF_L
16
+3VDD_CODEC
1
C985
1
C986
2
2
Internal SPKR.
Internal MIC
0.022U_0603_25V7K
2
MIC_IN_L
<29>
11/18 update
1U_0603_10V6K
1U_0603_10V6K
DOCK_MIC_R
<35>
DOCK_MIC_L
<35>
DOCK MIC
3
92HD71B7X5NLGXA1X8_QFN48_7X7
@ C746
1
2
0.1U_0402_16V4Z
@ C747
1
2
0.1U_0402_16V4Z
SENSE A
@ C748
1
2
0.1U_0402_16V4Z
SENSE B
@ C749
1
2
0.1U_0402_16V4Z
Port
Resistor
Port
Resistor
39.2K
39.2K
@ R1006
1
2
0_0402_5%
20K
20K
@R195
1
2
0_0805_5%
10K
10K
R198
1
2
0_1206_5%
5.11K
H
A
5.11K
GND
Security Classification
GNDA
GNDA
B
Use an 80mil to
connection or place
a 1206 resistor under
CODEC with double
vias.
<29,35>
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
Rev
0.2
Sheet
28
of
48
+5VAMP
+5VS
C766
10U_0805_10V4Z
C767
C1051
SPEAKER
R594
1
2
0_1206_5%
0.1U_0402_16V4Z
GAIN0
GAIN1
6dB
10dB
SPKL+
SPKLSPKR+
SPKR-
+5VS
0.1U_0402_16V4Z
VDD
PVDD1
PVDD2
C1054
<28>
LINE_OUT_L
C1041
0_0402_5%
1
1
2 0.022U_0603_25V7K
2
47P_0402_50V8J
1
1
2 0.022U_0603_25V7K
2
47P_0402_50V8J
ROUT+
18
SPKR+
ROUT-
14
SPKR-
LOUT+
SPKL+
LOUT-
SPKL-
1
2
GAIN1
RIN-
R1003
LIN+
LIN-
SHUTDOWN
21.6dB
R1004
@ 100K_0402_5%
+VDDA_CODEC
C743
1U_0603_10V4Z
1
2
R906
0_0402_5%
2
1
+VDDA_CODEC
BYPASS
10
R904
4.7K_0402_5%
R905
4.7K_0402_5%
C1044
11/18 update
4.7U_0805_10V4Z
2
1
R955 10K_0402_5%
+3VS
<33>
ANA_MIC_DET
2N7002_SOT23-3
Q160
R909
C742 1
MIC_EXT_L
ACES_88231-04001
CONN@
2
G
S
2
G
9/20 SP02000H700/SP02000H900
4.7K_0402_5%
2
EXTMIC IN
MIC_EXT_R
MIC_EXT_L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
HP_OUT_R
HP_OUT_L
3
S Q161
2N7002_SOT23-3
EXTMIC_DET#
<33,35>
1
1
CIR_ IN
CIR_IN
+5VL
R975
330K_0402_5%
2
G
EXTMIC_DET#
HP_DET#
9/20 SP02000H800
2N7002DW-7-F_SOT363-6
Q145B
6
5
HP_OUTR
<28>
HP_OUTL
Q147B
2N7002DW-7-F_SOT363-6
DOCK_LOUT_L
4
11/05 update
11/19 update
R968
C775 150U_Y_6.3VM
1
2 DOCK_LOUT_CR_R 1
2
47_0603_1%
+
1
<28>
Q147A
2N7002DW-7-F_SOT363-6
DOCK_LOUT_R
1
R969
C776 150U_Y_6.3VM
1
2 DOCK_LOUT_CR_L
+
2N7002DW-7-F_SOT363-6
Q145A
5
HP_DET#
09/13 update
6 1
10/30 update
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CONN@ ACES_87213-1400G
R974
10K_0402_5%
R973
10K_0402_5%
+3VALW
+3VALW
<28>
B+
JACK_DET#
<28,35>
R908
2
MIC_EXT_L
GND1
GND2
1U_0603_10V4Z
1
R907
4.7K_0402_5%
<28>
5
6
2
1
0_0402_5%
MIC_EXT_R
1
2
3
4
INTMIC_DET#
2N7002_SOT23-3
MIC_EXT_R
1
2
3
4
D
Q151
<28>
<28>
JP42
<28> MIC_IN_L
<28> MIC_IN_R
TPA6017A2_TSSOP20
VREFOUT_B
INTMIC IN
R951
100K_0402_5%
2
NC
12
21
20
13
11
1
<28>
19
THERMAL PAD
EC_MUTE#
EC_MUTE#
GND1
GND2
CONN@ E&T_3806-F04N-02R
100K_0402_5%
GND1
GND2
GND3
GND4
<33>
5
6
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
C1055
17
C1040
R1005
2 0.022U_0603_25V7K
2
47P_0402_50V8J
15.6dB
C763
C1053
1
1
GAIN0
2
100P_0402_50V8J
C762
1
2
3
4
0_0402_5%
RIN+
C1050
C761
1
2
3
4
LINE_OUT_R
2 0.022U_0603_25V7K
2
47P_0402_50V8J
R1001
100K_0402_5%
C1052
R1002
<28>
1
1
R1000
@ 100K_0402_5%
11/18 update
C1049
11/18 update
16
15
6
1
U28
C760
15.6dB
1
11/14 update
JP20
Av(inv)
1
2
47_0603_1%
DOCK_LOUT_C_R
DOCK_LOUT_C_R
<35>
DOCK_LOUT_C_L
<35>
C773 150U_Y_6.3VM
HP_OUT_R
1
2
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
l.c
ai
tm
Title
Rev
0.2
f@
2008/08/02
Deciphered Date
in
2007/08/02
Issued Date
ho
Security Classification
om
Sheet
E
xa
C774 150U_Y_6.3VM
HP_OUT_L
1
2
29
he
of
48
ACCELEROMETER
+3VS
+3VS_ACL
D44
2
R959
1
+3VS_ACL_IO
0_0603_5%
2
CH751H-40PT_SOD323-2
C1030
C1031
10U_0805_6.3V6M
2
0.1U_0402_16V4Z
SMB_CK_CLK0
+3VS_ACL_IO
R997
0_0402_5%
1
2
+3VS_ACL
SMB_CK_CLK0
<8,9,15,20>
14
SCL / SPC
U63
0011101b
Vdd_IO
GND
Reserved
GND
GND
10
GND
INT 2
Vdd
INT 1
13
SDO
12
Reserved
11
SMB_CK_DAT0
SMB_CK_DAT0
<8,9,15,20>
HDD_HALTLED
<34>
ACCEL_INT
R998
0_0402_5%
1
2
<19>
CS
LIS302DLTR_LGA14_3x5
2
R999
1
10K_0402_5%
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
30
of
48
Left side
USB CONNECTOR
Left side
Max 2.5A
+USB_VCCA
+5VALW
U40
W=100mils
8
7
6
5
OUT
OUT
OUT
OC#
TPS2061IDGN_MSOP8~N
4.7U_0805_10V4Z
1
+
2
1000P_0402_50V7K
C791
GND
IN
IN
EN#
0.1U_0402_16V4Z
C790
C788
1
2
3
4
USB20_N2_R
C789
150U_D_6.3VM
VIN
IO1
IO2 GND
USB20_P2_R
<20>
@ PRTR5V0U2X_SOT143-4
USB20_N2
<20>
USB20_P2
+USB_VCCA
SATA_TXN2
1
2
3
4
USB20_N2_R
USB20_P2_R
VIN
IO1
IO2 GND
SATA_TXP2
@ PRTR5V0U2X_SOT143-4
<21>
<21>
<21>
<21>
SATA_TXP2
SATA_TXN2
SATA_TXP2
SATA_TXN2
SATA_RXN2_C
SATA_RXP2_C
1 0.01U_0402_16V7KSATA_RXN2
1 0.01U_0402_16V7KSATA_RXP2
C792 2
C793 2
USB_EN#
VBUS
DD+
GND
1
2
3
4
5
6
7
8
9
10
+5VALW
JESAT
WCM-2012-900T_4P
JP47
11/14 update
+USB_VCCA
L51
4 4
D12
D11
+USB_VCCA
USB
USB_EN#
<33> USB_EN#
<20> USB20_N0
<20> USB20_P0
5
6
7
8
9
10
11
GND
A+
ESATA
AGND
BB+
GND
12
13
14
15
GND
GND
GND
GND
<20>
<20>
USB20_N1
USB20_P1
11
12
1
2
3
4
5
6
7
8
9
10
GND1
GND2
ACES_87213-1000G
9/20 SP02000DX00
CONN@
CONN@ TYCO_1759576-1
Finger printer
BT Connector
11/14 update
JP32
2
@ 0_0603_5%
20070209
@ SI2301BDS-T1-E3_SOT23-3
Q31
+3VS_FB
1
1
<20>
<20>
G
USB_EN#
USB20_N7
C832
0.1U_0402_16V4Z
USB20_N7
USB20_P7
USB20_N7
USB20_P7
D21
+3VS_FB
1
2
0_0603_5%
IO1
IO2 GND
USB20_P7
USB20_P6 <20>
USB20_N6 <20>
BT_LED <34>
CH_DATA <26>
CH_CLK <26>
1K_0402_5%
1K_0402_5%
2
2
0612 no install
D16
ACES_88231-08001
CONN@
+3VAUX_BT
USB20_N6
9/20 SP02000HC00/SP02000HB00
VIN
IO1
IO2 GND
USB20_P6
@ PRTR5V0U2X_SOT143-4
+3VALW
Q24
ACES_85201-06051
CONN@
+3VAUX_BT
SI2301BDS-T1-E3_SOT23-3
9/20 SP01000B000
1
C798
R519
1U_0603_10V4Z
100K_0402_5%
C799
C800
C801
0.1U_0402_16V4Z
@ PRTR5V0U2X_SOT143-4
@ R517 1
@ R518 1
VIN
1
2
3
4
5
6
GND
GND
+3VAUX_BT
USB20_P6
USB20_N6
JP39
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
GND1
GND2
+3VS
R622
1
+3VALW
0.01U_0402_16V7K
11/20 update
<21>
BT_OFF
4.7U_0805_10V4Z
R520
1
2
10K_0402_5%
1
C802
2
0.1U_0402_16V4Z
l.c
ai
Rev
0.2
f@
tm
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
31
he
2007/08/02
Issued Date
ho
Security Classification
om
of
48
+3VL
0.1U_0402_16V4Z
SMB_EC_CK1
SMB_EC_DA1
CONN@
U29
2
0_0402_5% 1
C803
11/28 update
R521
100K_0402_5%
U31
8
7
6
5
<33>
SPI_CS#
<33>
SPI_CLK
SPI_CS#
1
R996
1
<33,34,37>
<33,34,37>
0.1U_0402_16V4Z
2
0_0402_5%
20mils
C484
+3VAL
+3VL
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
<33>
EC_SO_SPI_SI
VCC
HOLD
INT_SPI_CS#
2
1
0_0402_5%
SPI_CLK_R
6
2
0_0402_5%
1 EC_SO_SPI_SI_R 5
0_0402_5%
1
R221
1
R227
2
R229
&U29
VSS
45@ SST25VF080B-50-4C-S2AF_SO8
9/20 SA000012E00/SA00000XT00
C
D
EC_SI_SPI_SO_R
2
R223
1
0_0402_5%
EC_SI_SPI_SO
<33>
9/20 SP07000F500
AT24C16AN-10SI-2.7_SO8
+3VALW
12/03 update
R526
100K_0402_5%
C489
G Vcc
U30
R228
INT_SPI_CS#
@ 0.1U_0402_16V4Z
INT_FLASH_EN#
R226
@ 100K_0402_5%
2
SPI_CS#
@ NC7SZ32P5X_NL_SC70-5
@ 22_0402_5%
JP12
SPI_CS#
EC_SI_SPI_SO_R
<21>
1
3
5
7
SB_INT_FLASH_SEL
1
3
5
7
2
4
6
8
2
4
6
8
INT_FLASH_EN#
SPI_CLK_R
EC_SO_SPI_SI_R
+3VALW
@ E&T_2941-G08N-00E~D
C:Chg. PN to LTC00000200
11/13 update
+3VS
JP41
SIRQ
<19,33>
LPC_AD3
<19,33>
LPC_AD1
LPC_FRAME#
LPC_DRQ#
PLT_RST#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME#
10
CLK_PCI_SIO
LPC_DRQ#
PLT_RST#
<19>
<11,14,19,25,26,27,33>
LPC_AD2
<19,33>
LPC_AD0
<19,33>
CLK_PCI_SIO
<19,23>
<19,33>
@ DEBUG_PAD
9/20 ??????
@ R232
22_0402_5%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK_14M_SIO
CLK_14M_SIO
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#
PLT_RST#
R137 1
CLK_PCI_SIO2
SIRQ
CLK_14M_SIO
<15>
1
<19,33>
6
SIRQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
@ R310
100_0402_5%
2
H31
+3VALW
2 @ 0_0402_5%
CLK_PCI_SIO2
<19>
2
11/09 update
@ C502
100P_0402_25V8K
@ ACES_85201-2005
9/20 DC233105000
@ C486
22P_0402_50V8J
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
32
of
48
Keyboard Connector
JP33
+3VL_EC
+3VL
C809
2
2
1000P_0402_50V7K
+3VL_EC
R527
1
+EC_AVCC
2
0_0805_5%
VCC
VCC
VCC
VCC
VCC
VCC
U33
C810
1
<20> GATEA20
<20> KB_RST#
<19,32> SIRQ
<19,32> LPC_FRAME#
<19,32> LPC_AD3
<19,32> LPC_AD2
<19,32> LPC_AD1
<19,32> LPC_AD0
R530
2
2
@ 33_0402_5%
@ 15P_0402_50V8J
<19,23>
CLK_PCI_EC
<11,14,19,25,26,27,32> PLT_RST#
2
47K_0402_5%
<20> EC_SCI#
<20,23> HDARST#
R533 1
+3VL_EC
C811
+3VALW
R538
10K_0402_5%
LID_SW#
11/22 update
+3VL
R528
R529
R531
R532
R513
4.7K_0402_5%
2
1 SMB_EC_DA1
4.7K_0402_5%
2
1 SMB_EC_CK1
4.7K_0402_5%
2
1 SMB_EC_DA2
4.7K_0402_5%
2
1 SMB_EC_CK2
10K_0402_5%
1
2 WL_BLUE_BTN
<32,34,37>
<32,34,37>
<6>
<6>
11/20 update
11/11 update
+3VL
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
21
23
26
27
INV_PWM
FAN_PWM
EC_BEEP
ACOFF
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
63
64
65
66
75
76
BATT_TEMP
BATT_OVP
CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
12
13
37
20
38
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
DA Output
IREF/DA2/GPIO3E
KSI0/GPIO30
DA3/GPIO3F
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
PS2 Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXOA00
KSO4/GPIO24
SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXOA02
KSO6/GPIO26 Matrix
SDIDI/GPXID0
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/RD#
KSO10/GPIO2A
SPIDO/WR#
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL1/GPIO44
SDA1/GPIO45
SUSP_LED#/GPIO55
SM Bus
SCL2/GPIO46
SYSON/GPIO56
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
68
70
71
72
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
77
78
79
80
PWM Output
AD
83
84
85
86
87
88
INV_PWM <17>
FAN_PWM <4>
EC_BEEP <28> 11/13 update
ACOFF <38>
0.01U_0402_16V7K
C812
ECAGND
1
2
BATT_TEMP <37>
BATT_OVP <37>
ADP_I <38>
ADP_ID <37>
TP_BTN# <34>
ANA_MIC_DET <29>
TP_BTN#
TP_CLK
TP_DATA
11/13 update
119
120
126
128
SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT
WL_BLUE_BTN
H_THERMTRIP#_EC
<20> SLP_S3#
<20> SLP_S5#
<20> EC_SMI#
<34> LID_SW#
<34> ESB_CLK
<34> ESB_DAT
<34> WL_BLUE_BTN
<6> H_THERMTRIP#_EC
<35> CONA#
<36> VLDT_EN
E51_TXD
E51_RXD
ON/OFF#
1
CIR_IN
FSTCHG
BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
AC_IN_D
ON/OFF#
1
R542
<36> DIM_LED
<34> NUM_LED#
2
0_0402_5%
C813
15P_0402_50V8J
1
2
Y7
3
NC
OUT
NC
IN
@
R545
20M_0402_5%
32.768KHZ_12.5PF_Q13MC30610003
1
C RY1
+EC_AVCC
<25>
L80
0_0603_5%
E51_RXD
R544
LAN_POWER_OFF
150_0603_1%
JP48
5
6
SB_PWRGD
BKOFF#
TP_LED#
TP_LED#
<34>
L
SUSP#
PWRBTN_OUT#
NMI_DBG#
2
C814
1
2
3
4
ACES_85201-04051
CONN@
+3VS
DOCK@ R589
10K_0402_5%
DOCK_VOL_UP# 2
1
+5VL
DOCK_VOL_DWN# 2
1
DOCK@ R590
10K_0402_5%
update
FSTCHG <38>
STD_ADP <38>
CAPS_LED# <34>
BAT_LED# <34>
2
1
ON/OFFBTN_LED# <34>
R541 10K_0402_5%
SYSON <26,34,36,40>
EC_RSMRST# <20>
EC_LID_OUT# <20>
EC_ON <36,39>
WL_BLUE_LED# <34>
SB_PWRGD <6,20,43>
BKOFF# <17>
1
2
3
4
9/20 SP01000KC00/SP010009O10
2 10K_0402_5%
11/11
<29,35>
<21>
G1
G2
VR_ON <43>
2
1
AC_IN <38,39>
D54
CH751H-40PT_SOD323-2
11/13
2
1
+3VALW
R1040
100K_0402_5%
1
2
C1073
100P_0402_50V8J
R534
10K_0402_5%
1
2
R535
10K_0402_5%
TP_DATA
1
2
+5V_TP
TP_CLK
update
ENBKL <11>
EAPD_CODEC <28>
EC_THERM# <21>
SUSP# <26,28,36,38,41>
PWRBTN_OUT# <20>
SUSP#
SYSON
R536
100K_0402_5%
R547
1
PCI_SERR#
R539
100K_0402_5%
<19>
0_0402_5%
1
4.7U_0805_10V4Z
11/13 update
+3VS
11/13 update
TP_BTN#
R1050
1
2
10K_0402_5%
1
C816
2
0.1U_0402_16V4Z
L81
1
2
0_0603_5%
0_0402_5%
EC DEBUG port
@
JP34
LAN_POWER_OFF
EC_RSMRST#
R516
11/13 update
+3VL_EC
C815
15P_0402_50V8J
11/13 update
4
124
V18R
GPI
XCLK1
XCLK0
11/07 update
122
123
110
112
114
115
116
117
118
C RY2
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
AGND
DOCK_SLP_BTN#
100
101
102
103
104
105
106
107
108
69
<34>
<35>
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
+5VS_LED
EC_SI_SPI_SO <32>
EC_SO_SPI_SI <32>
SPI_CLK <32>
SPI_CS# <32>
CIR_ IN
ECAGND
2
1
R543
4.7K_0402_5%
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
GND
GND
GND
GND
GND
+3VL_EC
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
9/20 SP01000FF00/SP01000G300
R46
73
74
89
90
91
92
93
95
121
127
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
GND1
GND2
DOCK_VOL_UP# <35>
DOCK_VOL_DWN# <35>
VGATE <43>
2
100K_0402_5%
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ACES_85201-24051
CONN@
EC_MUTE# <29>
USB_EN# <31>
I2C_INT <34>
MUTE_LED <35>
TP_CLK <34>
TP_DATA <34>
T20 PAD
97
98
99
109
R1044
25
26
DAC_BRIG <17>
VCTRL <38>
IREF <38>
AC_SET <38>
IR EF
AC_IN_D
R514 1
2 ESB_CLK
10K_0402_5%
R515 1
2 ESB_DAT
10K_0402_5%
11/16 update
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
9/20 SP020007200
EC KB926/KB conn
Size Document Number
Custom
LA-4111P
Date:
l.c
ai
Title
ho
2008/08/02
Deciphered Date
Rev
0.2
f@
2007/08/02
Issued Date
tm
Security Classification
ACES_85205-0400
om
+5VL
in
E51_RXD
E51_TXD
Sheet
E
xa
1
2
3
4
33
he
1
2
3
4
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
11
24
35
94
113
+3VS
1
2
3
4
5
7
8
10
1
0.1U_0402_16V4Z
10/08 update
GATEA20
KB_RST#
SIRQ
LPC_LFRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
For EMI
@ C213
@ C609
@ C754
@ C756
@ C757
@ C758
@ C759
@ C764
@ C768
@ C769
@ C822
@ C823
@ C824
@ C825
@ C826
@ C875
@ C876
@ C877
@ C878
@ C884
@ C885
@ C886
@ C887
@ C888
2
2
0.1U_0402_16V4Z
C808
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C807
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C806
67
C805
1000P_0402_50V7K
AVCC
0.1U_0402_16V4Z
1
9
22
33
96
111
125
0.1U_0402_16V4Z
1
1
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
of
48
10/08 update
<33> ON/OFF#
ON/OFFBTN_LED#
G1
G2
5
6
ACES_85201-04051
CONN@
TP_BTN#
11/20 update
+3VL+5VALW_LED
10/08 update
SWITCH BOARD.
R557
@ 4.7K_0402_5%
<26,33,36,40>
R556
Q34
2N7002_SOT23-3
2
G
SYSON
<33>
@ 10P_0402_50V8J
11/28 update
WL_BLUE_BTN
R1034 1
WL_BLUE_LED# R1035 1
2 RM@ 0_0402_5%
2 RM@ 0_0402_5%
R1046 1
R1047 1
R1048 1
R1049 1
2 CY@ 0_0402_5%
2 CY@ 0_0402_5%
2 ENE@ 0_0402_5%
2 ENE@ 0_0402_5%
I2C_INT
11/13 update
<32,33,37> SMB_EC_CK1
<32,33,37> SMB_EC_DA1
<33> ESB_CLK
<33> ESB_DAT
+5VALW_LED
<33>
1 R1036 2
@ 150_0402_5% <33> NUM_LED#
<21>
HDD_HALTLED
<30>
2
G
Q153
2N7002_SOT23-3
ACES_85201-1005N
CONN@
9/20 SP01000H400
JP40
TP_LED#
<33>
<33>
+3VS
R989
1
2
10K_0402_5%
1 R550
2
200_0402_5%
Q158B
WL/WW_LED
5
4
6
Q158A
1 R552
2
200_0402_5%
2N7002DW-7-F_SOT363-6
2
BT_LED
HT-F196BP5_WHITE
+5VALW_LED
WHITE
R1025
WL_LED#
1
Q168
R1008
DTA114YKAT146_SOT23-3
2
0_0402_5%
WW_LED#
<26>
<26>
R1024
100K_0402_5%
2
1 R549
2
200_0402_5%
100K_0402_5%
2
0_0402_5%
D8
ON/OFFBTN_LED#
1
R1007
09/29 update
<31>
POWER LED
10K
2N7002DW-7-F_SOT363-6
1
D7
2
+3VS
WL_BLUE_LED#
WL_BLUE_LED#
+5VS_LED
WHITE
11/28 update
R1041
2
1
@ 10K_0402_5%
47K
<33>
CONN@ ACES_88231-03041
HT-F196BP5_WHITE
CAPS_LED#
4
5
1
2 GND
3 GND
1
2
3
LID_SW#
11/14 update
11/10 update
WHITE
BAT_LED#
+3VALW
D6
<33>
11/14 update
HT-297UY5/BP5_YELLOW-WHITE
TP_LED#
3
2
G
4 2
YELLOW
HDD_HALTLED#
1 R42
2
0_0402_5%
@ 10K_0402_5%
@ 2N7002_SOT23-3S
1
2
3
4
5
6
7
8
9
10
GND
GND
L
D17
R985
WHITE
10/08 update
HT-297UY5/BP5_YELLOW-WHITE
12/03 update
11/10 update
2 2
+5VS
1
YELLOW
3
2N7002DW-7-F_SOT363-6
R984
390_0402_5%
2
2
3
WHITE
4
2N7002DW-7-F_SOT363-6 D
Q156
SATA_LED#
<21>
D18
6
Q7A
R983
200_0402_5%
390_0402_5%
Q7B
5
09/29 update
JP36
1
2
ON/OFFBTN_LED# 3
4
5
6
7
8
ON/OFF#
9
10
11
12
R988
1
2
10K_0402_5%
R987
200_0402_5%
R20
RM@ 0_0603_5%
+5VS
R558
10K_0402_5%
+5VS_LED
11/14 update
+5VS_LED
+5VS_LED +3VS
R555
RP@0_0603_5%
@ 4.7K_0402_5%
11/20 update
C777
11/13 update
HDD/G-Sensor LED
R554
1
1
1
2
R496
@ 10_0402_5%
C780
@4.7U_0805_10V4Z
1000P_0402_50V7K
0.1U_0402_16V4Z
<20>
1
C779
2
ACES_88020-12101
CONN@
@ C821
2 100P_0402_50V8J
10K_0402_5%
HDA_BITCLK_MDC
13
14
15
16
17
18
1
C778
2
GND
GND
GND
GND
GND
GND
+3VS
Q85
SI2301BDS-T1-E3_SOT23-3
1 R495
2HDA_SDIN1_MDC
33_0402_5%
R645
+3VS
HDA_SYNC_MDC
HDA_SDIN1
HDA_RST#_MDC
+3VS
<20>
<20>
<20>
2
4
6
8
10
12
TP_CLK <33>
TP_DATA <33>
+5V_TP
0_0603_5%
2
3
2
4
6
8
10
12
TP_CLK
TP_DATA
@ C820
100P_0402_50V8J 2
Max 0.5A
R235
1
JP25
1
3
5
7
9
11
1
2
3
4
9/20
SP01000KC00/SP01E000900
11/01 update
1
3
5
7
9
11
1
2
3
4
G1
G2
ACES_85201-04051
CONN@
+5VALW
HDA_SDOUT_MDC
<33>
5
6
9/20 SP01000J100
9/20 STANDOFF (H= 5.0 mm) ES000000800
<20>
TP_BTN#
<33>
@ D31
PSOT24C_SOT23-3
JP37
ON/OFF#
SW2
SMT1-05_4P
SW1
SMT1-05-A_4P
1
2
3
4
4
6
5
2
1
1
ON/OFF#
2
ON/OFFBTN_LED# 3
4
@ C819
0.1U_0402_16V4Z
R1038
@ 10K_0402_5%
5
6
JP1
11/22 update
+5VALW_LED
BTN
TP_DATA
TP_CLK
Max 0.5A
+5V_TP
M/B TO TP/B
+3VALW
TP ON/OFF
2
2
HT-F196BP5_WHITE
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
E
34
of
48
DOCK@
C831
1000P_0402_50V7K
<16> RED_L
<16> GREEN_L
<16> BLUE_L
<16> D_DDCDATA
<16> D_DDCCLK
<16> D_HSYNC
<16> D_VSYNC
<20> USB20_N3
<20> USB20_P3
D_DDCDATA
D_DDCCLK
D_HSYNC
D_ VSYNC
USB20_N3
USB20_P3
09/19 update
DOCK_PWR_ON Spec
0V = Notebook S4/S5, Dock off
2.5V = Notebook S3, Dock on
4V = Notebook S0, Dock on
<25>
<25>
<25>
<25>
PJP5
1
B+
DOCK@
DOCK_PWR_ON
R588
10K_0402_5%
DOCK@
DOCK@
C844
1000P_0402_50V7K
H33
@ H_2P8
C942
<33>
H35
@ H_2P8
C
Q149
@ MMBT3904_NL_SOT23-3
DOCK_LOUT_C_L
R646
1
2
@ 0_0402_5%
DOCK@ 1
C944
R992
SPDIFO_L
C943
DOCK@ C945
1
2
2
B
1
2
DOCK@ 0_0603_5%
2
2
DOCK@ 220P_0402_50V7K DOCK@ 220P_0402_50V7K
SPDIF_OUT
<28>
0.1U_0402_16V7K
R573
DOCK@ 110_0402_5%
220P_0402_50V7K
R647
1
2
DOCK@ 220_0402_5%
Q33
2N7002_SOT23-3
DOCK@
09/29 update
R566
47K_0402_5%
DOCK@
H34
@ H_2P8
R976
@ 33_0402_5%
DOCK_LOUT_C_R
SPDIF
+1.5VS
MIC_Dock
H36
@ H_2P8
<28>
DOCK_MIC_R
<28>
DOCK_MIC_L
DOCK@
L94
DOCK@ R942 10K_0402_5%
FCM1608KF-601T02_2P
DOCK_MIC_R_C
2
1 DOCK_MIC_R_R 1
2
DOCK@ R943 10K_0402_5%
DOCK_MIC_L_C
2
1 DOCK_MIC_L_R
1
2
FCM1608KF-601T02_2P
DOCK@
L93
1
1
DOCK@ R980
1.21K_0402_1%
10/09 updateDOCK@ C921
DOCK@ C922
2 220P_0402_50V7K
220P_0402_50V7K 2
DOCK@ R944
1.21K_0402_1%
H41
@ H_2P8
H40
@ H_2P8
H39
@ H_2P8
H37
@ H_2P8
H32
@ H_2P8
1 1
DOCK@
C843
1000P_0402_50V7K
2
3
DOCK_VOL_UP#
DOCK_VOL_DWN#
+DOCKVIN
R_VOL_DWN#
2
1
1
2
G
1
CONA#
DOCK@
MUTE_LED <33>
DOCK_SLP_BTN# <33>
JACK_DET# <28,29>
DOCK_VOL_UP# <33>
DOCK_VOL_DWN# <33>
R565
10K_0402_5%
DOCK@
CIR_ IN
CIR_IN <29,33>
DOCK_PWR_ON
MUTELED
1
2
DOCK_SLP_BTN# DOCK@ R591
1K_0402_5%
JACK_DET#
R_VOL_UP#
DOCK@ R567 1
2 200_0402_5%
R_VOL_DWN#
DOCK@ R568 1
2 200_0402_5%
SPDIFO_L
AUDIO_OGND
DOCK_LOUT_C_R
DOCK_LOUT_C_R <29>
DOCK_LOUT_C_L
DOCK_LOUT_C_L <29>
DOCK_MIC_R_C
DOCK_MIC_L_C
AUDIO_IGND
DOCK_PRESENT
L
R_VOL_UP#
+3VL_EC
R572 1K_0402_5%
T51
T52
T53
DOCK_PRESENT
PAD
PAD
PAD
41
42
43
44
11/05 update
11/14 update
2
1
Q36
2N7002_SOT23-3
DOCK@
GND
GND
GND
GND
TV_LUMA_L
TV_CRMA_L
TV_COMPS_L
CONN@ FOX_QL1122L-H212AR-7F
DAN202U_SC70
2
G
SYSON#
<36,42>
GND
GND
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
PAD-OPEN 2x2m
1
45
46
Digital gnd
TV Luma
TV chroma
TV composite
TV ground
CIR input
PWR_ON
Mute_LED
Sleep Botton
Jack Detect
VOL_up
VOL_down
SPDIF
Audio Output gnd
Right headphone
Left headphone
Mic_Right
Mic_Left
Mic gnd
Dock_present
+5VS
+3VALW
DOCK@ D43
2
2
1K_0402_5%
2
1K_0402_5%
DOCK@
CRT_Red
CRT_Green
CRT_Blue
DDC_DATA
DDC_Clock
Hsync
Vsync
USBUSB+
Digital gnd
MDI3MDI3+
MD2IMDI2+
MDI1MDI1+
MDI0MDI0+
Battery out
Battery out
1
R586
1
R585
RJ45_MIDI1RJ45_MIDI1+
RJ45_MIDI0RJ45_MIDI0+
+V_BATTERY
RJ45_MIDI1RJ45_MIDI1+
RJ45_MIDI0RJ45_MIDI0+
38
40
34
36
30
32
26
28
22
24
18
20
14
16
10
12
6
8
2
4
H54
@ H_3P3X0P6N
<28>
Q100
2
G
DOCK@ 2N7002_SOT23-3
S
DOCK@
Close
Q18
2N7002_SOT23-3
to CODEC U27
C978
1
R913
DOCK@ 47K_0402_5%
2
G
2
B
2
SENSE_B#
1
DOCK@ Q16
MMBT3904_NL_SOT23-3
DOCK@
R912
1
2
10K_0402_5%
DOCK_MIC_L_C
H52
H53
@ H_1P5N @ H_3P3X0P6N
DOCK@ 1U_0603_10V6K
Date:
l.c
ho
DOCK CONN
Rev
0.2
f@
ai
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
35
he
2007/08/02
Issued Date
tm
Security Classification
11/09 update
om
H55
H51
@ H_5P6N @ H_6P0X5P0N
2
1
H48
@ H_3P3
DOCK@
R915
10K_0402_5%
1
R914
DOCK@
10K_0402_5%
H46
@ H_4P2
H44
@ H_4P2
H47
@ H_3P3
H43
@ H_4P2
H42
@ H_2P8
+3VS
of
48
DIM LED
+5VALW_LED
Q32
PJP7
RUNON
1U_0402_6.3V4Z
RUNON
2 R152
1
330K_0402_5%
B+
D
C834
Q17
SUSP
2
2N7002_SOT23-3
G
S
DIM_LED#
C1026
C836
0.1U_0402_16V4Z
1
C1024 4.7U_0805_10V4Z
1U_0402_6.3V4Z
SI4800BDY_SO8 RUNON_S4
2 R956
1
330K_0402_5%
1
D
C1025
Q138
B+
<33>
DIM_LED
DIM_LED
C840
2
C1023
1
2
3
4
Q51
2N7002_SOT23-3
2
G
1
4.7U_0805_10V4Z
R587
10K_0402_5%
C838
+5VS_LED
SYSON#
2
G
2N7002_SOT23-3
Q166
PJP8
1
+5VS
SI2301BDS-T1-E3_SOT23-3
4.7U_0805_10V4Z
1
2
3
4
SI4800BDY_SO8
SI4800BDY_SO8
C864
S
S
S
G
0.01U_0402_25V7K
1U_0402_6.3V4Z
C839
D
D
D
D
4.7U_0805_10V4Z
8
7
6
5
S
S
S
G
Q14
4.7U_0805_10V4Z
D
D
D
D
C835
C833
1
2
3
4
0.01U_0402_25V7K
Q35
8
7
6
5
2
PAD-OPEN 2x2m
10/8 update
1 R50
2
@ 0_0603_5%
Q137
8 D
S
7 D
S
6 D
S
5 D
G
4.7U_0805_10V4Z
1
+5VS
+5VALW
+3V
+3VALW
+3VS
+3VALW TO +3V
+3VALW
+5VALW
+3VALW TO +3VS
+5VALW TO +5VS
SI2301BDS-T1-E3_SOT23-3
1
1
PAD-OPEN 2x2m
C837
Q12
VLDT_EN#
2
2N7002_SOT23-3
G
S
09/13 update
1
C1029
RUNON_S4
2
+1.2V
Q140
2N7002_SOT23-3
R598
100K_0402_5%
EC_ON#
SYSON# 2
G
S
Discharge circuit
Q44
2N7002_SOT23-3
2
1
S 2N7002_SOT23-3
EC_ON#
Q41
@ 470_0805_5%
SYSON# 2
G
1
Q37
S 2N7002_SOT23-3
VLDT_EN#2
G
2
G
EC_ON
R368
Q48
S 2N7002_SOT23-3
2
G
1
SUSP
Q46
1
3
S 2N7002_SOT23-3
<33,39>
+1.2VALW
R284
470_0805_5%
R280
470_0805_5%
R279
470_0805_5%
R239
470_0805_5%
+1.8V
2
+1.2V_HT
2
+1.8VS
+5VS
2
G
+5VL
R958
470_0805_5%
Q141
2N7002_SOT23-3
SYSON# 2
G
SUSP
+3V
R957
470_0805_5%
09/29 update
Q42
2
G
@ 2N7002_SOT23-3
09/13 update
+1.1VS
<35,42>
SYSON#
R597
100K_0402_5%
SYSON#
SUSP
100K_0402_5%
SUSP
<42>
<13>
S 2N7002_SOT23-3
SUSP
Q52
2
G
<26,33,34,40>
SYSON
S 2N7002_SOT23-3
Q38
SYSON 2
G
2N7002_SOT23-3
Q50
2
G
1
D
S 2N7002_SOT23-3
SUSP
1
1
Q49
S 2N7002_SOT23-3
R294
470_0805_5%
SYSON# 2
G
Q47
2
G
R596
100K_0402_5%
R293
470_0805_5%
R292
470_0805_5%
1
1
SUSP
4
R595
R288
470_0805_5%
+1.5VS
+0.9V
Q39
2
G
2N7002_SOT23-3
SUSP#
<26,28,33,38,41> <33>
09/13 update
Compal Secret Data
Security Classification
2007/08/02
Issued Date
FM1
1
FM2
1
FM3
1
CF1
1
A
CF2
1
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CF3
+5VL
+3VS
+5VL
+5VL
09/13 update
Title
VLDT_EN#
VLDT_EN
VLDT_EN#
1
2
G
Q13
2N7002_SOT23-3
B+
4.7U_0805_10V4Z
1U_0402_6.3V4Z
Q139
2
0.01U_0402_25V7K
C1028
SUSP
1U_0402_6.3V4Z
2 R233
1
330K_0402_5%
D
C849
C1027
1
2
3
B+
8
7
6
5
R138 2
1
330K_0402_5%
4.7U_0805_10V4Z
1.8VS_ENABLE
C847
C862
4.7U_0805_10V4Z
C842
1U_0402_6.3V4Z
1
2
3
C846
8
7
6
5
+1.2V
10/8 update
1 R51
2
@ 0_0603_5%
IRF8113PBF_SO8
C841
10U_0805_10V4Z
+1.2VALW
C848
4.7U_0805_10V4Z
1
2
3
+1.2V_HT
Q11
IRF8113PBF_SO8
8
7
6
5
+1.2VALW
Q4
IRF8113PBF_SO8
+1.8VS
0.01U_0402_25V7K
+1.8V
11/06 update
+1.2VALW TO +1.2V
+1.2VALW TO +1.2V_HT
4.7U_0805_10V4Z
+1.8V TO +1.8VS
C1069
0.1U_0402_16V4Z
DIM_LED#
VLDT_EN 2
G
Q40
2N7002_SOT23-3
Rev
0.2
Sheet
36
of
48
BATT1
+3VALW
PQ3
TP0610K-T1-E3_SOT23-3
499K_0402_1% 340K_0402_1%
PR4 1
PR1 1
2
2
BATT
PJP2
8
7
6
5
4
3
2
1
9
10
EC_SMD
EC_SMC
PD2
@SM05_SOT23
105K_0402_1%
PR6 1
2
0
-
PU1A
LM358ADT_SO8
PR5
10K_0402_5%
2
1
BATT_OVP <33>
PL3
HCB2012KF-121T50_0805
1
2
1
2
PL4
HCB2012KF-121T50_0805
BATT
1
2
PC8
1000P_0402_50V7K
PC9
0.01U_0402_50V4Z
8
7
6
5
4
3
2
1
GND
GND
VMB
PC5
1000P_0402_50V7K
2
1
PC4
100P_0402_50V8J
2
1
PJSOT24C_SOT23-3
PC3
1000P_0402_50V7K
PD1
2
2
1
PC2
100P_0402_50V8J
PJP1
ADPIN
PL2
SMB3025500YA_2P
2
1
3
PL1
SMB3025500YA_2P
1
2
+DOCKVIN
5
4
3
2
1
VIN
RLZ3.6B_LL34
1
2
PR3
10K_0402_5%
0.01U_0402_25V7K
PC6
5
4
3
2
1
2
ADP_SIGNAL
@1000P_0402_50V7K
+5VALW
PD4
PR2
10K_0402_5%
ACES_88334-057N
PC12
1
PR8
100_0402_5%
2 1
ADP_ID <33>
0.01U_0402_25V7K
PC1
2
1
AC_LED <38>
SUYIN_200275MR008GXOLZR
PR7
47K_0402_1%
1
2
+5VS
PH1
PR15
150K_0402_1%
2
BATT_TEMP
PQ1
SSM3K7002FU_SC70-3
2
G
PU1B
LM358ADT_SO8
PR12
2.55K_0402_1%
PC11
1000P_0402_50V7K
PC10
0.22U_0603_10V7K
+3VL
2
PR11
150K_0402_1%
+5VALW
PR17
1K_0402_5%
2
<38>
PR16
6.49K_0402_1%
1
2
ENTRIP1 <39>
PR10
15K_0402_1%
1
2
<32,33,34>
SMB_EC_CK1
1
2
PR9
10K_0402_5%
BAT_ID
SMB_EC_CK1
10KB_0603_1%_TH11-3H103FT
<32,33,34>
SMB_EC_DA1
SMB_EC_DA1
+3VL
PD3
@SM24.TC_SOT23-3
PR14
100_0402_5%
PR13
100_0402_5%
CPU
ENTRIP2 <6,39>
<33>
PQ2
SSM3K7002FU_SC70-3
2
G
l.c
ai
DC Connector/CPU_OTP
Date:
Rev
0.1
f@
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
37
he
2007/08/02
Issued Date
tm
Security Classification
om
of
48
P4
B+
BATT
VIN
P2
PQ102
AM4835EP-T1-PF_SO8
25
12
VADJ
REGN
24
RE GN 2
LODRV
23
DL _CHG
EXTPWR
1
2
DPMDET
3
2
1
21
1
1
20
19
18
BAT_ID
<37>
PC122
@0.1U_0603_25V7K
<33>
IREF
PR121
200K_0402_1%
PR122
681K_0402_1%
1
2
PC124
0.1U_0603_25V7K
BATT
PR120
2
1
133K_0402_1%
17
16
CELLS
SRP
SRN
BAT
IADAPT
PR123
1M_0402_5%
1
2
@47K_0402_5%
PR119
2
G
PC123
0.1U_0402_10V7K
BQ24740VREF
D
PQ111
SSM3K7002FU_SC70-3
PC118
0.1U_0402_10V7K
1U_0603_10V6K
PC120
0.22U_0603_10V7K
2
1
<33> ADP_I
PC119
PR117
100K_0402_5%
1
2
PC121
100P_0402_50V8J
2
1
PR118
10K_0402_5%
1
2
Charge Detector
BATT
PR112
0.015_1206_1%
1
2
5
6
7
8
PQ110
AO4466_SO8
22
IADAPT
15
PR116
39K_0402_5%
PGND
SRSET
ISYNSET
14
PQ106
DTC115EUA_SC70-3
4
PR115
100K_0402_1%
5
6
7
8
PL102
10U_LF919AS-100M-P3_4.5A_20%
1
2
13
1
2
PC105
4.7U_0805_25V6-K
1
2
PD102
VA DJ
P2
BQ24740VREF
PR124
1K_0402_5%
1
2
VIN
VIN
PACIN
1
8
P
G
2
1
LM393DG_SO8
PR134
10K_0402_5%
PD103
RLZ4.3B_LL34
S
FSTCHG#
1
2
G
FSTCHG
STD_ADP <33>
PR136
49.9K_0402_1%
1
2
P2
PQ113
SSM3K7002FU_SC70-3
3
<33>
1.24VREF
PR133
10K_0603_0.1%
PU102B
PU102A
LM393DG_SO8
PQ112
SSM3K7002FU_SC70-3
2
G
PC126
0.047U_0402_16V7K
PR127
10K_0402_1%
PR135
10K_0603_0.1%
PR132
100K_0402_5%
2
1
1
-
PR130
2.15K_0402_1%
1
2
PR128
10K_0402_5%
2
1
1
2
CH GEN#
PC125
0.1U_0603_25V7K
PR129
10K_0402_1%
2
1
1
PR131
133K_0402_1%
PR126
100K_0402_1%
+3VL
AC_IN <33,39>
+3VL
PR125
47_1206_5%
VIN
<33>
PC116
4.7U_0805_25V6-K
PH
ACOFF
PQ108
AO4466_SO8
3
2
1
VDAC
11
PC115
4.7U_0805_25V6-K
2
1
DH_CHG
LX_CHG
S PQ114
SSM3K7002FU_SC70-3
26
2
G
HIDRV
PU101
BQ24740RHDR_QFN28_5X5
VREF
PC111
0.1U_0402_10V7K
1
2
4
BST_CHG
PR139
100K_0402_5%
1
2
PC114
4.7U_0805_25V6-K
27
RLS4148_LL34-2
PC117
1U_0603_10V6K
+3VLP
PC113
4.7U_0805_25V6-K
2
1
28
BTST
VCTRL
PC104
4.7U_0805_25V6-K
1
2
2
1
CHGEN
ACP
ACN
4
LPMD
ACDET
PVCC
AGND
<33>
<37> AC_LED
PA CIN
PC110
1U_0805_25V6K
1
2
IADSLP
VIN
PR105
10K_0402_5%
CHG_B+
29
PR103
47K_0402_5%
1
2
A COFF#
PR108
10_1206_5%
1
2
TP
8
7
6
5
CHG_B+
+3VL
PD101
RLS4148_LL34-2
PR114
@0_0402_5%
1
2
PC103
4.7U_0805_25V6-K
1
2
PC108
PC109
@0.1U_0603_25V7K
9
10
PR113
143K_0402_1%
PC102
1U_0603_6.3V6M
1
2
BQ24740VREF
1U_0603_6.3V6M
PQ109
SSM3K7002FU_SC70-3
3
1
LPREF
PR110
0_0402_5%
1
2
SUSP#
2
G
1
2
3
PL101
HCB2012KF-121T50_0805
2
2
1
PR111
3K_0402_1%
1
2
A COFF#
CH GEN#
PC112
1
2
PA CIN
0.1U_0603_25V7K
1
PC107
@0.01U_0402_16V7K
PR109
<26,28,33,36,41>
150K_0402_5%
PQ107
SSM3K7002FU_SC70-3
ACSET
ACSET
AC_SET
2
1
PR106
200K_0402_5%
PC106
0.22U_0603_16V7K
2
1
1
2
2
G
ACDET
PR104
0_0402_5%
1
2
DTA144EUA_SC70-3
PQ104
PQ105
DTC115EUA_SC70-3
PR102
0.012_2512_1%
1
2
8
7
6
5
<33>
1
2
3
PR101
47K_0402_5%
1
2
PC101
47P_0402_50V8J
PR107
47K_0402_1%
1
2
PQ103
AM4835EP-T1-PF_SO8
1
2
3
8
7
6
5
PQ101
AM4835EP-T1-PF_SO8
S
PU103
4
ACDET
22P_0402_50V8J
2
100K_0402_1%
PR138
PC127
PR137
20K_0402_1%
CATHODE
NC
NC
1.24VREF
ANODE
APL1431LBBC-TR_SOT23-5
Security Classification
Issued Date
2007/05/29
Deciphered Date
2008/05/29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
REF
Title
Size
Document Number
Rev
0.1
LA-3941P
Date:
Sheet
38
of
48
2VREF_51125
PR303
20K_0402_1%
1
2
PR304
20K_0402_1%
2
22
DRVH1
21
11
LL2
LL1
20
LX_5V
12
DRVL2
DRVL1
19
LG_5V
5
6
7
8
+5VALWP
1
PR316
@4.7_1206_5%
+3VL
PR317
100K_0402_5%
3
2
1
PC319
@22U_0805_6.3V6M
PC310
150U_D_6.3VM
<41>
PC311
10U_0805_10V6K
3/5V_OK
PC315
@680P_0603_50V8J
PQ304
FDS6690AS_NL_SO8
VL
PR311
620K_0402_5%
1 2
PU301
TPS51125RGER_QFN24_4X4
VCLK
18
VIN
VREG5
17
16
EN0
PL303
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
1
VBST1
DRVH2
3
2
1
VBST2
13
PC313
4.7U_0805_25V6-K
VFB1
VREF
TONSEL
ENTRIP1
4
PR308
PC308
0_0402_5% 0.1U_0402_10V7K
BST_5V 1
PR310
2 1
2
0_0402_5%
UG_5V
1
2
PC314
@680P_0603_50V8J
23
1 2
24
10
PR315
@4.7_1206_5%
VO1
PGOOD
PQ302
AO4466_SO8
5
6
7
8
VREG3
VO2
GND
UG_3V
14
1
PC309
220U_6.3VM_R15
1
2 1
2
0_0402_5%
PC307
0.1U_0402_10V7K
LX_3V
LG_3V
+3VALWP
P PAD
15
PL302
4.7UH_SIQB74B-4R7PF_4A_20%
2
1
BST_3V
VFB2
25
PR307
PR309
0_0402_5%
1
2
6
SP8K10S-FD5_SO8
PC306
10U_0805_6.3V6M
ENTRIP2
8
7
6
5
SKIPSEL
1G
1S/2D
1S/2D
1S/2D
PR306
133K_0402_1%
2
D1
D1
G2
S2
1
2
PC303
4.7U_0805_25V6-K
PQ301
1
2
3
4
UG1_3V
PC301
2200P_0402_50V7K
2
1
PR305
174K_0402_1%
1
B++
PC305
4.7U_0805_25V6-K
2
1
+3VLP
2
PC316
@0.1U_0402_25V4K
2
1
PR302
30.9K_0402_1%
2
PC304
2200P_0402_50V7K
2
1
PL301
HCB2012KF-121T50_0805
ENTRIP1
B++
B+
ENTRIP2
PR301
13.7K_0402_1%
1
PC317
@0.1U_0402_25V4K
2
1
PC302
0.22U_0603_10V7K
B++
ENTRIP1
<6,37>
ENTRIP2
<37>
PC312
0.1U_0603_25V7K
2
G
D
PQ305
SSM3K7002FU_SC70-3
2VREF_51125
PQ306
SSM3K7002FU_SC70-3
2
G
PJP301
VL
PQ307
SSM3K7002FU_SC70-3
2
G
+5VALW
+3VALW
1
PAD-OPEN 2x2m
PAD-OPEN 4x4m
PJP303
1
+3VALWP
+5VL
VL
PJP304
PAD-OPEN 4x4m
EC_ON <33,36>
1
PAD-OPEN 2x2m
+5VALWP
PR314
100K_0402_5%
2
PC318
0.022U_0603_25V7K
<33,38> AC_IN
PQ308
SSM3K7002FU_SC70-3
1
2
2
PR318
G
330K_0402_1%
PR313
100K_0402_5%
2
+3VL
+3VLP
PJP302
3.3VALWP/5VALWP
Date:
l.c
ai
Rev
0.1
f@
tm
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
39
he
2007/08/02
Issued Date
ho
Security Classification
om
of
48
PR401
0_0402_5%
1
2
PL401
VOUT
V5FILT
VFB
13
DH_1.8V
LL
12
LX_1.8V
TRIP
11
V5DRV
10
PR410
1
2
0_0402_5%
3
2
1
DRVH
DH_1.8V_1
PQ401
AO4466_SO8
+5VALW
2
PR406
15.4K_0402_1%
1
2
4.7U_0805_25V6-K
PC404
2
1
PR407
@4.7_1206_5%
1
+
2 2
PC415
4.7U_0805_10V6K
DRVL
15
PGND
TPS51117RGYR_QFN14_3.5x3.5
DL_1.8V
3
2
1
1
2
14.3K_0603_0.1%
PC406
@680P_0402_50V7K
2
PL402
2.2UH_PCMC063T-2R2MN_8A_20%
1
2
5
6
7
8
PR408
+1.8VP
PGOOD
PC409
1U_0603_10V6K
B+
14
2
PC412
@680P_0603_50V7K
PC408
220U_D2_4VY_R25M
TP
TON
PC402
0.1U_0402_10V7K
HCB1608KF-121T30_0603
1
2
2
1
0_0402_5%
VBST
2
PR405
EN_PSV
PU401
PR404
255K_0402_1%
1
2
4.7U_0805_25V6-K
PC403
2
1
BST1_1.8V 1
PR402
0_0402_5%
PR403
316_0402_1%
+1.8VP
BST_1.8V
1
GND
5
6
7
8
1+5VALW
+5VALW
@0.1U_0402_25V4K
PC414
2
1
1.8V_B+
PC401
@1000P_0402_50V7K
2200P_0402_50V7K
PC405
<26,33,34,36> SYSON
+1.8VP
PQ402
FDS6690AS_NL_SO8
1
2
PC413
@10P_0402_50V8J
PR409
10K_0603_0.1%
PJP401
+1.8VP
+1.8V
PAD-OPEN 4x4m
Security Classification
Issued Date
2007/05/29
Deciphered Date
2008/05/29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Size
Document Number
Rev
0.1
LA-3941P
Date:
Sheet
40
of
48
PR501
11.5K_0402_1%
1
2
PR517
10_0402_5%
PR502
24.9K_0402_1%
PR503
18.7K_0402_1%
PR504
11.5K_0402_1%
+1.2VALWP
B+++
B+
PL502
HCB2012KF-121T50_0805
2
1
2
0_0402_5%
1
PR508
8
7
6
5
10
LX_1.1V
11
LL2
LG_1.1V
12
DR VL2
5
6
7
8
VO1
VFB1
23
VBST2
VBST1
22
BST_1.2V
DR VH2
DR VH1
21
UG_1.2V
LL1
20
LX_1.2V
DR VL1
19
LG_1.2V
PR507
0_0402_5%
2
1
2
PC507
0.1U_0402_10V7K
1
2
UG1_1.2V
1
PR509
0_0402_5%
1 2
PGND1
TRIP1
18
PR510
17.8K_0402_1%
PR512
33K_0402_5%
2
+5VALW
1
2
PC514
1U_0603_10V6K
PR514
3.3_0402_5%
PC513
@0.1U_0402_10V7K
PC512
0.1U_0402_16V7K
PC515
4.7U_0805_10V6K
PJP501
1
3/5V_OK <39>
+1.1VSP
<26,28,33,36,38> SUSP#
PC520
@680P_0603_50V8J
PR513
0_0402_5%
2
+1.2VALWP
3
2
1
PR511
19.1K_0402_1%
1
2
PR516
@4.7_1206_5%
4
PQ504
AO4466_SO8
PQ503
FDS6690AS_NL_SO8
+1.2VALWP
PL503
3.3UH_SIQB74B-3R3PF_5.9A_20%
1
2
TPS51124RGER_QFN24_4x4
17
V5FILT
V5IN
16
15
TRIP2
PGND2
13
2
3
PC516
@0.1U_0402_25V4K
2
1
UG_1.1V
GND
24
EN1
5
6
7
8
BST_1.1V
TONSEL
VO2
PGOOD1
14
PC519
@680P_0603_50V8J
1
2
3
EN2
1 2
PR515
@4.7_1206_5%
PGOOD2
PC509
4.7U_0805_6.3V6K
2
1
PC508
220U_D2_4VY_R25M
+1.1VSP
UG1_1.1V
PL501
2.2UH_PCMC063T-2R2MN_8A_20%
2
1
PC511
220U_D2_4VY_R25M
1
2
3
PC506
PR506
0.1U_0402_10V7K
0_0402_5%
2
1 2
1
PQ502
AO4466_SO8
P PAD
3
2
1
AO4466_SO8
+1.1VSP
PU501
25
PQ501
VFB2
PC503
@0.022U_0603_25V7K
8
7
6
5
VCCP_POK
PC510
4.7U_0805_6.3V6K
1
2
+1.1VSP
PC505
2200P_0402_50V7K
2
1
PR505
0_0402_5%
PC518
@0.1U_0402_25V4K
2
1
PC502
2200P_0402_50V7K
2
1
1
2
PC501
4.7U_0805_25V6-K
2
1
PC517
4.7U_0805_25V6-K
B+++
PC504
4.7U_0805_25V6-K
2
1
+1.1VSP
PR518
0_0402_5%
1
+1.1VS
B+++
PJP502
2
+1.1VS
+1.2VALWP
PAD-OPEN 4x4m
+1.2VALW
PAD-OPEN 4x4m
PJP503
4
+1.1VSP
+1.1VS
1.1VSP/1.2VALWP
Date:
l.c
ai
Rev
0.1
f@
tm
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Sheet
E
xa
2008/08/02
Deciphered Date
41
he
2007/08/02
Issued Date
ho
Security Classification
om
PAD-OPEN 4x4m
of
48
+1.8V
+1.8V
PU603
+5VALW
NC
TP
PC603
1U_0603_16V6K
G2992F1U_SO8
NC
VREF
NC
VOUT
NC
TP
+5VALW
PR606
1K_0402_1%
VOUT
VCNTL
GND
PC613
10U_0805_10V4Z
VIN
2
1
NC
VREF
5
1
NC
VCNTL
PC609
@10U_0805_10V4Z
GND
VIN
1
PR601
1K_0402_1%
2
1
2
PC601
10U_0805_10V4Z
PC602
@10U_0805_10V4Z
PU601
PC612
1U_0603_16V6K
G2992F1U_SO8
PR608
0_0402_5%
PC606
@0.1U_0402_16V7K
2
G
+1.5VSP
1
2
PR607
5.1K_0402_1%
2
<36> SUSP
1
PC605
10U_0805_6.3V6M
PQ602
SSM3K7002FU_SC70-3
2
G
+0.9VP
PR604
@0_0402_5%
PR603
1K_0402_1%
D
2
<36> SUSP
2
1
PC604
0.1U_0402_16V7K
PQ601
SSM3K7002FU_SC70-3
2
2
PR602
0_0402_5%
2
1
PC611
0.1U_0402_16V7K
VREF1.5V
<35,36> SYSON#
PC614
10U_0805_6.3V6M
PC610
@0.1U_0402_16V7K
PU602
APL5508-25DC-TRL_SOT89-3
PAD-OPEN 3x3m
PJP603
+1.5VSP
+1.5VS
+2.5VS
IN
OUT
+2.5VSP
GND
1
PR605
@150_1206_5%
2
+0.9V
PC607
1U_0603_6.3V6M
+0.9VP
+3VS
PC608
4.7U_0805_6.3V6K
PJP601
PAD-OPEN 3x3m
PJP602
+2.5VSP
2
PAD-OPEN 3x3m
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.1
Sheet
42
of
48
8
7
6
5
1
2
UGATE NB1
PHASE NB
LGATE NB
PC204
4.7U_0805_25V6-K
2
PR205
2_0402_5%
1
2
1
2
PC249
3300P_0402_50V7K
2
1
PC250
1800P_0402_50V7K
2
1
PC211
@47U_25V_M
PC248
3300P_0402_50V7K
2
1
PC214
2200P_0402_50V7K
2
1
PC213
4.7U_0805_25V6-K
2
1
PC212
4.7U_0805_25V6-K
2
1
PC235
4.7U_0805_25V6-K
2
1
D
D
D
D
PC234
4.7U_0805_25V6-K
2
1
5
6
7
8
G
S
S
S
4
3
2
1
PR221
14K_0402_1%
2
1
PR220
4.7_1206_5%
1 2
2
PC218
470P_0603_50V8J
3
2
1
3
2
1
1 2
AO4456_SO8
3
2
1
PQ208
3
2
1
PQ207
ISP 1
AO4456_SO8
2
2
PC222
2200P_0402_50V7K
2
1
PC221
4.7U_0805_25V6-K
2
1
1
ISP 1
1
PR238
54.9K_0402_1%
2
1
PJP201
PC232
1200P_0402_50V7K
PR240
1K_0402_1%
2
1
1
+CPU_CORE_1
PL204
0.36UH_PCMC104T-R36MN1R17_30A_20%
PR233
6.65K_0603_1%
1
2
PC229
0.1U_0603_25V7K
PC231
180P_0402_50V8J
PR236
6.81K_0402_1%
PC220
4.7U_0805_25V6-K
2
1
PC226
470P_0603_50V8J
PC230
1000P_0402_50V7K
2
1
PR231
14K_0402_1%
2
1
1
PR229
4.7_1206_5%
+CPU_CORE_1
PC236
4.7U_0805_25V6-K
2
1
PC237
4.7U_0805_25V6-K
2
1
PC240
@0.1U_0402_25V4K
2
1
5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1
5
6
7
8
5
6
7
8
PC224
0.22U_0603_10V7K
+CPU_CORE_0
+CPU_CORE_1
PAD-OPEN 4x4m
PJP202
PR243
255_0402_1%
2
1
+CPU_CORE_0
+CPU_CORE_1
PAD-OPEN 4x4m
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
om
4700P_0402_25V7K
PC233
tm
1
PR241
0_0402_5%
UGATE1_1
49
TP
1
PR228
2.2_0603_5%
PR226
1
2
0_0603_5%
2
1
2
ho
CPU_VDD1_FB_H
Rev
0.1
f@
<6>
1
ISP 0
in
1
PR239
0_0402_5%
CPU_VDD1_FB_L
<6>
PC242
2 1000P_0402_50V7K
PC219
0.1U_0603_25V7K
Sheet
E
xa
PQ205
AO4456_SO8
PR217
6.65K_0603_1%
1
2
43
he
CPU_VDD0_FB_L
+CPU_CORE_0
CPU_B+
2
2
<6>
1
PR237
0_0402_5%
5
6
7
8
5
6
7
8
BOOT0
UGATE_NB
PHASE_NB
ISP1
ISN1
24
23
VW1
22
21
20
18
VSEN1
COMP1
25
BOOT1
FB1
UGATE1
PC241
2 1000P_0402_50V7K
PC239
330P_0402_50V7K
2
1
1
2
2
BOOT_NB
PHASE NB
UGATE NB
37
38
39
LGATE NB
PGND_NB
LGATE_NB
OCSET_NB
RTN_NB
VSEN_NB
PHASE1
26
VDIFF1
27
UGATE1
PC215
1000P_0402_50V7K
1
BOOT_NB1 2
1
PR207
11.3K_0402_1%
1
43
44
45
PHASE1
COMP0
BOOT1
LGATE1
FB0
VW0
PQ204
AO4456_SO8
PQ206
SI4684DY-T1-E3_SO8
11
6.81K_0402_1%
1
PR235
0_0402_5%
FSET_NB
28
CPU_VDD0_FB_H
COMP_NB
29
PGND1
PR232
1
46
LGATE1
VDIFF0
1
2
PC228
1000P_0402_50V7K
<6>
VCC
OCSET
ISL6265IRZ-T_QFN48_6X6
+
2
PL203
LGATE0
10
12
54.9K_0402_1%
FB_NB
30
PC225
1
2
1200P_0402_50V7K
1
2
PC227
180P_0402_50V8J
48
VIN
PVCC
17
32
31
ISP0
PR230
RBIAS
1K_0402_1%
PGND0
LGATE0
16
ENABLE
RTN1
SVC
VSEN1
4700P_0402_25V7K
PR227
RTN0
255_0402_1%
33
15
95.3K_0402_1%
PC223
1
2
PHASE0
PHASE0
19
21K_0402_1%
UGATE0
UGATE0
RTN1
0.36UH_PCMC104T-R36MN1R17_30A_20%
2
1
1
2
0_0603_5%
PR219
36
SVD
VSEN0
UGATE0_1
2.2_0603_5% 0.22U_0603_10V7K
PR214
PC217
1
2 1
2
35
PWROK
ISN0
PR224
PC210
2.2U_0603_6.3V6K
PQ203
SI4684DY-T1-E3_SO8
BOOT0
VSEN0
PR225
SVC
PR223
+5VS
BOOT_NB
34
1
@1000P_0402_50V7K
PC244
2
1
@1000P_0402_50V7K
PC245
2
1
@1000P_0402_50V7K
PC246
1
@1000P_0402_50V7K
PC247
VR_ON
PL202
SMB3025500YA_2P
14
CPU_SVC
<33>
SVD
PGOOD
13
<6>
PR218
1
2
0_0402_5%
PR2221
2
0_0402_5%
CPU_SVD
OFS/VFIXEN
ISP 0
SB_PWRGD
<6>
+CPU_CORE_0
<6,20,33>
VGATE
PU201
47
PR216
10K_0402_1%
2
1
<33>
PR215
@10K_0402_5%
B+
CPU_B+
PR211
1_0603_5%
40
2
PR212
0_0402_5%
1
2
PR213
@0_0402_5%
1
2
PC206
0.1U_0603_16V7K
VSEN_NB
RTN0
+5VS
+3VS
41
PC216
0.1U_0603_25V7K
PC243
1000P_0402_50V7K
CPU_B+
RTN_NB
PR208
2_0402_5%
1
2
42
33P_0402_50V8K
PC209
2
1
PC207
0.1U_0402_16V7K
2
1
2
1
PR210
PC208
44.2K_0402_1% 1200P_0402_50V7K
+5VS
l.c
PC205
1000P_0402_50V7K
ai
1
PR209
0_0402_5%
PR204
22K_0402_1%
1
2
PR203
0_0402_5%
PR206
0_0402_5%
2
1
PC203
2200P_0402_50V7K
CPU_B+
1
2
3
VDD_NB_FB_L
1
2
3
<6>
PC202
220U_D2_4VY_R25M
1
2
VDD_NB_FB_H
PQ202
AO4466_SO8
PQ201
AO4466_SO8
8
7
6
5
10U_0805_6.3V6M
PC201
<6>
2
1
4.7UH_SIQB74B-4R7PF_4A_20%
PC238
470P_0402_50V7K
PL201
+CPU_CORE_NB
of
48
Title
Date Request
Owner
Issue Description
Rev.
Solution Description
37
DC Connector
/CPU_OTP
9/29
Compal
for Layout
41
1.1VSP/1.2VALWP
9/29
Compal
HW request
41
1.1VSP/1.2VALWP
9/29
Compal
HW request
Add PJP503
43
CPU_CORE
9/29
Compal
HW request
43
CPU_CORE
9/29
Compal
43
CPU_CORE
9/29
Compal
Add PJP201PJP202
38
Charger
9/29
Compal
37
10/08
Compal
for Layout
38
Charger
10/08
Compal
10
40
1.8VP
10/08
Compal
PWR request
11
41
1.1VSP/1.2VALWP 10/08
Compal
PWR request
Add PR517PR518
DC Connector
/CPU_OTP
12
37
13
37
14
43
15
37
DC Connector
/CPU_OTP
3.3VALWP/5VALWP
CPU_CORE
3.3VALWP/5VALWP
11/01
Compal
PWR request
Add PD4PC12
11/01
Compal
for Layout
11/02
Compal
EMI request
11/12
Compal
for Layout
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.1
Sheet
44
of
48
29
4
Audio
FAN
29
10/30
11/01
HW
HW
Speaker no sound
FAN Conn. not correct part
Speaker
11/01
HW
34
MDC
11/01
HW
8
9
11,35
11,21
TV_OUT
11/05
NB/SB Thermal 11/05
HW
HW
10
21,31
SB SATA
11/05
HW
11
21
SB SATA
11/05
HW
12
21
SB GPIO
11/05
HW
13
14
15
16
17
31
29
25
21,24
36
SB SATA
11/05
Audio HP OUT 11/05
LAN Transfermor11/05
SB SATA
11/06
DIM LED
11/06
HW
HW
HW
HW
HW
18
27
CardReader
HW
11/06
0 .2
2007/08/02
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
0 .2
0 .2
Security Classification
Issued Date
Title
om
4
5
HW
0 .2
l.c
16
ai
LAN
CRT
tm
25
0 .2
HW Changed-List History-1
ho
10/29
10/29
Rev.
Rev
0.2
f@
10/29
Solution Description
Update the LAN Design page and support circuit
in
25
Request
Issue Description
Owner
HW
Change LAN Chip U20 from Marvell 88E8042 to
Realtek RTL8102EL
HPQ
Add POE(Power Over Ethernet) design
Sheet
E
xa
1
1
Date
Title
LAN
45
he
Item Page#
of
48
Date
Request
Owner
HW
HW
CIC
HW
HW
Issue Description
Rev.
19
20
21
22
23
16
17
18
33
17
Title
CRT
LCD
LCD
KBC
WebCam
24
25
18
19,32
HDMI
11/09
SB-CLK-Debug 11/09
HW
HW
Remove R490(100K_0402)
0 .2
0 .2
26
27
28
29
30
31
25
18
6
33
35
26
LAN
HDMI
CPU
KBC
Holes
Mini-Card
11/09
11/09
11/09
11/09
11/09
11/09
HW
HW
HW
HW
ME
HW
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
32
33
33
27
KBC
CardReader
11/09
11/10
HW
HW
34
34
LED Function
11/10
HW
11/07
11/07
11/07
11/07
11/09
Solution Description
Change R491 from 200_0402 to 200_0805
Change Q43 from AOS3413 to SI2301
Remove R490(100K_0402)
Add R16 close to Q3.1 for H_THERMTRIP#
Add H_THERMTRIP# to U33.25
Del H49 H50 H38 H45 for M/E drawing change
0 .2
0 .2
HW
0 .2
11/13
HW
0 .2
11/13
11/13
HW
HW
11/13
HW
SB-GPIO
KBC-GPIO
11/10
11/11
HW
HW
37
6,31
CPU,FPR
11/13
38
11
NB
39
40
17
6,33
WebCam
CPU,KBC
41
18
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
0 .2
0 .2
Security Classification
21
33
Title
0 .2
35
36
0 .2
0 .2
HDMI
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
Rev
0.2
Sheet
46
of
48
11/13
HW
44
45
46
47
25
13
18
20
LAN
NB
HDMI
SB
11/13
11/13
11/13
11/13
HW
HW
HW
HW
48
SB,Cardreader
11/13
HW
49
50
51
20,21,
27
21,33
28,33
33
SB,KBC
Codec,KBC
KBC
11/13
11/13
11/13
HW
HPQ
HW
52
33
KBC
11/13
HW
53
34
Switch Design
11/13
HW
54
34
LED
11/14
HW
Audio-Dock
Holes
Multi-Bay
11/14
11/14
11/14
HPQ
ME
ME
58
59
60
61
62
63
33
20
33
35
33
28,29
Holes
SB
KBC
DOCK
K/B
AUDIO
11/14
11/16
11/16
11/16
11/16
11/18
ME
ATI
EC
EMC
HW
HPQ
29
AUDIO
11/19
HPQ
0 .2
0 .2
0 .2
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
0 .2
Security Classification
Issued Date
0 .2
Update JP2,JP9,JP10,JP11,JP20,JP40,JHDMI,JESAT,JCRT,
JDOCK Symbol
Add back H52 become H_1P5N; Del CF4
Title
0 .2
0 .2
0 .2
0 .2
64
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
4
0 .2
tm
29
29
4,24
HW Changed-List History-2
ho
55
56
57
0 .2
0 .2
0 .2
0 .2
Rev
0.2
f@
0 .2
om
SB,BIOS
l.c
21,32
0 .2
ai
43
in
Rev.
Solution Description
Sheet
E
xa
11/13
Request
Issue Description
Owner
HW
Reduce SB related design for Chip A12 and others
Date
47
he
Title
4 2 19.32 SB,BIOS
Item Page#
of
48
Title
13
NB
22
SB
22
SB
33,34 Function Board
69
70
71
72
73
74
75
76
77
23
31
34
33
6
19
26
28
10~13
65
1
Date
11/20
11/20
11/20
11/20
SB
11/20
BlueTooth
11/20
Power On Switch 11/22
KBC
11/22
CPU
11/22
SB
11/22
Express Card
11/22
Audio Codec
11/22
NB,
11/23
78 19
SB
11/23
79 22
SB
11/26
80 28
Codec
11/26
81 34
T/P
11/28
82 14
HDMI
11/28
83 15
CLK Gen.
11/28
84 28
Codec
11/28
8 5 20,27 SB,CardReader 11/28
86 32
BIOS
11/28
87 34
LED
11/28
88 19
SB
11/30
8 9 06,19, SB
11/30
23
90 33
KBC
11/30
91 32
BIOS
12/03
92 34
LED
12/03
Request
Issue Description
Owner
ATI
Design Change for NB A12 Version chip
Rev.
Solution Description
Remove U64,C1064,C1065,C1066,C1067,R1015,R1016,Q163,R1017.
Install L19, remove L95
0 .2
1
ATI
HW
HW
HW
HW
HW
HW
HW
HW
HW
HW
HW
HW
HW
HW
HW
ATI
HW
HW
HW
HW
HW
HW
ATI
HW
HW
HW
Change 32.768KHz Main Source Vendor become EPSON Change Y7 from SJ100001V00 to SJ132P7K220
Cancel Ext. BIOS reflash design because of +3VL erroe Add R221; Remove U30,R226,R228,C489
Remove Q156
Cancel G-Sensor INT2 LED function
0 .2
0 .2
0 .2
Reserve R555 for +5VALW_LED, add R554 for +3VL close to JP36.1
Reserve R1034 close to JP36.4,R1035 close JP36.5,Remove R1036
Add R513 PH to +3VS close to U33.19
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
0 .2
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.2
Sheet
48
of
48