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TECH II MID:
1.Explain (a)Petri-nets for states machine-basic concepts and properties (b) extended Petri-nets for parallel controllers. 2. Discuss about front end digital design tools for FPGAs and ASICs

3.Design a 4-bit counter using D flip-flops. Write code for mentor graphic EDA Tool FPGA Advantage for this design. 4. Explain the Mentor graphics EDA tool-FPGA advantage in designing a digital system. 5.a) What is meant by linked state machinery? Explain with an example. b) Write a brief note on state assignments FPGAs?
6.How would you implement a parallel adder with accumulator using an FPGA device?

7.Design a binary multiplier using shift register and parallel adder. Draw an ASM chart in one-Hot design.