PROGRAMMABLE MODULES SPECIFICATION OF PROGRAMMABLE COMBINATIONAL AND SEQUENTIAL MODULES 1. psa 2. rom 3.

. fpga THE WAY THE MODULES ARE PROGRAMMED NETWORKS OF PROGRAMMABLE MODULES EXAMPLES OF USES

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12 Programmable Modules

PROGRAMMABLE SEQUENTIAL ARRAYS (psa)

inputs

outputs

x n PLA
present state next state

z k

State register

p y Y

PSA clk
Figure 12.1: PROGRAMMABLE SEQUENTIAL ARRAY (psa).

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12 Programmable Modules

Example 12.1: IMPLEMENTATION OF SEQUENTIAL SYSTEMS USING psas SEQUENCE GENERATOR INPUTS: x {0, 1} OUTPUTS: z {0, 1, 3, 6, 7, 10, 14} FUNCTION: The transition and output functions x = 0 : z = 0 10 14 7 0 x = 1 : z = 1 10 3 6 1 x = 0 : z = 0000 1010 1110 0111 0000 x = 1 : z = 0001 1010 0011 0110 0001

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CLK

z3 z2 z1 z0
State

0 1 0 0 0 1 0 0

1 1 1 0

0 1 1 1

0 10 14 7 0 10 14 7 (a) Case x = 0

CLK

z3 z2 z1 z0
State

0 1 0 0 0 1 1 0

0 0 1 1

0 1 1 0

1 10 3

6 1 10 3

(b) Case x = 1
Figure 12.2: TIMING SEQUENCES IN Example 12.1.

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Example 12.1 (cont.)

y k=0 k=1 0 10 k 10 k 1 3 6 x 6 0 1 k 0 1 k 7 10 14 3 k x 14 7 Y K y {2, 4, 5, 8, 9, 11, 12, 13, 15} dont care states K Y3 Y2 Y1 Y0
Introduction to Digital Systems

= = = = =

xy3y2 xy3y2y1 ky1 ky3y2 ky3y2 y 1 y2 k y 3 y2 y1 y3 k y 2 y3 y 3 k y 2 k y 3 y2

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(from state register)

6
y
0 -- programmable connection -- connection made

1 2 3 4 y 5 6 y 7 8 y y 9 10 11 12 13 14 15 16 17 18
3 2 2 1 0 1 2

y k 2

y y y y k 2 y k 3 y k 3

x y3 y2

x y3y2y1 k y1 k y3 y2 k y3 y2
9 next state K
CLK

STATE REGISTER

k y
3

y2

y1

y0

present state

1 2 output

z0

Introduction to Digital Systems

Figure 12.3: psa IMPLEMENTATION IN Example 12.1.

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READ-ONLY MEMORIES (rom)

E En

x0 Address Inputs x1 x n-1

2n X k

ROM

z k-1

z0

Outputs
Figure 12.4: READ-ONLY MEMORY (rom)

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EXAMPLE 12.2

Address Contents x z 000 1011 001 1101 0111 010 011 1000 100 0000 1111 101 110 1111 1011 111

Introduction to Digital Systems

12 Programmable Modules

9
E x1 x0
1 1 1 1 0 0 0 1 1 0 1 0 1

z3 z2 z1 z0
0 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0

NOR Array
Vdd pull-up devices Gnd

Z (a)

Z Z Z

word 0 Gnd

x0 x1

Binary decoder

word 1

word 2 1 0 1 1 Gnd word 3 1 0

enable three-state buffers z3 (b) z2 z1 z0

Figure 12.5: mos IMPLEMENTATION OF A 4 4 READ-ONLY MEMORY: a) THE FUNCTION; b) THE CIRCUIT.

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IMPLEMENTATION OF SWITCHING FUNCTIONS USING roms

10

ROM (512x5) 0 1 00000 00001

+

1 0 1 1 1 0 1 0 1

cin x0 x1 x2 x3 y0 y1 y2 y3

BINARY DECODER

0 1

1 1110 1010 11001 Input/output mapping:

349

11001

356

01101 cin x3 x2 x1 x0 + y3 y2 y1 y0 cout z 3 z 2 z 1 z 0

7 8 511 11111

cout

z3 z2 z1 z0

1 1001
Figure 12.6: rom-BASED IMPLEMENTATION OF A 4-BIT ADDER.

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IMPLEMENTATION OF SEQUENTIAL SYSTEMS USING roms

11

INPUTS: x = (x1, x0), xi {0, 1} OUTPUTS: z {0, 1, } STATE: y = (y1, y0), yi {0, 1, } FUNCTION: The transition and output function PS y1 y0 00 01 10 11 x 1 x0 01 10 11 01,0 10,1 10,0 00,0 11,1 11,0 11,0 10,0 00,1 10,0 00,0 11,1 Y1 Y0 , z N S , Output

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12

ROM address ROM contents y y x x YY z 1 0 1 0

1 0

x x

0 1

0 1 2 3

ROM 16 X 3

next state present state CLK

S y

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
next state

-01 10 10 -00 11 11 -11 10 00 -10 00 11

0 1 0 0 1 0 0 0 1 0 0 1
output

(a)

(b)

Figure 12.7: rom-based implementation of a sequential system: a) network; b) rom contents.

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TYPES OF rom MODULES

13

MASK-PROGRAMMED rom FIELD-PROGRAMMABLE rom (proms) ERASABLE rom (eprom) ELECTRICALLY ERASABLE rom(ash-memory) or eeprom

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NETWORKS OF PROGRAMMABLE MODULES

14

f1(x4, x3, x2, x1, x0) = one-set(0,3,11,12,16,23,27) f0(x4, x3, x2, x1, x0) = one-set(5,7,19,21,31) rom MODULE: 8 2

x = (x(0), x(1)) x(0) = (x4, x3) x(1) = (x2, x1, x0)

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15

x4 x3
0 1 E= 1 En 3 0 0 1 0

x2 x1 x0
011

DECODER 2 1 1 0 0

Row 0 1 2 3 4 5 6 7

3 E 0 0 0 1 ROM 0 3 0 0 0 Z 0 0 0 0 0 0 0 1 Z

3 E 1 0 0 0 ROM 0 2 0 0 1 Z 0 0 0 1 0 1 0 0 Z

3 E 0 0 0 1 ROM 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0

3 E 1 0 0 1 ROM 0 0 0 0 0 Z 0 0 0 0 0 1 0 1 Z 0 1

f0 f1

Figure 12.8: rom-BASED NETWORK FOR THE IMPLEMENTATION OF TWO FUNCTIONS.

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16
x n-1 , . . . , x k n-k
N = 2 n-k

x k-1 , . . . ,x 0

En
N-1

DECODER
N-2 0

k
En

k
En

k
En

ROM N-1

ROM N-2

ROM 0

* three-state outputs f (a)

N=2

n-k

k x k-1 , . . . ,x 0 k

En

En

En

ROM N-1

ROM N-2

ROM 0

x n-1 , . . . , x k

n-k
E

N-1

N-2

MULTIPLEXER En

f (b)

Figure 12.9: IMPLEMENTATIONS OF FUNCTIONS WITH n VARIABLES: a) roms AND DECODER; b) roms AND MULTIPLEXER
Introduction to Digital Systems 12 Programmable Modules

LARGE NUMBER OF SFs

17

E
n En n En n En

x n-1 , . . . ,x 0
n

ROM 3

ROM 2

ROM 1

11

Figure 12.10: rom-BASED IMPLEMENTATION OF LARGE NUMBER OF SWITCHING FUNCTIONS.

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FIELD PROGRAMMABLE GATE ARRAYS (FPGA)

18

Switch matrix Input/Output Blocks

Programmable Logic Block

Switches

Input/Output Blocks Input/Output Blocks

Introduction to Digital Systems

Wiring channel

Figure 12.11: ORGANIZATION OF AN fpga chip.

Input/Output Blocks
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BASIC APPROACHES IN PROGRAMMING OF FPGAs

19

- ON-CHIP STATIC RAM LOADED WITH CONFIGURATION BIT PATTERNS (sram-fpgas). (volatile) - ANTIFUSE-PROGRAMMED DEVICES PROGRAMMED ELECTRICALLY TO PROVIDE CONNECTIONS THAT DEFINE CHIP CONFIGURATION - ARRAY-STYLE eprom and eeprom PROGRAMMED DEVICES USING SEVERAL plas AND A SHARED INTERCONNECT MECHANISM

Introduction to Digital Systems

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20

SRAM cell 1

Transistor 0

Closed switch (a)

Open switch
LUT (Look-Up Table)

MUX 1 0 1 1

y=d

a b c

Decoder

a b c d

0 1 2 3

0 1 1 0 1 0 0 1

y=f(a,b,c)

SRAM cells
(b) (c)

SRAM cells

Figure 12.12: sram fpgaPROGRAMMABLE COMPONENTS: (a) Switch. (b) 4-input multiplexer. (c) Look-up table (LUT).

Introduction to Digital Systems

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Example: XILINX XC2000

21

X Outputs A B C D G Look -Up Table (LUT) F CLK Y

Set
S D Q

K R

Reset

K SRAM-controlled multiplexer
B C K

A CLB D X Y

CLB symbol

Figure 12.13: A CONFIGURABLE LOGIC BLOCK (CLB) (Courtesy of Xilinx, Inc.)

Introduction to Digital Systems

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22

A G B C D Q (a) A A 3-variable function M U X A 3-variable function F A 4-variable function F B

A B C D Q A B C D Q (b) A 3-variable function

C D Q F A

C D Q A 3-variable function G

(c)

Figure 12.14: sram-fpga options in generating functions: (a) One 4-variable function. (b) Two 3-variable functions. (c) Selection between two functions of 3 variables. (Courtesy of Xilinx, Inc.)

Introduction to Digital Systems

12 Programmable Modules

PROGRAMMABLE INTERCONNECT

23

1. DIRECT INTERCONNECTIONS BETWEEN HORIZONTALLY AND VERTICALLY ADJACENT clbs PROVIDE FAST SIGNAL PATHS BETWEEN ADJACENT MODULES 2. GENERAL-PURPOSE INTERCONNECT CONSISTS OF VERTICAL AND HORIZONTAL WIRING SEGMENTS BETWEEN SWITCH MATRICES 3. LONG VERTICAL AND HORIZONTAL LINES SPAN THE WHOLE clbARRAY

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24

Two vertical long lines

Global long line

A B C K CLB D X Y CLB Direct connection Horizontal long line CLB

Switch Matrices

CLB General-purpose interconnect

CLB

CLB

General-purpose interconnect
Figure 12.15: PROGRAMMABLE INTERCONNECT. (Courtesy of Xilinx, Inc.)
Introduction to Digital Systems 12 Programmable Modules

Example 12.5: BCD ADDER MODULE

25

IMPLEMENT A ONE-DIGIT BCD ADDER USING A sram-fpgaMODULE OF XC2000 TYPE x = (x3, x2, x1, x0), xj {0, 1}, x {0, . . . , 9} y = (y3, y2, y1, y0), yj {0, 1}, y {0, . . . , 9} cin {0, 1} OUTPUTS: s = (s3, s2, s1, s0), sj {0, 1}, s {0, . . . , 9} cout {0, 1} INPUTS: FUNCTION: x + y + cin = 10cout + s COMPUTE 16u + v = x + y + cin {0, . . . , 19} using a 4-bit binary adder

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Example 12.5 (cont.)

26

THREE CASES: u=0 v9 s=v cout = 0 u = 0 v > 9 s = v 10 = (v + 6) mod 16 cout = 1 u=1 s = v + 16 10 = v + 6 cout = 1 BCD OUTPUT s=

(v + 6)mod16 if u = 1 or v 10 v otherwise

cout =

1 if u = 1 or v 10 0 otherwise

THE CONDITION u = 1 or v 10 CORRESPONDS TO SWITCHING EXPRESSION t = u v 3 v2 v3 v1

Introduction to Digital Systems 12 Programmable Modules

Example 12.5 (cont.)

27

t u x 3 y3 x 2 y2 x y1 1 x y0
0

out

3-bit Adder

v3

4-bit Adder

s3 s s s
2 1 0

v2 v1 v0

in
Figure 12.16: IMPLEMENTATION OF BCD ADDER MODULE

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Example 12.5 (cont.) SIMPLIFICATION OF THE 3-BIT ADDER s3 = v3 t(v2 v1) s2 = v2 tv1 s1 = v 1 t

28

MOREOVER, s0 = v 0 cout = t

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29

x3 y3 v3 u

CLB

u v3

B A v2 C X D Y K

t cout

x2 y2 v3 CLB v2 x1 y1 v2 CLB v1 x0 y0 v1 CLB c in

Introduction to Digital Systems

v1

t s3

v 2 CLB v1

t s2

v 1 CLB

t CLB s1

v0 s0
12 Programmable Modules

DESIGN WITH FPGAs INVOLVES INTENSIVE USE OF CAD TOOLS AND MODULE LIBRARIES

30

Design entry : A SCHEMATIC ENTRY OR A BEHAVIORAL DESCRIPTION Implementation : PARTITION OF DESIGN INTO SUBMODULES THAT CAN BE MAPPED ONTO clbs, PLACEMENT OF SUBMODULES ONTO CHIP, AND ROUTING OF SIGNALS TO CONNECT THE SUBMODULES

Design verication : IN-CIRCUIT TESTING SIMULATION, AND TIMING ANALYSIS

Introduction to Digital Systems 12 Programmable Modules