Vending Machine (Verilog)

Submitted By:
Wajahat Ali Butt 107

Hashir Badar 113
Muhammad Fahad Shabbir 127
Muhammad Safeer 134
DESIGN SPECIFICATIONS
We have designed this machine for three products. The user will first select
one of the three products. The machine will tell him the price of the product.
Then he will enter money. If the amount of money entered is equal to the
price of the product then product will be issued. But if the amount of money
entered is greater than the price then product will be issued as well as
change will be returned. The return of change as well as the issue of product
is indicated by LED. The product selected as well as its price is displayed on
7 segment LED display. The product is selected as well as money is entered
through switches. There is a reset button to reset the machine to idle state.
The 1st product has Rs.1 , 2nd product has Rs.2 fare and 3rd product has Rs.3.
The three products are represented in binary no. as 001,010,100 respectively.
The user is allowed to enter Rs. 1, Rs.2, or Rs.3 coin which are represented
in binary as 0 or 1.
STATE DIAGRAM
Free
state
Produc Produc Produc

t_A_St t_B_St t_C_St
ate ate ate
Chang
e
State
VERILOG CODING
`timescale 1ns / 1ps

///////////////////////////////////////////////////////////
///////////////////////
// Company:
// Engineer:
//
// Create Date: 00:10:36 07/11/2008
// Design Name:
// Module Name: vend
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///////////////////////////////////////////////////////////
///////////////////////
module vend(
//Inputs
clk, // internal clock (50 MHz)

reset, // reset variable
RS1, // Rupees 1 coin (dip switch)
product,
//Outputs
// 2nd SEVEN Segment
LED_a2,
LED_b2,
LED_c2,
LED_d2,
LED_e2,
LED_f2,
LED_g2,
// 1 st SEVEN Segment
LED_a1,
LED_b1,
LED_c1,
LED_d1,
LED_e1,
LED_f1,
LED_g1,
);
//*********************************************************
*******************
// ASSIGNING each variable as input or output.
input clk;
input reset;
input RS1;
input RS2;
input RS3;
input[2:0] product;
output LED_a2;
output LED_b2;
output LED_c2;
output LED_d2;
output LED_e2;
output LED_f2;
output LED_g2;
output LED_a1;
output LED_b1;
output LED_c1;
output LED_d1;
output LED_e1;
output LED_f1;
output LED_g1;
// output LED_timer;
// declaring output as reg
reg LED_a2;
reg LED_b2;
reg LED_c2;
reg LED_d2;
reg LED_e2;
reg LED_f2;
reg LED_g2;
reg LED_a1;
reg LED_b1;
reg LED_c1;
reg LED_d1;
reg LED_e1;
reg LED_f1;
reg LED_g1;
reg [3:0]t_money;
reg [3:0]r_money;
reg [3:0]first_digit;
reg [3:0]second_digit;
reg temp1; // temporary reg variables

for toggling
reg temp2;
reg temp3;
reg [1:0]pres_state, next_state;
parameter
FREE_STATE= 3'd0,
PRODUCT_A_STATE=3'd1,
PRODUCT_B_STATE = 3'd2,
PRODUCT_C_STATE= 3'd3,
CHANGE_STATE = 3'd4;
//*********************************************************
*******************
always@(posedge clk or negedge reset)

begin
if (reset == 0)
pres_state <= FREE_STATE;
else
pres_state <= next_state;
end
//*********************************************************
*******************
always@ (posedge clk)

begin
case(pres_state)
FREE_STATE:
begin
case(product)
3'b001:
next_state<=PRODUCT_A_STATE;
3'b010:
next_state<=PRODUCT_B_STATE;
3'b100:
next_state<=PRODUCT_C_STATE;
default:
next_state <= FREE_STATE;

endcase
end
next_state<=PRODUCT_A_STATE:
begin
if(t_money<3)
next_state <=PRODUCT_A_STATE;
else if(t_money >=3 )
next_state <= CHANGE_STATE;

end
next_state<=PRODUCT_B_STATE:
begin
if(t_money<4)
next_state <=PRODUCT_B_STATE;
else if(t_money >=4)

end
next_state<=PRODUCT_C_STATE:
begin
if(t_money<5)
next_state <=PRODUCT_C_STATE;
else if(t_money >=5)

end
CHANGE_STATE:
begin

end
endcase
end
//*********************************************************
*******************
always@ (posedge clk)

begin
case(pres_state)
FREE_STATE:
begin
if (reset == 0)
begin
temp3 <= 0;
temp2 <= 0;
temp1 <= 0;
if(product==3'b000)
r_money <= 0;
else if(product==3'b001)
r_money <= 3;
r_money <= 4;
r_money <= 5;
first_digit <= 4'd0;

second_digit <= 4'd0;
end
end
PRODUCT_A_STATE:
begin
if(RS1 == !temp1)
begin
temp1 <= !temp1;
t_money <= t_money + 1;
r_money <= r_money - 1;
end
else if(RS2 == !temp2)
begin
temp2 <= !temp2;
end

begin
temp3 <= !temp3;
end
second_digit <=r_money;
end
PRODUCT_B_STATE:
begin
if(RS1 == !temp1)
begin
temp1 <= !temp1;
end
begin
temp2 <= !temp2;
end

begin
temp3 <= !temp3;
end
end
PRODUCT_C_STATE:
begin
if(RS1 == !temp1)
begin
temp1 <= !temp1;
end
begin
temp2 <= !temp2;
end

begin
temp3 <= !temp3;
end
end
CHANGE_STATE:
begin
first_digit<=12;
second_digit<=0 ;
end
endcase
end
//*********************************************************
*******************
//display on 7segments
always @(first_digit)
begin
case(first_digit)
4'b0000 :
begin
LED_a1 <= 1'b0; // for displaying
nothing at seven - segment
LED_b1 <= 1'b0;
LED_c1 <= 1'b0;
LED_d1 <= 1'b0;
LED_e1 <= 1'b0;
LED_f1 <= 1'b0;
LED_g1 <= 1'b0;
end
4'b1100 :
begin
LED_a1 <= 1'b1; // display C at
seven - segment
LED_b1 <= 1'b0;
LED_c1 <= 1'b0;
LED_d1 <= 1'b1;
LED_e1 <= 1'b1;
LED_f1 <= 1'b1;
LED_g1 <= 1'b0;
end
default :
begin
LED_a1 <= LED_a1; // maintain
output LEDs
LED_b1 <= LED_b1;
LED_c1 <= LED_c1;
LED_d1 <= LED_d1;
LED_e1 <= LED_e1;
LED_f1 <= LED_f1;
LED_g1 <= LED_g1;
end
endcase
end
//*********************************************************
*******************
always @(second_digit)
begin
case(second_digit)
4'b0000 :
begin
LED_a2 <= 1'b1; // 0 display at seven -
segment
LED_b2 <= 1'b1;
LED_c2 <= 1'b1;
LED_d2 <= 1'b1;
LED_e2 <= 1'b1;
LED_f2 <= 1'b1;
LED_g2 <= 1'b0;
end
4'b0001 :
begin
segment
LED_b2 <= 1'b1;
LED_c2 <= 1'b1;
LED_d2 <= 1'b0;
LED_e2 <= 1'b0;
LED_f2 <= 1'b0;
LED_g2 <= 1'b0;
end
4'b0010 :
begin
segment
LED_b2 <= 1'b1;
LED_c2 <= 1'b0;
LED_d2 <= 1'b1;
LED_e2 <= 1'b1;
LED_f2 <= 1'b0;
LED_g2 <= 1'b1;
end
4'b0011 :
begin
segment
LED_b2 <= 1'b1;
LED_c2 <= 1'b1;
LED_d2 <= 1'b1;
LED_e2 <= 1'b0;
LED_f2 <= 1'b0;
LED_g2 <= 1'b1;
end
4'b0100 :
begin
segment
LED_b2 <= 1'b1;
LED_c2 <= 1'b1;
LED_d2 <= 1'b0;
LED_e2 <= 1'b0;
LED_f2 <= 1'b1;
LED_g2 <= 1'b1;
end
4'b0101 :
begin
segment
LED_b2 <= 1'b0;
LED_c2 <= 1'b1;
LED_d2 <= 1'b1;
LED_e2 <= 1'b0;
LED_f2 <= 1'b1;
LED_g2 <= 1'b1;
end
default :
begin
LED_a2 <= LED_a2; // maintain
output LEDs
LED_b2 <= LED_b2;
LED_c2 <= LED_c2;
LED_d2 <= LED_d2;
LED_e2 <= LED_e2;
LED_f2 <= LED_f2;
LED_g2 <= LED_g2;
end
endcase
end
endmodule

Vending Machine (Verilog)

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Vending Machine (Verilog)

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Drepturi de autor:

Formate disponibile

Submitted By:

Wajahat Ali Butt 107

Produc Produc Produc

`timescale 1ns / 1ps

clk, // internal clock (50 MHz)

// ASSIGNING each variable as input or output.

reg temp1; // temporary reg variables

reg [1:0]pres_state, next_state;

always@(posedge clk or negedge reset)

always@ (posedge clk)

next_state <= FREE_STATE;

else if(t_money >=3 )

next_state <= CHANGE_STATE;

else if(t_money >=4)

next_state <= CHANGE_STATE;

else if(t_money >=5)

next_state <= CHANGE_STATE;

next_state <= CHANGE_STATE;

always@ (posedge clk)

first_digit <= 4'd0;

else if(RS3 == !temp3)

else if(RS3 == !temp3)

else if(RS3 == !temp3)

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