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TV

PARTS LIST LISTE PIECES DETACHEES ERSATZTEILLISTE LISTA PARTI DI RICAMBIO LISTA DE PIEZAS DE REPUESTO

THOMSON 27LB120S4/U Chassis LCD12B


SPEAKER KIT ENS. HAUT PARLEUR ZUSAMMEN LAUTSPRECHER INSIEME ALTOPARLANTE CONJUNTO ALTAVOZ FOLDING BOX ACCESSORIES EMBALLAGE CARTON ACCESSOIRES KARTON ZUBEHOER IMBALLAGGIO CARTONE ACCESSORI EMBALAJE CARTON ACCESORIOS POWER SUPPLY LEAD CORDON DALIMENTATION NETZKABEL CAVO DI ALIMENTAZIONE CABLE DE ALIMENTACION POWER SUPPLY LEAD UK CORDON DALIMENTATION UK NETZKABEL UK CAVO DI ALIMENTAZIONE UK CABLE DE ALIMENTACION UK RF CABLE CABLE RF RF KABEL CAVO RF CABLE RF CARTON BOX TOP EMBALLAGE CARTON SUPERIRUR VERPACKUNG VON OBEN IMBALLAGGIO DI SOPRA EMBALAJE DE ARRIBA FOLDING BOX BOTTOM EMBALLAGE CARTON INFERIEUR VERPACKUNG VON UNTEN IMBALLAGGIO DI SOTTO EMBALAJE DE ABAJO FITTING LEFT CALE GAUCHE POLSTER LINKS DISTANZIATORE SINISTRA CALZO IZQUIERDA FITTING RIGHT CALE DROITE POLSTER RECHTS DISTANZIATORE DESTRA CALZO DERECHA FITTING BOTTOM CALE INFERIEUR POLSTER UNTERST DISTANZIATORE INFERIORE CALZO INFERIOR 25731340

MODULES
MAIN POWE AUDI IF IR KB VIDE MAIN SMPS AUDIO TMM FE6234 TUNER IR CONTROL VIDEO/CONNECTOR 35884510 35884740 35884490 35885050 35770430 35765250 35884530

M
27LB120S4 PARTS LIST 35885070 27LB120S4 LISTE DE PIECES DETACHEES 27LB120S4 ERSATZTEILLISTE 27LB120S4 LISTA PARTI DI RICAMBIO 27LB120S4 LISTA DE PIEZAS DE REPUESTO 27LB120S4/U-27LCDB03B UM GB,F,D,I,E 35834310 27LB120S4/U-27LCDB03B NU GB,F,D,I,E 27LB120S4/U-27LCDB03B BA GB,F,D,I,E 27LB120S4/U-27LCDB03B IU GB,F,D,I,E 27LB120S4/U-27LCDB03B IU GB,F,D,I,E 27/30LCDB INSTAL GUIDE WALL MOUNT 35785470 27/30LCDB NOTICE INSTAL ACCROCHE MURAL 27/30LCDB INST. SANLEITUNG WANDHALTERUNG 27/30LCDB ISTRUZ INSTAL SUPPORTO MURALE 27/30LCDB INSTRUC INSTAL SOPORTE MURAL

35741730

W 35068730

EQUIPMENT/PRESENTATION EQUIPEMENT/PRESENTATION AUSSTATTUNG/GEHAEUSE PARTI VARIE EQUIPO/PRESENTACION


DISPLAY LCD 27 V270W1/L04 CMO ECRAN LCD 27 V270W1/L04 CMO LCD-ANZEIGE 27 V270W1/L04 CMO VISUALIZZATORE LCD 27 V270W1/L04 CMO VISUALIZADOR LCD 27 V270W1/L04 CMO RCT311TAM1 REMOTE CONTROL RCT311TAM1 TELECOMMANDE RCT311TAM1 FERNBEDIENUNG RCT311TAM1 TELECOMANDO RCT311TAM1 TELEMANDO FRONT CABINET ASSY FACADE EQUIPEE FRONTPLATTE KPL MOBILE FRONTALE CPL MUEBLE FRONTAL CPL REAR PANEL DOS RUECKWAND PANNELLO POSTERIORE TAPA POSTERIOR BASE PLATE OF THE FOOT EMBASE DU PIED FUSS-BASISPLATTE BASE DI APPOGGIO DEL PIEDE EMBASE DEL PIE STAND FOOT MONTANT DU PIED STANDFUSS PIEDE VERTICALE PIE VERTICAL LID OF FOOT COUVERCLE DU PIED KAPPE DES FUSSES COPERCHIO DEL PIEDE TAPA DEL PIE 35770380

W 10722790

35750400

35770750

21282900

35770760

50088690

35770780

25811560

35770790

25739220

35770800

25739230

25739240

For any requests, please contact THOMSON multimedia after sales service area Pour toutes prcisions, contactez votre service apres vente local THOMSON multimedia Fr weitere Ausknfte, wenden Sie sich bitte an die THOMSON multimedia Kundendienste Per precisazioni, contattare lassistenza tecnica THOMSON multimedia Para cualquier pregunta, por favor contactar con el responsable de zona del servicio postventa de THOMSON multimedia

VERSION 1 VERSION 2

10 / 2004 00 / 0000

35885070 1/1

No copying, translation, modification on other use authorized. All rights reserved worldwide. Tous droits de reproduction, de traduction, d'adaptation et d'excution rservs pour tous les pays. Smtliche Urheberrechte an diesen Texten und Zeichnungen stehen uns zu. Nachdrucke, Vervielfltigungen - auch auszugsweise - nur mit unserer vorherigen Zustimmung zulssig. Alle Rechte vorbehalten. I diritti di riproduzione, di traduzione, e esecuzione sono riservati per tutti i paesi. Derechos de reproduccion, de traduccion, de adaptacion y de ejecucion reservados para todos los paises.

SERVICE MODE - MODE SERVICE - SERVICE-MODE - MODO SERVICIO


Overview
EN

Service Mode Operation Manual


Sound Picture Preferences Installation
Figure Overview OSD Model support: 15 20 and 20 bi-sonic Service Mode 1. Press the menu button, and then the screen display will appear Overview OSD, below as Figure Overview OSD. Then press the info button and 1, 0and 3 buttons step by step to enter Service Mode. And Figure Service mode will appear on the screen display.

FR
Mode Service 1.Presser la touche Menu lecran de selection ci-dessus apparait Presser la touche Info, la touche 1 puis les touches 0 et 3 pour acceder au Mode Service

IT

Manuale Procedura Service Mode


Modelli: 15 20 e 20 bi-colonna Service Mode 1. Premere il tasto menu per far visualizzare il menu Sommario, vedi pagina OSD. Poi premere sequenzialmente i tasti info , 1, 0 e 3 per entrare in Service mode. Il menu di Service mode verr visualizzata sullo schermo. Per cambiare pagina premere il tasto Menu. Menu Sommario

DE

ES

Anleitung Service Mode


Fr Modelle: 15, 20 und 20 bi-sonic Service Mode 1. Drcken sie die MENU Taste. Es erscheint das bersicht Men (siehe Abbildung 1). Drcken sie dann nacheinander die Tasten INFO, 1, 0, und 3. Die erste Seite des Service-Modes wird angezeigt (siehe Abbildung 2).

Manual de operacin del Modo Servicio


Para modelos de : 15, 20 y 20 bi-columna Modo Servicio 1. Pulsar la tecla men, en la pantalla se mostrar el men OVERVIEW (NDICE), como se muestra en la figura MENU OVERVIEW (NDICE). A continuacin, pulsar las teclas info, 1, 0 y 3 una tras otra para entrar en Modo Servicio y se mostrar la primera pgina del Modo Servicio en la pantalla.

NAVIGATION INSIDE THE SERVICE MODE - DEPLACEMENT DANS LE MODE SERVICE SUCHE IN SERVICE MODE - OPZIONI NEL SERVICE MODE - BUSQUEDA EN MODO SERVICIO
REMOTE CONTROL - TELECOMMANDE - FERNBEDIENUNG TELECOMANDO - MANDO A DISTANCIA
Changing page - Changement de page Seitenwechsel - Cambiare Pagina - Cambio de pgina

- Press "Menu" button - Appuyer sur la touche "Menu" - Taste "Menu" - Premere " Menu" - Pulse "Menu" Choosing a setting from the menu / setting e value Choix d'un rglage dans un menu / Rglage d'une valeur Wahl einer einstellung in einem men / Einstellung eines wertes Scegliere una Regolazione dal Menu / Selezione di un valore Eleccion de un Ajuste en un menu / Ajuste de un valor

Color temp Red Drive Green Drive Blue Drive Red Offset Green Offset Blue Offset Reset To Default Calibration... Auto Turn on

P-W -

P-N

P-C

V-N

V-C

Color temp Red Drive Green Drive Blue Drive Red Offset Green Offset Blue Offset Reset To Default Calibration... Auto Turn on

P-W -

P-N

P-C

V-N

V-C

+ - 123 + - 123 + - 123 + - 123 + - 123 + - 123 190247 Eu 20L0BI Ver 09171I

+ - 123 + - 123 + - 123 + - 123 + - 123 + - 123 190247 Eu 20L0BI Ver 09171I

Tuner 1D on off

Tuner 1D on off

Naviagation up - Change value - Rglage de la valeur - Wert nden - Cambiare valore - Cambiar valor

Naviagation down

> <

VALUE VALUE

LCD12B
First issue 01 / 05

Color temp Red Drive Green Drive Blue Drive Red Offset Green Offset Blue Offset Reset To Default Calibration...

P-W P-N -

P-C V-W V-N

V-C

+ - 128 + - 128 + - 112 + - 131 + - 129 + - 128 11:45:04 EU 30L04B Ver:30LB07AT

TUNER: 09

EN
1. Color Temp: P-N means Normal on YpbPr, V-N means Normal on Video mode. Each item decide different gamma curve. 2. Red drive, Green drive and blue drive means gamma RGB gain. Control by scaler 3. Red offset, Green offset and blue offset means gamma RGB offset. Control by scaler 4. Reset To Default: press OK will load all default value on User OSD 5. Calibration: press this botton guide to calibrate A/D converter white and black level on PC input. Also guide to calibrate A/D converter PbPr offset on YpbPr input. 6. MV enable: (30") designer debug tool revision ( this is information only )

IT
1. Color Temp: P-N significa Normale in funzione YPbPr, V-N significa Normale in funzione Video. Ogni selezione determina una differente curva di risposta. 2. Red Drive, Green Drive e Blue Drive significa guadagno gamma RGB. Controllato da una scala. 3. Red Offset, Green Offset e Blue Offset significa Offset gamma RGB. Controllato da una scala. 4. Reset To Default: premendo OK verranno caricati tutti i valori di Default nel Menu Utente. 5. Calibration: premere questo tasto guida per calibrare il livello Bianco /Nero del convertitore A/D dellingresso PC. Calibra anche loffset del convertitore A/D PbPr dellingresso YpbPr. 6. MV enable: (30")

FR
1. Color Temp: Temperature des couleurs. P-N correspond un reglage Normal /YpPr V-N correspond un reglage normal / mode vido chaque item permet de rgler la courbe de gamma. 2. Red drive, Green drive and blue drive: green drive et Bleu drive correspond aux reglages de gain du gamma RVB ( control par le scaler). 3. Red offset, green offset et blue offset: correspond aux rglage doffset du gamma RVB ( control par le scaler ). 4. Reset To Default: Appuyer sur OK. Charger les valeurs par defaut sur le menu OSD. 5. Calibration: Appuyer sur OK pour valider. Etalonne les niveaux blanc et noir du convertisseur A/D de l entre PC Etalonne egalement les offset Pb/Pr du convertisseur A/D sur l entre Ypb Pr. 6. MV enable: Port Vido Chip 323 ( Seulement Utilis pour le debuggage en conception ). Si vous quittez le menu usine, la fonction n'existe plus.

ES
1. Color Temp: P-N significa Normal en modo YpbPr, V-N significa Normal en modo Video. Cada elemento tiene una curva de gamma distinta. 2. Red drive, Green drive y Blue drive ajustan la ganancia de la gamma RGB. 3. Red offset, Green offset y Blue offset ajustan el offset de la gamma RGB. 4. Reset To Default: Al pulsar OK se cargarn todos los valores por defecto del men de usuario 5. Calibration: Pulsando este botn ayuda a calibrar el convertidor A/D de nivel de blanco y negro para la entrada de PC. Tambin sirve para calibrar el offset del convertidor A/D PbPr en la entrada YpbPr. 6. MV enable: (30") puerto de vdeo c.i. 323 (uso solamente por el diseador, si se deja el men de fbrica, no funciona mas)

DE
1. Color Temp: P-W steht fr Warm im YPbPr-Mode, P-N steht fr Neutral bei YPbPr-Mode, P-C steht fr Kalt im YPbPr,-Mode, V-W steht fr Warm im Video-Mode, V-N steht fr Neutral im Video-Mode, V-C steht fr Kalt im Video-Mode. Alle Modi haben unterschiedliche Gamma-Kennlinien. 2. Red Drive, Green Drive und Blue Drive: Einstellung der RGBVerstrkung 3. Red Offset, Green Offset und Blue Offset: Einstellung des RGBOffsets 4. Reset to Default: Durch Drcken der OK-Taste werden die Benutzerdaten gelscht und die Defaultwerte geladen. 5. Calibration: Kalibrieren der Schwarz- und Weipegel des ADWandlers des PC-Eingangs. 6. MV enable: (30") Chip 323 Video-Port (Nur fr Entwicklungszwecke, hat keine Funktion sobald der Produktionsmode verlassen wird.)

LCD12B
First issue 01 / 05

OSD Position Burn in mode Burn in time adjust Video Int Gain YPbPr Int Gain Colour PW 1280 Brighness Set First INstallation Fan test
EN
7. OSD position: OSD position selection. 8. Burn in mode: For development only. Value change is not recommended. 9. Burn in time Adjust: For development only. Value change is not recommended. 10. Video int Gain: this slider bar used to align brightness spec of Video mode. Larger value bring to brighter. Control by Video decoder VPC3230 11. YPbPr: For development only. Value change is not recommended. 12. Colour: adjust color saturation. Same funct ion on User OSD. Control by Video decoder VPC3230. 13. Tuner Set V-Level: not used 14. Tuner Get V-Level: not used. 15. Set First Installation: Enable means TV will pop-up installation OSD at next power-on. 16. Tuner Set Factory Programs: not used. 17. Fan test: For development only. Value change is not recommended 17-1. Enter PW1230 Adjustment page: Deinterlacer parameters control. For development only. Value change is not recommended.

On

Off

0:00 0 96 180 53 8

NotEnabled...

Tuner Set Factory Programs

IT
7. OSD position: Selezione posizione OSD. 8. Burn in mode: Utilizzato per la fabbrica. Si consiglia di non cambiare valore. 9. Burn in time Adjust: Utilizzato per la fabbrica. Si consiglia di non cambiare valore. 10. Video int Gain: Regola il livello di luminosit in funzione Video. Pi alto il valore pi limmagine luminosa. Controllo tramite il Decoder Video VPC3230. 11. YPbPr: Utilizzato per la fabbrica. Si consiglia di non cambiare valore. 12. Colour: Regola la saturazione del colore. Stessa funzione del Menu utente. Controllo tramite Video Decoder VPC3230. 13. Tuner Set V-Level: Non utilizzato. 14. Tuner Get V-level: Non utilizzato. 15. Set First Installation: Enable significa abilitazione, allaccensione, del menu di prima installazione. 16. Tuner Set factory Programs: Non utilizzato. 17. Fan test: Utilizzato per la fabbrica. Si consiglia di non cambiare valore. 17-1. Enter PW Adjustment page: Controllo parametric Deinterlacer. Utilizzato in fabbrica. Si consiglia di non cambiare valore.

FR
7. OSD position: Selection de la position OSD. 8. Burn in mode: Rglage usine, ne pas modifier. 9. Burn in time Adjust: Rglage usine, ne pas modifier. 10. Video int Gain: Rglage de la lumire en mode vido. Contrle par le dcodeur vido VPC 3230. La position leve du curseur augmente la lumire. 11. YPbPr: Rglage usine, ne pas modifier. 12. Colour: Rgle la saturation de la couleur. 13. Tuner Set V-Level:Pas utilis. 14. Tuner Get V-Level: Pas utilis. 15. Set First Installation: Signifie que la TV la prochaine mise sous tension affichera le menu d installation. 16. Tuner Set Factory Programs: Pas utilis. 17. Fan test: Rglage usine, ne pas modifier. 17-1. Enter PW1230 Adjustment page: Ne pas modifier. Rglage usine Contrle les parametres Deinterlacer.

ES
a7. OSD position: Selecciona la posicin del OSD. 8. Burn in mode: No se recomienda cambiar este valor 9. Burn in time Adjust: No se recomienda cambiar este valor 10. Video int Gain: Esta barra deslizante se utiliza para ajustar las especificaciones del brillo en el modo Video. Cuanto mayor sea el valor, ms brillante. Control por el descodificador de Video VPC3230 11. YPbPr: No se recomienda cambiar este valor 12. Colour: ajusta la saturacin del color. Es la misma funcin que el men de usuario. Control por el descodificador de Video VPC3230. 13. Tuner Set V-Level: no utilizado. 14. Tuner Get V-Level: no utilizado. 15. Set First Installation: Enable significa que la prxima vez que se conecte el TV aparecer el men de primera instalacin. 16. Tuner Set Factory Programs: no utilizado. 17. Fan test: No se recomienda cambiar este valor 17-1. Enter PW1230 Adjustment page: control de los parmetros de Deinterlacer. No se recomienda cambiar este valor.

DE
8. OSD Position: Wahl der Men-Position auf dem Bildschirm 9. Burn in mode: Eine nderung dieser Grundeinstellung ist nicht empfehlenswert. 10. Burn in time Adjust: Eine nderung dieser Grundeinstellung ist nicht empfehlenswert. 11. Video Int Gain: Helligkeitsvoreinsteller fr den Video-Mode. Steuerung ber den Videodecoder VPC3230. XX. YPbPr: Eine nderung dieser Grundeinstellung ist nicht empfehlenswert. 12. Colour: Einstellung der Farbsttigung; gleiche Funktion wie die Benutzersteuerung. Steuerung ber den Videodecoder VPC3230. 13. Tuner Set V-Level: nicht benutzt 14. Tuner Get V-Level: nicht benutzt 15. Set First Installation: Enable lsst beim nchsten Einschalten des Gertes nach einer Netztrennung das Installationsmen erscheinen. 16. Tuner Set Factory Programs: nicht benutzt. 17. Fan test: Eine nderung dieser Grundeinstellung ist nicht empfehlenswert. 17-1. Enter PW1230 Adjustment Page: Abgleich der Parameter des Deinterlacers. Eine nderung dieser Grundeinstellungen ist nicht empfehlenswert.

LCD12B
First issue 01 / 05

Pw Gamma Scale Mode Color Delay HVLock Sensitivity Audio Gain Audio Delay Pb Offset Pr Offset Nonlinear Scale... -

Automatic Cinerama + 3 + 5 + 25 + 7 + 58 + 60

VClipPct VOffsetPct VStretchPct HClipPct HOffsetPct HStretchPct

+ - 1074 + - 998 + - 1000 + - 1030 + - 1000 + - 1300 -

- NotEnabled...

SW Deinterlace Field Inverse...


EN
18. PW Gamma: gamma curve selection. Automatic means pick-up proper gamma curve automatically when user choose Normal, Warm and Cool. Value change is not recommended. 19. Scale Mode: screen ratio selection. 21. HV Lock Sensitivity: Tuner HV sync sensitivity. Value change is not recommended. Fake programme be detected or Real programme be skipped. 22. Color Delay: Color timing delay which only impact on Video mode. For development only. Value change is not recommended 23. Audio gain: not used. 24. Pb offset: adjust Pb offset on YpbPr input. 25. Pr offset: adjust Pr offset on YpbPr input. These 2(25,26) Functions above could be automatically done by Calibration page1.
GEOMETRY V-Amplitude VClipPct 4/3 16/9 V-Position VOffsetPct 16/9 V-Linearity VStretchPct 4/3 16/9 GEOMETRY H-Amplitude HClipPct 4/3 16/9 H-Position HOffsetPct 16/9 H-Linearity HStretchPct 4/3 16/9

FR
18. PW Gamma: Selection de la courbe de gamma Automatic correspont loptention de la courbe de gamma approprie quand lutilisateur choisit la position froide, neutre, chaude ou le rendu des couleurs est meilleur. il est deconseill de slectionner la position value Change. 19. Scale Mode: Selection format decran. 21. HV Lock Sensitivity: Sensibilit de la Synch. HV tuner. Il est imperatif de ne pas modifier sa valeur. Le tuner dtectera les mauvais progrmmes ou passera les programmes corrctes. 22. Color Delay: Rglage du dlai couleur en mode vido. Rglage usine, ne pas modifier. 23. Audio gain: Non utilis. 24. Pb offset: Rglage de loffset Pb sur l entre Ypb Pr. 25. Pr offset: Rglage de loffset Pr sur lente Ypb Pr. Ces 2 rglages ( 25, 26 ) sont automatiquement effectues par calibration de la page 1 du mode service.

IT
18. PW Gamma: Selezione curva gamma. In Automatic viene selezionata automaticamente la curva gamma ideale, in base alla scelta utente Calda, Fredda o Neutra, nella funzione Tonalit . Si consiglia di non cambiare valore. 19. Scale Mode: Selezione Rapporto schermo. 21. HV Lock Sensitivity: Sensibilit Sync HV Tuner. Si consiglia di non cambiare valore. Livello soglia per saltare eventuali emittenti con segnale debole. 22. Color Delay: Regola il ritardo colore rispetto al segnale video. Utilizzato per la fabbrica. Si consiglia di non cambiare valore. 23. Audio Gain: Non utilizzato. 24. Pb offset: Regola loffset Pb sul segnale YpbPr in ingresso. 25. Pr offset: Regola loffset Pr sul segnale YpbPr in ingresso. Le regolazioni menzionate nei punti 25 e 26 possono essere eseguite automaticamente come indicato nella riga Calibration di pagina 1.

DE
18. PW Gamma: Auswahl der Gamma-Kennlinie: Bei Einstellung Automatic wird automatisch die jeweilige Kennlinie gewhlt, wenn der Benutzer zwischen Warm, Neutral oder Kalt umschaltet. Eine nderung dieser Grundeinstellung ist nicht empfehlenswert. 19. Scale Mode: Wahl des Bildformates 21. HV Lock Sensitivity: Empfindlichkeit des Synchrondetektors im Tuner. Eine nderung dieser Grundeinstellung ist nicht empfehlenswert, da sonst der Sendersuchlauf falsche Ergebnisse liefern knnte. 22. Color Delay: Einstellung Farbversatz. Eine nderung dieser Grundeinstellung ist nicht empfehlenswert. 23 Audio Gain: nicht benutzt 24. Pb Offset: Einstellung des Pb Offsets bei YPbPr. 25. Pr Offset: Einstellung des Pr Offsets bei YPbPr. Zu 26 und26: Der Abgleich dieser Funktionen kann automatisch mit der Funktion Calibration auf der Service-Mode Seite 1 durchgefhrt werden.

ES
18. PW Gamma: Seleccin de la curva de gamma. Automatic quiere decir que recuperar automticamente la curva ideal de gamma cuando el usuario seleccione Normal, Clido o Fro. No se recomienda cambiar este valor. 19. Scale Mode: selecciona la relacin de pantalla. 21. HV Lock Sensitivity: Sensibilidad de los sincronismos HV del sintonizador para la bsqueda de emisoras. No se aconseja cambiar este valor. Los canales reales pueden ser ignorados o los falsos memorizados. 22. Color Delay: Retardo del color en modo Video. No se recomienda cambiar este valor 23. Audio gain: no utilizado. 24. Pb offset: ajuste del offset de Pb en la entrada YpbPr. 25. Pr offset: ajuste del offset de Pr en la entrada YpbPr. Estas 2 funciones anteriores (25,26) sern hechas automticamente en Calibration de la pgina 1.

LCD12B
First issue 01 / 05

Auto Adjustment Default Langage RGB Filter Video Filter Monitor Sync VPC Brightness Reset Reset All Nvram... Test Pattern... H.position V.position VID_320T_5.PWF On Off Temp: 51.0 C Fan1: ORPM Fan2: ORPM + + 100 25 English

EN
26. Auto Adjustment: auto adjustment new timing(position ,phaseetc). Only active on PC mode. 27. Default Language: set default language. Same function on User OSD. 28. RGB filter: sharpness filter of PC port of scaler. Impact on PC and YpbPr input 29. Video filter: sharpness filter of Video of scaler. Impact on TV Video and YcbCr. 30. Monitor Sync: force to On. So that Video format can auto detection. 31.VPC Brightness Reset: For development only. Value change is not recommended. 32. Reset All Nvram: press OK will reset all parameters on service mode, including color temp settings, brightness setting.etc. 33. Test Pattern: display test-pattern which generate by scaler. Only active on PC source. 34. H.Position: adjust horizontal position while PC source in 35. V.Position: adjust Vertical position while PC source in

IT
26. Auto Adjustment: Auto regolazione nuove temporizzazioni ( posizione, fase ... etc). Attivo solo in funzione PC. 27. Default language: Seleziona la lingua. Stessa funzione del Menu Utente. 28. RGB Filter: Definizione filtro del demoltiplicatore (scaler) della porta PC. Influisce sugli ingressi PC e YpbPr. 29. Video Filter: Definizione filtro del demoltiplicatore del segnale Video. Influisce sui segnali TV Video e YcbCr. 30. Monitor Sync: Forzato su On. In questo modo pu essere rilevato automaticamente il Formato Video. 31.VPC Brightness Reset: Utilizzato per la fabbrica. Si consiglia di non cambiare valore. 32. Reset All Nvram: Premendo OK verranno resettati tutti I parametri del Service Mode, inclusi regolazione Temp. Colore, Regolazione Luminosit, ... ecc.). 33. Test Pattern: Attivazione serie di segnali test. Attivo solo con ingresso PC. 34. H. Position: Regola la posizione Orizzontale in ingresso PC. 35. V. Position: Regola la posizione Verticale in ingresso PC.

FR
26.Auto Adjustment: Actif seulement en mode PC. Auto rglage des nouveaux parametres de temps ( Position, phase..). 27. Default Language: Selectionne la langue par dfaut. Mme fonction que le rglage utilisateur. 28. RGB filter: Filtre Contour RGB du Port PC. 29. Video filter: filtre contour Vido. Agit sur les entres TV Vido et Ye bCr. 30. Monitor Sync: Forc ON Auto dtection du format Vido. 31.VPC Brightness Reset: Rglage usine, ne pas modifier. 32. Reset All Nvram: Appui sur OK. Reset De tous les parametres du MODE SERVICE incluant la temprature de couleur, Contour... etc. 33. Test Pattern: Affichage de la mire interne. Actif seulement en mode PC 34. H.Position: Rglage Horizontal en mode PC. 35. V.Position: Rglage Vertical en mode PC.

ES
26. Auto Adjustment: Autoajuste de nuevo timing (posicin, faseetc). Slo activo en modo PC. 27. Default Language: selecciona el idioma por defecto. Hace la misma funcin que el men "Usuario". 28. RGB filter: filtro de nitidez. Vlido para las entradas de PC e YpbPr. 29. Video filter: filtro de nitidez. Vlido para las entradas de TV, Video e YcbCr. 30. Monitor Sync: forzado a On. El formato de video puede ser autodetectado. 31.VPC Brightness Reset: No se recomienda cambiar este valor 32. Reset All Nvram: pulsando OK se borrarn todos los parmetros del Modo Servicio, incluyendo los ajustes de temperatura de color, ajustes de brillo y contraste....., etc. 33. Test Pattern: muestra unas cartas de ajuste generadas internamente. Activo solamente en modo PC. 34. H. Position: ajusta la posicin horizontal sobre la entrada PC. 35. V. Position: ajusta la posicin Vertical sobre la entrada PC.

DE
26. Auto Adjustment: Automatischer Abgleich von Timing, Lage, Phase usw. im PC-Mode 27. Default Language: Auswahl der Mensprache; gleiche Funktion wie die Benutzersteuerung. 28. RGB Filter: Abgleich des Schrfefilters des Scalers fr PC-Mode und YPbPr. 29. Video Filter: Abgleich des Schrfefilters des Scalers fr den Video-Mode. 30. Monitor Sync: Sollte immer auf On stehen damit das Videoformat automatisch erkannt wird. 31.VPC Brightness Reset: Eine nderung dieser Grundeinstellung ist nicht empfehlenswert. 32. Reset All Nvram: Drcken der OK-Taste setzt alle Parameter im Service-Mode ( auch Farbtemparatur, Helligkeit usw.) zurck. 33. Test Pattern: Zeigt ein vom Scaler erzeugtes Testmuster auf dem Bildschirm. Nur im PC-Mode. 34. H.Position: Horizontallage fr PC-Eingang. 35. V.Position: Vertikallage fr PC-Eingang.

LCD12B
First issue 0 / 05

Life Time 00009:30 00005:05 Project Code EU27L04B Panel Resolution 1280 X 720 NvRam Ver. 15 / 94 HXV Res / HFreq 649 X 546 15,68 KHz HXV Total 864 X 625 Mode Num 64 DCLK 81 MHz SDK 2.2 SPB Release Build: Sept 9 2004 17:46:49 Factory Save... TUNER: 09

EN
36. Life Time: The left item means the time added by stand by + TV on The right item display the time of TV-on only. 37. Project Code: as title 38. Panel Resolution: as title 39. NvRam Ver. Display EEPROM data veriosn. 40. HXV Res / Hfreq: timing information. Resolution and H clock 41. HXV Total: timing information. 42. Mode Num: timing information. Sequence of Timing chart. 43. DCLK: timing information. Data clock These (41,42,43,and 44) items above are for development check only. 44.SDK: Designer debug tool revision ( this is information only ) 45. Factory save: save factory parameters.

IT
36. Life Time: Il contatore a sinistra indica il tempo totale di funzionamento in Stand By + apparecchio acceso. Il contatore a destra indica il tempo totale di funzionamento ad apparecchio acceso (ON). 37. Project code: Codice progetto. 38. Panel Resolution: Risoluzione pannello. 39. NvRam Ver: Versione EEPROM. 40. HXV res / Hfreq: Informazione timing. Risoluzione e Clock H. 41. HXV Total: Informazioni timing. 42. Mode Num: Informazioni Timing. Sequenza carta tempi. 43. DCLK: Informazioni Timing. Clock Data. I valori menzionati nei punti 41, 42 43 e 44 sono solo per la fabbrica 44.SDK: 45. Factory save: Parametri memorizzati in fabbrica.

FR
36. Life Time: -Indication de gauche: indique le temps fonctionnement total du TV: On+ Stand by. -Indication de droite: Indique le temps de fonctionnement du TV en On seulement. 37. Project Code: Info code. 38. Panel Resolution: Resolution du panneau dcran. 39. NvRam Ver. Version EEPROM. 40. HXV Res / Hfreq: Information de temps resolution et Horloge H. 41. HXV Total: Information de temps. 42. Mode Num: Information de temps 43. DCLK: Information de temps.Data clock. Ces 4 lignes dinformation sont utilises en dveloppement. 44.SDK: Version de l'outil de debuggage. 45. Factory save: Sauvegarde les paramtres usine.

ES
36. Life Time: Los nmeros de la izquierda muestran la suma de las horas en stand-by + TV encendido. Los de la derecha indican slo las horas de TV encendido. 37. Project Code: informativo 38. Panel Resolution: informativo 39. NvRam Ver. Indica la versin de la EEPROM. 40. HXV Res / Hfreq: informacin de timing. Resolucin y frecuencia H. 41. HXV Total: informacin de timing. 42. Mode Num: informacin de timing. 43. DCLK: informacin de timing. Frecuencia del reloj. Estas 4 funciones anteriores (41,42,43,y 44) son informativas. Slo son para comprobacin. 44.SDK: Herramienta para la revisin de los defectos de diseo (slo para informacin) 45. Factory save: memoriza los valores de fbrica.

DE
Seite 5 des Service-Modes 36. Life Time: Betriebsstundenzhler, links: Summe Standby-Zeit und TV-Ein, rechts: nur TV-Ein-Zeit. 37. Project Code: 38. Panel Resolution: Auflsung der LCD-Panels 39. NvRam Ver. : Version EEPROM-Daten 40. HXV Res / HFreq:Timing-Information (Auflsung und H-Clock) 41. HXV Total: Timing Information 42. Mode Num Timing Information 43. DCLK: Timing Information Data Clock 44.SDK: Version des Entwicklungsdebugtools (nur zur Information). 45. Factory Save: Daten des Service-Modes speichern.

LCD12B
First issue 01 / 05

BLOCK DIAGRAM - SCHEMA SYNOPTIQUE - BLOCKSCHALTBILD - SCHEMA A BLOCCHI - ESQUEMA DE BLOQUES Block Diagram
4 pin

6 pin 16 pin

5 pin

5 pin

Audio Board

PFC/DC+DC Board
10 pin 10 pin 12 pin 6 pin 16 pin
LVDS THC63LVDM83A

30 pin

12 pin

Flash

Scaller PW166B

30 pin

LCD Panel (Invertert)

5 pin

AC Input
Keypad/IR In terface

Keypad Board

5 pin

12 pin

Main Board
AFE AD9883

De-Interlace PW1230

DDC 10 pin 12 pin

UART

DDC

DVI-I DVI Audio

PC PhoneJack Audio Input Y CbCr


Component L/R Audio input

SVideo

SCART1 L/R Audio Composite Input Video

20 Pin

Video Decoder VPC3230D

50 pin FFC

10 pin

50 pin EFC

DVI Receiver HDCP Sil169

Analog Mux. BA7657F

Audio Processor MSP3412G Video Mux. CXA2161R

14 pin

Tuner Module

Teltext SDA555XFL

14 pin

Tuner

Scart Board
SCART2

LCD12B First issue 01 / 05

BLOCK DIAGRAM - SCHEMA SYNOPTIQUE - BLOCKSCHALTBILD - SCHEMA A BLOCCHI - ESQUEMA DE BLOQUES

Video Signal Flow


Tuner SCART 1 Video Output

SCART 2 Video Output MM1234+ ADG779

SCART 2

SCART 1

Composite Video S-Video VPC3230D

Y
Pr/ Cr Pb/ Cb

C X A 2161R

SDA555X FL

BA7657F

PC

AD9883 To Panel

DVI-D

Differetial Sigal

Sil169

RGB 888

Pixelworks PW166B

Y U V 422

RGB 888

THC6 3L VDM83 A

LVDS signal

LCD12B First issue 01 / 05

BLOCK DIAGRAM - SCHEMA SYNOPTIQUE - BLOCKSCHALTBILD - SCHEMA A BLOCCHI - ESQUEMA DE BLOQUES

Audio Signal Flow


SCART 2 Audi o L/R Output

SCART 2

Component Audio

FROM TUNER AUDIO

SCART 1 Audi o L/R Output

Composite Audio L/R Input

P h oneJack L/R Outpu t

DVI AUDIO

SCART 1

CXA7002R

MSP3412G Tuner TDA2822D E arPhone Output

74HC4053D PC Phone-Jack Input

TDA7490

LCD12B First issue 01 / 05

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO
( CONNECTOR BOARD 1/5)

CONNECTOR BOARD
TP 1

J1 1000 OHM 5 5 6 6 TP 2 CVBS_IN L1 CVBS_AV

[P.3] [P.3] [P.3]

TP 3

R1

1K

AUD_CVBS_L

TZMC5V1 D3 2 2 J2 L2 Y . TP 6 S1 S1 G1 . G1 2 4 TP 8 TP 7 75 DN 2 BAV99 3 1 R6 TP 5 1000 OHM

TZMC5V1 D4

DN 1 BAV99

1 G2 2 G3

L3 1000 OHM VC C J A DN 3 BAV99 K A DN4 BAV99 J K S_C

LCD12B First issue 01 / 05

1 2

Bottom View

Bottom View G1

AUDIO MONITOR OUTPUT

3 4

TP 4 C1 C2

R2

1K D1 TZMC5 V1 D2 TZMC5 V1 R5 75 VCC R3 22 K R4 22 K

AUD_CVBS_

6
2210018561 O PEN O PEN L4 IN PUT_DET 1000 OHM J4 7 6 1 2 4 5 3 7 6 1 2 4 5 3 L5 TP22 L6 TP23 C3 TP24 C4 D5 1000P J 1000P J TZMC5 V1 TZMC5 V1 D6 2 20 OHM 2 20 OHM

S_Y VC C

[P.3]

[P.3]

R7 75

J3

[P.5]
S-VIDEO IS INDEPENDENT

SCART2_LOUT

TP 9 TP11

1 3 5 7

2 4 6 8 10 12 14 16 18 20

TP10

AUD_SCART2_L

[P.5] [P.5] [P.3] [P.1]

[P 3]
R8 R9 0 0 R10 1 00K R11 1 00K AUDIO_L_LINE AUDIO_R_LIN E

[P.5] [P.5] [P.5] [P.3] [P.3]


CONNECTOR BOARD

SCART2_ROUT

TP12

TP13

AU D _SCART2_R

TP14 SCART2_S_Y SCART2_S_C +9 V TP20 TP16 TP18

9 11 13 15 17 19

TP15 TP17 TP19

SCART 2_VD_OU T SCART2_S WI TC H

VC C TP21

D7 TZMC5 V1

D8 TZMC5 V1

2072060210

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO
( CONNECTOR BOARD 2/5)

VC C

VC C C5 0.1 U K R12 68 K R15 100 R20 68 K R22 1K Q1 2N3904 R16 47 SCART1_CVBS

CONNECTOR BOARD
K

[P.2]
SCART1_ROUT SCART1_LOUT R13 R14 0 0 R17 D92 1 00K D1 0 R18 C7 1 00K 1000P J 1000PJ TP27 3 5 REVERSE 4 6 7 8 9 D1 4 D1 5 TP33 10 11 12 13 TZMC5 V1 TZMC5 V1 TP35 14 15 16 17 D1 8 TP37 18 19 20 21 TP38 TZMC5 V1 75 R30 TP36 R29 0 SCART1_BLNK[P.4] DATA_OUT TP34 1 TP31 CLK_OUT R25 0 TP32 TP28 TP29 R23 0 SCART1_AL_IN C8 TP25 1 2 TP26 R21 0 S CART1_AR_IN [P.2] J5 (SCART1) SCART1_CVBS_I N R19 75 C6 10U 16V L7 1000 OHM +

DN5 BAV99

[P.2]

[P.2]

[P.2]

TZMC5 V1

TZMC5 V1

[P.2] [P.2] [P.2]

SCART1_BLUE_IN

TP30

[P.2] [P.1]
SCART1_AL_I N

R24

1K D11 TZMC5V1 D12 TZMC5V1

SCART1_SWITCH D13 12.4_ TO_ 14.1V

AUD_SCART1_L

[P.3] [P.3]

[P.2]
S CART1_AR_IN R26 1K R27 22 K R28 22 K

SC ART1_GREEN_IN

AU D_SCART1_R D16 TZMC5V1 D17 TZMC5V1

[P.2]

SCAR T1 _RED_IN

VC C K

VC C

J DN7 BAV99 A L9 1000 OHM J VC C K SCART1_CVBS_IN 1000 OHM

DN6 BAV99C9 0.1 U K A

R31 68 K R32 R33 68 K R35 47 R36 1K S CART1_BLUE 100 Q2 2N3904

[P.3] [P.2]
C12 0.1 U K VC C R38 68 K

SCART1_BLUE_IN

L8 C10 R34 75 10U 16V +

[P.2]
SCART1_VIDEO_OUT

[P.1]

+9 V T R40 R45 C16 O PEN C17 O PEN 470 470 C18 O PEN C19 O PEN AUD_TV_R AUD_T V_L L11 Z22 0 R41 + C15 10U 16V 560

[P.2]
SCART1_ROU SCART1_LOUT

C14 +

VC C Q4 2N3904 DN8 BAV99 J K

VC C

R42 1 100 R46 68 K R50 +9 V 1K 2

[P.2]

10U 16V

R47

CVBS_TV

[P.3]
1000 OHM L10 C13 R43 75

C11 0.1 U K

R37 68 K R39 Q3 2N3904 R44 100 68 K R49

[P.3] [P.3]

R51 22 1

SC ART1_GREEN_IN

10U 16V

[P.2]
+ C21 10U 16V

A +

R4 8

47

J6 +9 V TP39 TP42 1 3 5 7 9 11 13 2060201207 SCL_5V 2 4 6 8 10 12 14 TP40 TP41 TP43 TP44 TP46 TP48 TP49 R55 R57 R59 R62 SCL_TV SDA_TV 100 100 0 0 L13 1000 OHM TU NER_DET TU NER_AC K TP45 TP47

R53 470 2

SCART1_GREEN

[P.1]
VC C K VC C 1K

R60 2N3906 Q7

100

Q6 2N3904 R63 R65 1K 68 S CART1_VIDEO_OUT J 1000 OHM SCART 1_RED_IN CONNECTOR BOARD L12 C22 R58 75 10U 16V +

[P.2]
A

DN9 BAV99C20 0.1 U K

R52 68 K R54 R56 68 K R6 1 R64 1K 47 SCART1_RE D 100 Q5 2N3904

[P.3] [P.3]

Top View (ST)


14 13 2 1
S DA_5V

[P.2]

[P.1]

LCD12B First issue 01 / 05

VIDEO SIGNAL PROCSSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO
( CONNECTOR BOARD)

SCART BOARD

SCART2_AL_IN

R11

1K D1 TZMC5V1 D2 TZMC5V1

AUD_SCART2_L

SCART2_AR_I N

R13

1K R16 22K R17 22K

AUD_SCART2_R D5 TZMC5V1 D6 TZMC5V1 VCC

SCART2_RO UT SCART2_LOUT

R6 R7

0 0

J1
C3 D3 2 R9 R10 100K 100K 1000PJ C4 1000PJ D4 TP1 TP3 1 3 5 TP6 7 9 TP9 11 13 SCART2_S_C_IN TP11 15 17 TP13 19 21

(SCART2) 2 4 REVERSE 6 8 10 12 14 16 18 20 TP14 SCART2_S_Y_IN SCART2_S_Y_IN L4 1000 OH M TP12 TP2 TP4 TP5 TP7 R14 R15 0 0 TP8 TP10 SCART2_AL_IN SCART2_SWITCH D7 12.4 to 14.1V R12 0 SCART2_AR_I N SCART2_S_C_IN

DN2 BAV99 3 1000 OH M L2 R18 75

TZMC5V1

TZMC5V1

SCART2_S_ C

TZMC5V1 D8

D9

CLK_OUT2 DATA_OUT2

VCC DN4 BAV99 3 1 2

TZMC5V1

SCART2_S_Y R19 75

DN3

VCC BAV99

L3 1000 OH M Sc rew Holes

SCART2_ VD_OUT SCART2_LOUT TP93 TP95 SCART2_RO UT TP97 2 4 6 8 OP2 OP OP3 OP OP4 OP TP99 SCART2_S_Y SCART2_S _C +9V TP101 TP104 10 12 14 16 TP103 18 20 1 3 5 7 9 11 13 15 17 19 TP105 TP98 TP100 TP102 SCART2_VD_ OUT SCART2_SWITCH SCART2_DET VCC TP96 AUD_SCART2_R TP94 AUD_SCART2_L

5 4 3 2 H1

9 8 7 6

5 4 3 2 H2

9 8 7 6

Optical Points OP1 OP

HOLE-V8

HOLE-V8

OP5 OP

OP6 OP

OP7 OP

OP8 OP

R27 0

SCART BOARD 30", 32"

J2

LCD12B
First issue 03 / 05

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO
( CONNECTOR BOARD 3/5)

[P.1]

[P.1]

[P.2]

[P.1]
SCART 2_S_C

[P.1]
S_ C

CONNECTOR BOARD

SCART2_S_Y

CVBS_AV

CVBS_T V

[P.1]

S_Y

TT_CVBS_VD

[P.4]
R66 75 R68 O PEN R69 0

+9 V Q8 O PEN R70 O PEN CVBS_VD R71 O PEN C23 O PEN

2 .2U Z

2 .2U Z

2 .2U Z

2 .2U Z

2 .2U Z

2 .2U Z

+5V_PI +5V_PI C30 O PEN

R67

C2 4

C2 5

C2 6

C2 7

C2 8

C2 9

0.1 U K

[P.3]

55

54

53

52

51

50

49

48

47

56

46

45

44 +5V_VOUT

VIN9

VIN8

VIN6

VIN5

VIN3

VIN12

VIN1

+5V_VID

VOUT1

VOUT2

VOUT3

VID_BIAS

VOUT4

43

+9 V RIN4 VOUT5 42 41 40 O PEN 39 38 L14 10 0U 37 36 35 34 33 32 R83 31 R89 30 R90 29 C37 C38 0.1U K 0.1U K 0 0 75 SCART 2_VD_OUT SCL_5V S DA_5V AUD_TV_R AUD_T V_L R81 10 K +5V_PI R82 75 R85 O PEN R86 0 +9 V Q1 0 O PEN R87 O PEN OUT_S_Y R88 C36 O PEN R78 R80 1K 10 K +5V_PI C35 12P J R79 O PEN R73 R74 O PEN 75 R75 R76 0 Q9 O PEN R77 O PEN OUT _S_C C32 O PEN

C3 1 +5V_PI R72 68 K C33 C34

0 .1U K

1 2

VIN13 SYNC_ID VIN11 VIN10 VIN7 VIN4 VIN2 GND_DIG TV_FBLK FBLK_IN1 FNC_TV FBLK_IN2

[P.1] [P.2]

SCART2_S_Y S CART1_CVBS

2.2U Z 2.2U Z

3 4 5 6 7 8 9 10 11 12 13

GND_VID VOUT6 VOUT7 U1 TRAP INTERUPT

[P.3]

CXA2161R

SCL SDA LOGIC MONO PHONO_R

[P.1] [P.3] [P.3] [P.2] [P.2]


O PEN

R84

+5/+12V_VCCA

FNC_VCR AUD_BIAS -5V_GNDA +12V_DIG +5V_DIG

PHONO_L LIN4 ROUT1 LOUT1 RTV LTV

+5V_PI

14

[P.3]

RIN3

RIN2

RIN1

LIN3

LIN2

LIN1

O PEN

+12V L15 L16 Z22 0 +9 V Z22 0 VCC Z22 0 L17

15

16

17

18

19

20

21

22

23

24

25

26

27

+12V_PI

28

+12V 1 C48 0.1 U K

U2 7809ABD2T VI GN D VO 3

C4 0

C4 1 1 C4 2

C4 3

C4 4

C4 5

C4 6

C39 +12V_P I

10U 16V

AUD_MUX_R

[P.5] [P.5] [P.3,5] SCL_5V [P.4] TT_SC L [P.1] SCART2_S WI TC H [P.4] TT_VS [P.1] IN PUT_DET
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 J7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

+9 V

+ 0.1U K 0.1U K 2 16 V 22 U 0.1U K 0.1U K 0.1U K 0.1U K + C49 47U 16V C5 0 0.1 U K A UD_CVBS_ L

C47

10U 16V

AUD_MUX_L

VC C

+5V_PI

+12V

+12V_PI

L19

Z22 0

Z220

[P.1]

[P.1]

[P.2]

L18 + C51 10U 16V C52 0.1 U K C53 0.1 U K

[P.2]

C54 10U 16V

C55 0.1 U K

C56 0.1 U K

C57 0.1 U K

AUDIO_RESET S DA_5V TT_SDA SCART1_S WI TC H TT_HS SCART_FB_E N SCAR T_TT_BLN K SCART_TEXT_B SCART_TEXT_G SCART _TEXT_R OUT _S_C OUT_S_Y C VBS_VD A UD_PC_L AUD_PC_ R AUD_COM P_ L AU D_COMP_R AUDIO_L_OU T AUDIO_R_OUT A UDI O _L_EAR AUDIO_R_EAR

[P.4,5] [P.3,5] [P.4] [P.2] [P.4] [P.4] [P.4] [P.4] [P.4] [P.4] [P.3] [P.3] [P.3] [P.5] [P.5] [P.5] [P.5] [P.5] [P.5] [P.5] [P.5]

1_L AUD_SCART

A UD_CVBS_R

AUD_SCART

1_R

CONNECTOR BOARD

LCD12B First issue 01 / 05

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO
( CONNECTOR BOARD 4/5)

CONNECTOR BOARD
+3.3VDAC U3 C58 0.1 U K VC C WP SC L SD A 8 7 6 5 R99 4.7 K R100

+2.5V 4.7 K 0.1 U K C59

+2 .5VDAC C60

+3 .3VDAC U4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VDD 2.5 VSS VDD 3.3 CVBS VDDA 2.5 VSSA P2.0 P2.1 P2.2 P2.3 HS/SSC VS P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 SDA555x FL P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 VDD 3.3 VSS VDD 2.5 BLANK/COR B G R VDDA 2.5 VSSA XTAL1 XTAL2 RSTP4.3 P4.2 VDD 3.3 VSS P3.7 P3.6 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

+3 .3VDAC

+2 .5VDAC C61

+2.5V C62 0.1 U K

R9 4 R9 5 R9 6 R9 7 R9 8

+3 .3VDAC 0 OPEN 0 OPEN 0 R101 R102 R103 R104 R105

(Bypass Group Delay Circuit for TMM tuner)


+9 V R 106 6.8 K C66 TT_CVBS_VD + C6 3 1.3 K 22U 16V O PEN R 108 R 112 3.3 K R115 470

1 2 3 4

NC NC NC GND

0.1 U K

0.1 U K

EE _SCL EE _SDA

AT 24 C02

LCB INFO LIST I2C _E N RGB _G AI N

OPEN 0 OPEN 0 OPEN

R 107 560 C6 4 Q1 1 2N3904 R114 R117 O PEN 0 O PEN C65 0.1 U K

TT_FSB TT_ FSB BLUE GREEN RED

[P.4]
+3.3V

[P.3]

R 109 220 Q1 2 2N3904

R110 680

R111 680

R 113 680 R 120 47

[P.3] [P.3] [P.3] [P.3]

TT_HS TT_VS TT_SCL TT_SDA

R116 R118 R122 R124

0 0 0 0

TT_ RST n R123

+3.3V R 125 O PEN

Y1 C67 33P J

6M HZ C68 33P J

R119 O PEN R 121 330

[P.4] TT_BLN K
TE XT_B TE XT_G

R 126 BLU E AUDIO_RESET GREEN RED 2N3906 Q13 2N3906 Q1 4 R 127 R 129 2N3906 Q1 5

10 10 10

R128

VC C C69 O PEN R 130 470

[P.4] [P.4]

ADG77 9truthtable IN 0
Q1 6 2N3904

1 + C70 10U 16V

Dout S1 S2
VCC

OPEN

I2C : 0X60

TE XT _R [P.4]

R131

100

[P.2]

SCART1_BLNK

2N3906 Q1 7 R132 75 Q1 8 2N3904 SCART _BK R134 10 K TT_BLNK R 135 470 SEL VC C VC C Q2 0 2N3904 0 6 1 4 U6 S1 S2

C75 2 0.1 U K 5 U5 VC C 3 SCA RT_TT_BLN K VIN GN D VOUT 2 + C71 47U 16V C73 0.1 U K +3 .3VDAC L20 BEAD + C74 10U 16V C72 0.1U K +3.3V

R133

10 K

VD D

Dout GND IN
ADG7 79

[P.3]

[P.3]

SCART_FB_E

R 137

Q1 9 2N3904 R139 R140 150

TT_FSB

VC C VC C 13 C81 + 0.1 U K C82 10U 16V C78 0.1U K 3

U7 2 VIN VOUT GND R 136 681F + C76 47U 16V + 2.5VDA C L21 BEAD C79 0.1 U K + LM317M C77 10U 16V +2.5V

U8 R 141 O PEN SEL C83 10 K C87 O PEN C88 10 K C89 O PEN C90 10 K C91 MM1234 2 16 1 SEL 12 11 14 SEL 7 8 9 SW 1 IN1A IN1B SW 2 IN2A IN2B SW 3 IN3A IN3B

VC C

[P.2] [P.4] [P.2] [P.4] [P.2] [P.4]

SCART1_BLUE

1U Z R 142

OUT 1 OUT 2 OUT 3 GND1 GND2 GND3

3 5 6

SCART_TEXT_B SCART_TEXT_G SCART _TEXT_ R

[P.3] [P.3] [P.3]


+3 .3VDAC PIN11 C84 0.1 U K

LD1117-3.3

R138 681F

TEXT_B

1U Z R 143

C80 10U 16V

SCART1_GREEN

1U Z R 144

CONNECTOR BOARD PIN3 0 C85 0.1 U K P IN44 C86 0.1 U K

MM1234 truth table SW 0 1 RGBout RGB A in RGB B in

TEXT_G

1U Z R 145

SCART1_RED

1U Z R 146

TEXT_R R147 1K R 148 1K

1U Z R 149 1K

LCD12B First issue 01 / 05

15 4 10

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO
( CONNECTOR BOARD 5/5)

CONNECTOR BOARD

NOTE:I 2C ADDRESS SELECT


R151 R150 10 Y2 OPEN 18.432M HZ R152 4.7K R153 4.7K C9 2 3.3P C

C9 3 3.3P C VCC

C9 4 56 P J

L22 Z220

TP 50TP 51 C9 8 56 P J C9 9 56 P J

+ C9 5 100 U 16V

C9 6 470P K

C9 7 1.5N M

64

63

62

59

58

57

55

53

51

52 ANA2_IN+

61

60

56

NC

NC

NC

TP

54

STANDBYQ

ADR_SEL

TESTEN

XTAL_OUT

ANA_IN -

XTAL_IN

[P.3 ] [P.3 ]

SCL_5V SD A_5V

R154 R155

10 0 10 0 C101 OPEN C102 OPEN

1 2 3 4 5 6 7

AUD_CL_OUT

D_CTR_I/O_0

D_CTR_I/O_1

ANA1_IN+

50

I2C_CLK I2C_SDA I2S_SL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2S_DA_IN2 NC NC NC RESETQ

AVSUP AVSS

49 48 47 46 45 44 43 42 41 40 39 38 37 36

C103 0.1U K

C100 10 U 16V

MONO_IN VREFTOP SC1_IN_R SC1_IN_L


U9

C104 C105

330 N Z 330 N Z

R156 R157

47 0 47 0

AUD _M UX _R AUD_ MU X_L

[P.4] [P.4] [P.3] [P.3] [P.3] [P.3] [P.1] [P.1]

VCC L23 Z220

ASG1 SC2_IN_R

8 9 10 11

C106 C107 C108 C109 C114 C115

330 N Z 330 N Z 330 N Z 330 N Z 330 N Z 330 N Z C116 C117 330P J C118 330P J C119 330P J C120 330P J C121 330P J C122 330P J

R158 R159 R160 R161 R162 R163 C123 330P J

47 0 47 0 47 0 47 0 47 0 47 0

AUD_PC _R A UD_PC_ L AUD_COM P_ R AUD_CO MP _L AUD_SCART 2_R AUD_SCA RT2_L

MSP4421K

SC2_IN_L ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L AGNDC

VCC R164 4.7K D1 9

+ C110 100 U 16V

C111 1.5N M

C112 220P Z

C113 470P K

12 13 14 15 16

35 34 33
C127 C124 + 0.1U K 3.3U 35V L24 +9V L25 D2 0 330P J

[P.3 ]

AUDIO_RE SET 1N4148 + C125 22 U 16V

SC2_OUT_R

SC1_OUT_R

SC2_OUT_L

SC1_OUT_L

DACM_SUB

17

DACM_R

DACM_C

DACM_S

DACM_L

CAPL_M

AHVSUP

DACA_L

DACA_R

AHVSS

CAPL_A

VREF2

VREF1

18

19

20

21

22

23

24

25

26

27

28

29

30

31

[P.3 ] [P.3 ]

AUDIO_ R_EAR A UDIO_L_EAR C 128 330P J C 133 330P J

1U Z 1U Z

C126 C132

32

Z220

Z220 C129 C134 10 U 16V 1.5N M + C130 470P K + C131 470U 25V <Spec > 1N4148

[P.3 ] [P.3 ]

AU DI O_R_OUT A UDIO_L_O UT

R165 C135 2 C137 10 U 16V 1 10 U 16V + + R166

47 0 47 0 1000P J C138 1000P J C139 1000P J C140 1000P J C141 1000P J C142 R167 R168 R171 R172 C136 22 0 C145 22 0 C146 22 0 C143 10 U 16V 10 U 16V + 22 0 C144 + 10 U 16V + 10 U 16V + 10 U 16V +

AU DIO_L_LIN E AUDIO_R _LINE SCART 2_LOUT SCART2_R OU T

[P.1 ] [P.1 ] [P.1 ] [P.1 ]

R169

R170

10K

10K

S crew Holes

5 4 3 2
H1

9 8 7 6

5 4 3 2
H2

9 8 7 6

5 4 3 2
H3

9 8 7 6

5 4 3 2
H4

9 8 7 6

Optical Points CONNECTOR OP1 OP OP2 OP OP3 OP OP4 OP OP5 OP OP6 OP OP7 OP BOARD

HO LE-V 8

HO LE-V 8

HO LE-V 8

HO LE-V 8

OP8 OP

OP9 OP

OP10 OP

OP11 OP

OP12 OP

OP13 OP

OP14 OP

OP15 OP

OP16 OP

LCD12B First issue 01 / 05

AUDIO AMPLIFIER SCHEMATIC DIAGRAM - SCHEMA DE LAMPLIFICATEUR AUDIO - AUDIO ENDVERSTRKER - SCHEMA AMPLIFICATORE AUDIO - ESQUEMA DEL AMPLICADOR AUDIO

AUDIO BOARD

J1=>J9 Main board

PWM-STAGE 1

U1 TDA7490L

CN705

G-2-5

PWM-STAGE 2

J2=>CN703 Audio power board

NOTES: 1. Resistor values are in ohm, K = 1,000 ohm, M = 1,1000 000 ohm 2. All resistors are SMD 0603 5% exept where otherwise indicated 3. All capacitors are SMD 0603 5% exept where otherwise indicated 4. Represents PCB common ground

AUDIO BOARD

LCD04B First issue 01 / 05

KEYBOARD SCHEMATIC DIAGRAM - SCHEMA DES CIRCUITS COMMANDES - SCHALTBILD BEDIENTEIL - SCHEMA DEI CIRCUITI TASTIERA - ESQUEMA DE LOS CIRCUITOS MANDOS

J3=> J6 Main board J3


12 11 10 9 8 7 6 5 4 3 2 1 Optical Points

IR BOARD J2=> J3 KeyPad board

J2=> J8 Main board


G2 R1 0 5 4 3 2 1 G1 TP 1 TP 2 TP 3 TP 4 TP 5 EAR_MUTE A udio_R Audio_L + 10U C9 16V 51.1KF

J2
12V

8 6 R1 1 5 16V 51.1KF 12V 4 + 3

100U

100U

J3=> J2 IR board
10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 TP 6 TP 7 TP 8 TP 9 TP 10 TP 11 TP 12 TP 13 TP 14 TP 15 G2 KP D0 KP D1 KP D2 KP D3 KP D4 KP D5 1 1 SW6 3 SW5 3 1 SW4 3 1 SW3 3 1 SW2 3 1 SW1 3

3 1 Q2 2N3 904 2 1 + C1 4 100U 16V R1 5 10K 2

OP1 OP OP2 OP OP3 OP OP4 OP OP5 OP OP6 OP OP7 OP

12 11 10 9 8 7 6 5 4 3 2 1

IR Sensor P/N :05.04856.010 for the USA IR Sensor P/N :05.04833.010 for the EU

H1 HO LE-V 8

9 1 5 9 1 5
R2 10K

10U C4

8 4 8 4

7 3 7 3

6 2 6 2

TP 1 TP 2 L2 TP 3 L3 TP 4 L4 TP 5 KP D0 TP 6 KP D1 TP 7 KP D2 KP D3 TP 8 KP D4 TP 9 TP 10 KP D5

2 1

V5S

33 0

R4

4 3

V5S

G2 J2 20L1033010 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 G2

J2
G1

TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

33 0

R1

LE D1 GREEN/RED

H2 HOL E-V8
R8 1K

TSOP4856

U1

2 + C1 4.7U 25V

1 2 3

VOUT GND VCC

G1
R1 10K Q1 2N3906 + C1 2 100U 16V + C1 3 100U 16V R9 1K

R2 330

TDA2 822D U1

R3 5.1K
7

V5S
12V R5 C1 0 1 16V R1 2 39 4.7 R6 16V C6 0.1U 25V K 39 R1 3 4.7 C7 0.1U 25V K D1 TZMC 5V 1 D2 TZMC 11 D3 TZMC 5V 1 C1 1000P 7 6 1 2 4 5 3

J1
7 6 1 2 4 5 3 2210165091

C2 1000P

C1 1

C3 100 0P

R7 1K

C15 100U 16V

C16 100U 16V

D4 TZMC 5V 1

D5 TZMC1 1

D6 TZMC 5V 1

R1 4 47K

V5S

D7

V5S

R3 10K

1N4148

G1

KEYPAD BOARD
2 5 4 4 2 5 4 2 5 4 2 5 4 2 5 4

Q3 2N3904 R4 10K

6 7 8 9 H1 HOLE -V8 1

2 3 4 5 H2 HOLE -V 8

6 7 8 9 1

2 3 4 5

Optical

Points OP1 OP OP2 OP OP3 OP OP4 OP OP5 OP OP6 OP OP7 OP

OP8 OP

OP9 OP

OP10 OP

OP11 OP

OP12 OP

OP13 OP

OP14 OP

LCD12B First issue 01 / 05

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
MAIN BOARD 1/11)

+5VS

MAIN BOARD
K K DN 1 BAV99 TP13 6 DN 2 BAV99

DN 3 BAV99

J2 J 7 6 1 2 4 5 3 7 6 1 2 4 5 3 L1 TP 4 L2 220 OHM R5 2 2 C7 TP13 7 C8 D1 1000P J 1000P J TZMC5 V1 TZMC5 V1 D2 1K R9 O PEN TP 8 220 OHM R3 1K AUD_PC_L AUD_PC_R R10 O PEN

[P.2] [P.2]

J DN 4 BAV99 K

J J1 6 1 7 2 8 3 9 4 10 5 D-Sub15 17 R1 G1 B1 TP 7 TP 1 TP 3 TP 6 R6 75 R7 75 R1 R2 R4 R8 75 47 47 47 C4 47P 50V J PC_5V C5 47P 50V J C6 47P 50V J

AUDIO PC INPUT
A RED_PR_IN GREEN_YP_IN BLUE_PB_IN

1 1

16

D3

1 1 2 OP 4 OP

D4 TZMC5 V1

TP 2 GSDA TP 5 TP 9 TP10 GSCL

11 12 13 14 15

[P.3] [P.3] [P.3]

TZMC5 V1

D26 27V

D27 27V

D5 TZMC5 V1 D7 R11 R12 1K 1K TP14 2 TP14 3 D9 +5VS 1 D10 1N4148 PC_5V 1 1N4148 R15 4.7K G SCL G SDA TZMC5 V1 D30 TZMC5 V1 R16 4.7K 8 7 6 5 VC C WP SC L SD A 2 2 C1 2 C1 0 C1 1 0.1U K

D6 TZMC5 V1

D8 RGB_VS RGB_HS R13 R14 U1 0 .1U K 0 .1U K C1 3 1 2 3 4 5 6 7 8 C1+ V+ C1C2+ C2VT2OUT R2IN SP232ECN 47 47 C9 VCC GND T1OUT R1IN R1OUT T1IN T2IN R2OUT +5VS 0.1U K 16 15 14 13 12 11 10 9 Optical Points OP 1 OP RX TX D OP 2 OP OP 3 OP OP 5 OP OP 6 OP OP 7 OP

[P.3] [P.3]

UART_R X UA RT_T X RX TX D

[P.4] [P.4]
OP 8 OP OP 9 OP OP10 OP OP11 OP OP12 OP OP13 OP OP14 OP OP15 OP OP16 OP

C1 4

U2 A0 A1 A2 GND 1 2 3 4

0.1U K

0.1U K

MAIN BOARD

AT24C02A

D31

Screw Holes

5 4 3 2 H1 HOLE-V8

9 8 7 6

5 4 3 2 H2

9 8 7 6

5 4 3 2 H3

9 8 7 6

5 4 3 2 H4 HOLE-V8

9 8 7 6

5 4 3 2 H6 HOLE-V8

9 8 7 6

5 4 3 2 H8 HOLE-V8

9 8 7 6

HOLE-V 8

HOLE-V 8

LCD12B First issue 01 / 05

TZMC5 V1

TZMC5 V1

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
(MAIN BOARD 2/11)

+3V_DDV I

R1 8 R1 7 O PEN

OPEN

Main BOARD
K K K K K K

+5VS

C1 5 O PEN L3 DN 10 O PEN OPEN

C1 6 O PEN

R2 0 R1 9 O PEN

OPEN GRE[0. .7]

J 31
J3

DN5 O PEN

DN6 O PEN

DN7 O PEN

DN8 O PEN

DN9 O PEN

[P.4 ] [P.4 ]
TP 13 8 D2 D1 D0 D2 + D1 + D0 + IDCK+ ID CK -

GFBK DVI_C K G PEN GVS GHSS OG R2 2 OPEN

R2 1

OPEN

17 18

[P.4 ] [P.4 ] [P.4 ]

R2 3 R2 4 R2 5

OPEN OPEN OPEN

1 2 3 4 5 6 7 8

10 11 12 13 14

19 20

21 22 23

15 16

TP 21 VD3 3 +3V_DDV I OPEN C2 5 OPEN C2 6 OPEN C2 7 OPEN C2 8 OPEN C3 5 OPE N C3 6 OPEN C3 7 OPEN C3 8 OPEN L5

C3 C5_ C4 32

C1 C5 C2

25 27 29 30 26 28

24

1 9 17 2 10 18 3 11 19 4 12 20 5 13 21 6 14 22 7 15 23 8 16 24

5 6 7 8 5 6 7 8

4 3 2 OPEN 1 4 RN2 3 2 OPEN 1


RN1

GRE7 GRE6 GRE5 GRE4 GRE3 GRE2 GRE1 GRE0

[P.4]

31

TP 11 TP 12 TP 13 TP 14 TP 15 TP 16

[P.2 ]

C1 7 O PEN

C1 8 O PEN

C1 9 O PEN

C2 0 O PEN

+5VS TP 17 TP 18 TP 19 TP 20 HO T_ PLUG L4 OPEN C2 1 22U OPEN C2 2 OPEN

+5V_EDI D

QO1 QO0 HSYNC VSYNC DE OGND ODCK OVCC CTL3 OCK_INV HS_DJTR GND VCC QE23 QE22 QE21 QE20 QE19 QE18 QE17 QE16 OVCC OGND QE15 QE14

1 D1 7 1 D1 8

2 O PEN 2 O PEN

U3

5 6 7 8 5 6 7 8

4 3 2 OPEN 1 4 RN4 3 2 OPEN 1


RN3

GGE7 GGE6 GGE5 GGE4 GGE3 GGE2 GGE1 GGE0

GGE [0..7]

[P.4]

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

OPEN
K 1 1
D3 2 OPEN D3 3 DN 13 O PEN

+5VS

AV DD L34 OPEN

+3 V_ADVI

C3 0 OPEN DN 14 O PEN ADP WR L35 OPEN U6

C3 1 OPEN

C3 2 OPEN

C3 3 OPEN

OGND QO23 OVCC AGND RX2+ RX2AVCC AGND AVCC RX1+ RX1AGND AVCC AGND RX0+ RX0AGND RXC+ RXCAVCC EXT_RES S PVCC PGND RESERVED SCL

51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

QO2 QO3 QO4 QO5 QO6 QO7 OVCC OGND QO8 QO9 QO10 QO11 QO12 QO13 QO14 QO15 VCC GND QO16 QO17 QO18 QO19 QO20 QO21 QO22

SII169

OPEN

QE13 QE12 QE11 QE10 QE9 QE8 OGND OVCC QE7 QE6 QE5 QE4 QE3 QE2 QE1 QE0 PDOZ SCDT STAG_OUT VCC GND PIXS SDA PDZ RESETZ

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

5 6 7 8 5 6 7 8

4 3 2 1 OPEN 4 RN6 3 2 OPEN 1


RN5 R2 8 OPEN

GBE7 GBE6 GBE5 GBE4 GBE3 GBE2 GBE1 GBE0 DVI _PDO DV I_SCDT +3V_DDV I

GBE [0..7]

[P.4 ]

32

[P.6 ] [P.6 ]

R2 9

OPEN R3 0 R3 2 OPEN OPEN C2 3 OPEN R3 4 OPEN +3V_DDV I

GND

+3V_DDV I

+5V_EDI D +5V_EDI D

C3 9 LD1117-3. 3 OPEN

C4 0 47U OPEN

C4 1 OPE N

+3V_DDV I +3 V_ADVI D2 + D2 D1 + D1 D0 + D0 IDCK+ ID CK Q21 3 2N39062 R186 10K R188 1K +9V DVI_SCL_3V R187 +3 V_PDVI R3 8 O PEN DVI_SDA_3V

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

OPEN

+3 V_PDV I

VIN

VOUT

2 D2 3

1 O PEN

S II169 _RST Z

[P.6 ]

OPEN
[P.2]

[P.2 ]

R3 9 OPEN

R3 5 OPEN

Q1

Q2

[P.2]

DVI_SCL_3V

2
OPEN

3 3
OPEN

2
R4 0 OPEN R4 1 OPEN

U4

8 7

VCC WP SCL SDA


O PEN

A0 A1 A2 GND

1 2 3 4

R3 6 OPEN

R3 7 OPEN

+3V_DDV I

C2 4 O PEN

[P.2 ]

Q3

Q4

DVI _SCL

6 5

[P.2]

DVI_SDA_3V

2
OPEN

3
OPEN

DVI _SDA

AV_SE L LOW HIGH


R189

OUTPU T DVI PC
R4 3 OPEN +3V_ADVI R4 2 O PEN

+3V_DDV I

10K

+9V L32 TP 23 1 OPEN R2 6 OPEN ZD1 O PEN ZD2 O PEN [P .2] AUD _DVI_L 1U K R172 47K +9V TP 23 3 3 R173 1K R174 27K R175 1U K +9V R178 27K R176 47K R177 1K Q18 2N3904 10 0 AUD _DVI_L [ P.2] +9V R170 27K R171 10 0 Q17 2N3904

C231 + 10 U 16V

C232 0.1U K

Q22 2N3904

PC_AUDIO_SEL R190 10K 1K

[P .6]

R2 7 OPEN

C171

16 5 3

J4

U 37C 74HC 4053

AU D_PC_DVI_L

[P .7]

L33

OPEN R3 1 OPEN R3 3 OPEN ZD3 O PEN ZD4 O PEN AUD_DVI_R [ P.2] [P .1] A UD_PC_ L

6 7 8

4
C172

TP 23 2

R191 OPEN

2210018551

OPEN
DVI AUDIO input

C173 [P .2] AUD_DVI_R 1U K

Main BOARD
16 12
+9V 1K R181 R182 27K R183 10 0 Q20 2N3904

R180 47K

U37A

11

R179

10 0

Q19 2N3904

14 13
74HC 4053 R192 OPEN

AUD_PC_ DVI_ R

[P .7]

C174 [P .1] AUD_PC _R 1U K

R184 47K R185 1K

LCD12B First issue 01 / 05

6 7 8

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
(MAIN BOARD 3/11)

Main BOARD
R164 C216 470K +5VS 470P 50 V K 0.01U K 0.01U K + L31 Z220 R4 7 R4 9

R4 4

R4 5

OPEN

GBLKSPL

[P .4 ] R4 6 C4 2 3.3K .039U 16 V K

47 47 C4 3 PV DD AV DD 3900P 50 V K

Trac e and Components Close IC


PV DD VD3 3

R165 C217

C229

C 230 1U K C4 7 0.1U K

GVM ID

[P.9]

COMP _CRPR

2 16V 10 U
C219

1 C218
68K

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

C221

0.01U K

U3 2

[P.4]
HIN_ 1 HIN_ 2 HD_ O R_out VCC G_out CON_IN CON_ O CTL B_out VD_out VIN_ 2 24 23 22 21 20 19 18 17 16 15 14 13
C5 3

GCOAS T 0 .22U K BA IN

GND VD CLAMP MIDSCV GND PVD PVD FILT GND VSYN C HSYN C COAST GND VD VD GND GND VD D VD D GND

[P.9]

5
CN8 OPEN GB E[0..7 ]

0.01U K +

COM P_ CY PY

2 16V 10 U

1 C220

CN7 OPEN

[P.9]

CO MP _CBPB

2 16V 10 U
C223

1 C222

0.01U K +

[P.1]

RE D_PR_IN

2 16V 10 U
C225

1 C224

0.01U K +

[P.1]

GR EEN_ YP _IN

2 16V 10 U
C227

1 C226

1 2 3 4 5 6 7 8 9 10 11 12

RIN_ 1 HDdetect GIN_ 1 GND BIN_ 1 GND RIN_ 2 GND GIN_ 2 GND BIN_ 2 VIN_ 1
BA7657 F

C5 6 C5 8

0 .22U K

GA IN

1000 P J SOG IN 50V 0 .22U K 0 0 GVR EF RA IN

C6 1

0.01U K +

[P.1]

GND VD GND VSOUT SOGOUT HSOUT DATACK GND VD D R7 R6 R5 R4 R3 R2 R1 R0 VD D VD D GND

BLUE_PB_ IN

TW O_OPTION

TWO_OPTION LO W HIGH

OUTPUT PC Y Pr Pb

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

C6 4 0.1U K

CN9 OPEN

2 16V 10 U

1 C228

RG B_VS RG B_HS

[P.4] [P.4]

SCL _CP U SDA_ CP U

R5 1 R5 2

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

GND VD BAIN GND VD VD GND GAIN SOGIN GND VD VD GND RAIN A0 SCL SDA REF BYPASS VD GND

U9 AD9 883KST-110

I2C Addr: 0x98

GND B0 B1 B2 B3 B4 B5 B6 B7 VDD GND G0 G1 G2 G3 G4 G5 G6 G7 GND

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

AD BE0 AD BE1 AD BE2 AD BE3 AD BE4 AD BE5 AD BE6 AD BE7 AD GE AD GE AD GE AD GE AD GE AD GE AD GE AD GE 0 1 2 3 4 5 6 7

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

RN7 47 RN8 47

8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5

GBE0 GBE1 GBE2 GBE3 GBE4 GBE5 GBE6 GBE7 GGE0 GGE1 GGE2 GGE3 GGE4 GGE5 GGE6 GGE7

[P.4]

L37

Z220 Q24 U1 4 LD1117-3. AV DD L8 Z220

+5VS R194 OPEN

SI4431D Y- T1

ADP WR

GND

3 2 1

8 7 6 5

VIN

VOUT

AD RE AD RE AD RE AD RE AD RE AD RE AD RE AD RE R163 A DCK C 210 O PEN C 211 O PEN 0

0 1 2 3 4 5 6 7

1 2 3 4 1 2 3 4

RN 11 47 RN 12 47

8 7 6 5 8 7 6 5

GRE0 GRE1 GRE2 GRE3 GRE4 GRE5 GRE6 GRE7

(OPEN)

C7 4 0.1U K

C7 5 47U 16V

R5 8 L7

0 30 OHM GCL K

L30 30 OHM

GGE [0..7]

[P.4]

RN9 47 RN 10 47

CN 10 OPEN

CN 11 OPEN

CN 12 OPEN GRE[0. .7]

[P.4]

[P.4]

Main BOARD U5 L10 Q25 OPEN Z220 R195 OPEN C233 OPEN VD3 3

DVI_CK

C6 5 O PEN

C6 6 O PEN

GND

AD PW R_ON

1 2
R196 OPEN

VIN

VOUT

2
A DHS R5 9 R6 0 47 47 C6 7 OPEN C6 9 0.1U K VD33 ADS OG C6 8 OPEN

LD1117-3. 3 C3 4 0.1U K

GFBK GVS

[P.4] [P.4]

C2 9 47U 16V

ADVS VD33

16

U1 5 PV DD L11 Z220

R6 1 U1 1 C7 0 220P 50 V J R6 2 D2 4 VD3 3 33K 1K VD3 3 U1 3 36 0 [P .6] GAF EO E

VIN GND

VOUT

[P.7 ]
1
+ C8 8 47U 16V

MV _EN

1 2 3

VC C

U1 2

OE A GND

VCC

1 2 4 3 9 10 11

C8 7 0.1U K

LD1117-3. 3

1A 1B 1R 2A 2B 2R GND

CX1 RCX1 1Q 1Q 2Q 2Q CX2 RCX2

14 15 13 4 5 12 6 7 1

2 R6 3
1N4148 D2 5 R6 4

1 2

OE A GND

VCC

74LVC1 G126 PV DD

AV DD

VD3 3

1N4148 C7 3 220P 50 V J

1K

3
+ C7 1 1U 50V R6 6 47K

R6 5

47 C7 2 O PEN

GHSS OG

[P.4]

74LVC1 G126

VD3 3 R6 7 221K F

C7 8 0.1U K

C7 9 0.1U K

C8 0 0.1U K

C8 1 0.1U K

C8 2 0.1U K

C8 3 0.1U K

C8 4 0.1U K

C8 5 0.1U K

C8 6 0.1U K

C7 6 0.1U K

C8 9 0.1U K

C9 0 0.1U K

C9 1 0.1U K

C9 2 0.1U K

C9 3 0.1U K

C9 4 0.1U K

C9 5 0.1U K

C9 6 0.1U K

LCD12B First issue 01 / 05

74LV123PW

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
(MAIN BOARD 4/11)

TP24

TP25 E3 W1 3 Y13 P3 P4 RESET MCKEXT DCKEXT XTALI XTALO RXD TXD IRRCVR 0 IRRCVR 1 PORTA0 PORTA1 PORTA2 PORTA3 PORTA4 PORTA5 PORTA6 PORTA7 PORTB0 PORTB1 PORTB2 PORTB3 PORTB4 PORTB5 PORTB6 PORTB7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 D1 1 D1 2 D1 3 D1 4 D1 5 P1 P2 N3 N4 R1 R2 T1 T2 R3 U1 U2 R4 T3 V1 W1 V2 T4 U3 Y1 W2 F4 F3 E1 F2 F1 G2 G1 H1 H4 H3 H2 J1 J2 J4 J3 K1 M3 M4 N2 M1 L2 L1 K2 M2 N1 E2 D1 TP26 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RD n WR n TP29 TP30 TP31 ROMOEn [P.6] ROMWEn [P.6] CS0n CS1n A[1..19] C97 22P J W1 2 DC LK R V13 U1 3 Y13 Y15 R1 9 T20 R1 8 R1 7 T18 U1 9 T17 V20 U1 8 V19 W2 0 W1 9 Y20 V17 U1 6 W1 8 Y19 Y18 V16 U1 5 Y16 V15 W1 6 W1 5 Y12 W1 1 Y11 U1 0 V10 W1 0 Y10 W9 Y9 W8 V8 U8 Y8 Y7 W7 Y5 V6 U6 W5 Y4 V5 Y3 V4 Y2 DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DG DG DG DG DG DG DG DG 0 1 2 3 4 5 6 7 R69 30 OHM RVS RHS RDE DR[0..7] C98 22P J D CLK

Main BOARD
[P.2,3] [P.2,3] [P.2] [P.2,3] [P.2,3]
G FBK GCL K G PEN GV S G HSSO G H1 9 G2 0 J17 G1 9 GCLK GPENSO G GV S GH S H1 7 H1 8 F19 F20

[P.6] RESET
R6 8 X607 TP27 GBLKSPL GCOAST C99 O PEN Y1 GFBK GREF GBLKSPL GCOAST X608 C 100 14.318 MH Z 18P J VCPU33 R7 1 R7 2 V33 [P.1] [P.1] RX TX D R70 R73 470 10 K TP28 SDA_CPU SCL_CPU RX D TX D 18P J

[P.6]
DCLK DV S DH S DCKEXT DE N DRE0 DRE1 DRE2 DRE3 DRE4 DRE5 DRE6 DRE7 D[0..15] DGE DGE DGE DGE DGE DGE DGE DGE U16C 0 1 2 3 4 5 6 7

DCLK RV S RHS RDE

[P.5] [P.5] [P.5] [P.5]

[P.2,3] [P.2,3]

[P.5]

R212

[P.2,3]

M2 0 N1 9 N1 8 N1 7 N2 0 P20 P19 R2 0 F18 E19 E20 J18 H2 0 J19 J20 K19 D1 6 A18 C1 7 B18 A19 B19 A20 D1 8 K20 L17 L18 L19 L20 M1 8 M1 7 M1 9 E17 C1 9 B20 C2 0 E18 F17 D1 9 D2 0 B15 A16 C1 5 D1 5 B16 A17 C1 6 B17

GRE0 GRE1 GRE2 GRE3 GRE4 GRE5 GRE6 GRE7 GGE GGE GGE GGE GGE GGE GGE GGE GBE0 GBE1 GBE2 GBE3 GBE4 GBE5 GBE6 GBE7 GRO0 GRO1 GRO2 GRO3 GRO4 GRO5 GRO6 GRO7 GGO0 GGO1 GGO2 GGO3 GGO4 GGO5 GGO6 GGO7 GBO0 GBO1 GBO2 GBO3 GBO4 GBO5 GBO6 GBO7 V25P VCPU33 L14 Z22 0 V3P 0 1 2 3 4 5 6 7 U 16A

R213

G RE[0. .7]

G RE0 G RE1 G RE2 G RE3 G RE4 G RE5 G RE6 G RE7 GGE GGE GGE GGE GGE GGE GGE GGE GBE0 GBE1 GBE2 GBE3 GBE4 GBE5 GBE6 GBE7 0 1 2 3 4 5 6 7

C1 D3 E4 D2 C2 B1 B2 A1 C4 D5 B3 A2 A3 C5 D6 B4 A4 C6 B5 A5

3.3 K

3.3 K

3.3 K

GGE[0..7]

[P.2,3]

[P.2] [P.2] [P.9] [P.9] [P.11] [P.11] [P.7] [P.7]

SDA_CPU SCL_CPU TT_SDA TT_SCL DI_SDA DI_SCL PW R_ON LCD_B R

3.3 K

IRRCVR_3V [P.6]

DG[0..7]

[P.5]

U16D

[P.6]

R74 C 101 2.2 U K 16V

10 K 3.3 K 3.3 K

PW M_BR VR Y 0 VR Y 1 VR Y 2 VR Y 3 VR Y 4 VR Y 5 VR Y 6 VR Y 7

PW166B-1 0T Misc

G BE[0..7]

[P.2,3]

PW166B-1 0T Display Port

PW166B-1 0T Graphics Port

V33

[P.11] [P.11] [P.11] [P.11] [P.11] [P.11]

VCLK VPEN VVS VH S VFI EL D V GU[0. .7]

D1 2 C1 3 A14 B14 A15 V GU0 V GU1 V GU2 V GU3 V GU4 V GU5 V GU6 V GU7 VBV0 VBV1 VBV2 VBV3 VBV4 VBV5 VBV6 VBV7 D8 C8 B7 A7 B8 D9 C9 A8 B9 A9 B10 A10 D1 1 A11 C1 2 B13

VCLK VPEN VVS VHS VFIELD VY 0 VY 1 VY 2 VY 3 VY 4 VY 5 VY 6 VY 7 VUV0 VUV1 VUV2 VUV3 VUV4 VUV5 VUV6 VUV7 V33 VCPU33 U 16B

[P.11] VRY[0..7]

DBE0 DBE1 DBE2 DBE3 DBE4 DBE5 DBE6 DBE7 DRO0 DRO1 DRO2 DRO3 DRO4 DRO5 DRO6 DRO7 DGO0 DGO1 DGO2 DGO3 DGO4 DGO5 DGO6 DGO7 DBO0 DBO1 DBO2 DBO3 DBO4 DBO5 DBO6 DBO7

DB 0 DB 1 DB 2 DB 3 DB 4 DB 5 DB 6 DB 7

DB[0..7]

[P.5]

R198

R199

TP33 TP35 VCPU33 TP36 R75 R7 6 R77 R78 4.7 K O PEN 4.7 K 4.7 K

PW166B-1 0T Video Po rt

TM S D1 3 TC K A6 TD O W3 A13 U5 B6

CPUTM S CPUTC K CPUTD O MODE0 MODE1 MODE2

RD WR BHEN ROMOE ROMWE RAMOE RAMWE CS0 CS1 EXTIN T NM I

TP32 TP34 CS0n CS1n

[P.6] [P.6]

[P.11]

VBV[0..7]

NM I

[P.6]

R8 1 R80 R7 9

O PEN 0 O PEN

R 197

O PEN

VV S

[P.11]

NO TE: Upon reset, the on-board A/D and video decoder will be tri-stated.
VCPU33 V3P U17 8 7 6 5 VC C WP SC L SD A AT 24C32 SCL_CPU SDA_CPU C2 0.1 U K 1 U34 8 7 6 5 VC C NC SCL1 SCL0 SDA1 SDA0 EN GN D PCA9515D P SDA_5V PW R_O N MAIN BOARD 1 2 SCL_CPU 3 SDA_CPU 4 VCPU25 NC NC NC GND 1 2 3 4

R8 3

R8 4

C1 0.1 U K U33 8 7 6 5 VC C NC SCL1 SCL0 SDA1 SDA0 EN GN D PCA9515DP 1 2 3 4 R 210 R 211 0 0 SCL_CPU SDA_CPU C102 0.1 U K

2.2 K

R82

27

2.2 K

VCPU25

SCL B12 C3 C10 C11 C14 G3 G1 8 K18 L3 P18 V11 V14 Y14 V7 C7 C18 K3 U20 V9 V12 V18 V3 Y6 Y17 SDA

C 103 0.1 U K

C 104 0.1 U K

C105 0.1U K

C106 0.1 U K

C 107 0.1 U K

C108 0.1U K

C 109 0.1 U K

C 110 0.1U K

C 111 0.1 U K

C112 0.1 U K

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD1 0

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14

[P.6] RESET
U1 8 1 2 3 NC VD D VSS NC RE S V6300L 4 R87 +5VS 5 C 128 0.1 U K 470 4 R88 1K 5 2 3 SW 1 1

VC C VCPU33 R8 5 R8 6

PW R_O N VCPU33

[P.4] [P.4]

PW166B-1 0T

U 16E

Power and Ground

GND 1 GND 2 GND 3 GND 4 GND 5 GND 6 GND 7 GND 8 GND 9 GND1 0 GND1 1 GND1 2 GND1 3 GND1 4 GND1 5 GND1 6 GND1 7 GND1 8 GND1 9 GND2 0 GND2 1 GND2 2 GND2 3 GND2 4 GND2 5

2.2 K

2.2 K

SCL_5V

A12 B11 D4 D7 D10 D14 D17 G4 G1 7 K4 K17 L4 P17 T1 9 U4 U7 U9 U11 U12 U14 U17 W4 W6 W1 4 W1 7

LCD12B First issue 01 / 05

+ C 116 100U 16V

C117 0.1 U K

C 113 0.1 U K

C 114 0.1 U K

C 118 0.1 U K

C 119 0.1 U K

C120 0.1U K

C121 0.1 U K

C 122 0.1 U K

C123 0.1U K

C 124 0.1 U K

C 125 0.1U K

C 126 0.1 U K

C127 0.1 UK

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
(MAIN BOARD 5/11)

[P.4] [P.4] [P.4] [P.4]

DCLK RV S RH S RD E

V33 DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 C 129 O PEN C130 O PEN C 131 O PEN 1 C 132 DRLV7 0.1U K DRLV5 DGLV 0 2 3 4 5 DGLV 1 DGLV 2 V33 DGLV 6 8 9 OPEN C 133 DGLV 7 0.1U K DGLV 3 DGLV 4 10 11 12 13 V33 8 7 6 5 OPEN DGLV 5 DBLV 0 R92 O PEN DGLV 6 DRLV7 DGLV 1 DGLV 5 DGLV 2 DGLV 3 DGLV 7 DGLV 4 DBLV 6 14 15 16 17 DBLV 7 R93 10 K DBLV 1 DBLV 2 18 19 20 21 OPEN DBLV 3 DBLV 4 DBLV 5 V33 25 26 8 7 6 5 OPEN DHS C 138 0.1U K DVS DBLV DBLV DBLV DBLV DBLV DBLV DBLV DBLV 0 1 2 3 4 5 6 7 27 28 22 23 24 6 7 U19 VC C TXIN5 TXIN6 TXIN7 GND TXIN8 TXIN9 TXIN10 VC C TXIN11 TXIN12 TXIN13 GND TXIN14 TXIN15 TXIN16 VC C TXIN17 TXIN18 TXIN19 GND TXIN20 TXIN21 TXIN22 TXIN23 VC C TXIN24 TXIN25 T HC63LVDM83A T.L. TXIN4 TXIN3 TXIN2 GND TXIN1 TXIN0 TXIN27 LVDS GND TXOUT0TXOUT0+ TXOUT1TXOUT1+ LVDS VCC LVDS GND TXOUT2TXOUT2+ TXCLK OUTTXCLK OUT+ TXOUT3TXOUT3+ LVDS GND PLL GND PLL VCC PLL GND PWR DWM TXCLK IN TXIN26 GND 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 L17 34 Z22 0 33 32 31 30 29 D CLK DEN C 137 0.1U K 1 RX IN2RXIN2+ RXCLKIN RXCLKIN + RX IN3RXIN3+ C 134 0.1U K 2 1 Z22 0 + C 135 22U 16V RX IN0RXIN0+ RX IN1D RLV1 D RLV0 D RLV6 VC C L15 D RLV4 D RLV3 D RLV2

[P.4] DR[0..7]

DR2 DR0 DR6 DR3 DR4 DR1 DR5 DG0

RN13 47 5 6 7 8 5 6 7 8 RN14 47 4 3 2 1 4 3 2 1

TP39 TP40 TP41 TP42 TP43 TP44 TP45 TP46 TP47 TP48

DRLV2 DRLV0 DRLV6 DRLV3 DRLV4 DRLV1 DRLV5 DGLV 0

Z22 0

20D2010215

CN14

V33 RXIN1+ L16

[P.4]

DG[0..7]

RN15 47 DG6 DR7 DG1 DG5 DG2 DG3 DG7 DG4 5 6 7 8 5 6 7 8 RN16 47 4 3 2 1 4 3 2 1

CN15

DG0 DG1 DG2 DG3 DG4 DG5 DG6 DG7

FOR

CMO 27" , 30" LCD CONNECTOR

CN16

V33

LVDS_EN + 2 C 136 22U 16V

[P.4]

[P.4]

RN17 47 DB[0..7] DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 5 6 7 8 5 6 7 8 RN18 47 4 3 2 1 4 3 2 1

CN17

MA IN BOA RD

CN18

LCD12B First issue 01 / 05

OPEN

G2

G2

TP49

RXIN3+ 1 RX IN33 RXCLKIN + 5 RXCLKIN - 7 RXIN2+ 9 RX IN211 RXIN1+ 13 RX IN115 RXIN0+ 17 RX IN019 21 23 25 27 29

G1

R89 R90 R91

47 47 47

DCLK DVS DHS DEN

TP37 TP38

Main BOARD
J5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 G1

TP14 0

CN13

OPEN

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
(MAIN BOARD 6/11)

Main BOARD
[P.4] [P.4] [P.4]
ROMOE n ROM WE n RESET R95

VCPU33 R94 0 O PEN FW Pn A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 26 28 11 12 14 47 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9

U20 AT 49BV8192A(T) VPP CE OE VCC WE RP WP BYTE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 FCEn D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 GND GND

13 VCPU33 37 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 46 27 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C139 0.1 U K R98 1K

+5VS R96

Q1 3 2N3906 2 3

+5VS L18

Z22 0

2
10 K

2N3904 2N3906
R99

R97 1K

+5VS R100

[P.6]

LED1_SEL 1K

1 2 R 101 10 K

Q1 5 2N3904

Q1 4 2N3906 2 3

4 CN1 9 O PEN

10 K

R 103 R 102 1K

470 R 104 10 K

IRRCVR_3V

[P.4]

R 105

[P.6]

3 1 10 K VCPU33 2 R106 Q1 6 2N3904

LED2_SEL 1K

R135 OPEN

R107 3.3 K

R108 3.3 K D0 D1 D2 D3 D4 D5 D6 D7 A1 A3 A5 A7 A8 A10 A13 A15 A16 A18 C140 0.1 U K 18 16 14 12 9 7 5 3 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 GN D TP50 12 TP51 11 TP52 10 TP53 9 TP54 8 TP55 7 TP56 6 TP57 5 TP58 4 TP59 3 TP60 2 1 12 11 10 9 8 7 6 5 4 3 2 1 J6

20

U21 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 2 4 6 8 11 13 15 17 1 19 KPD0 KPD1 KPD2 KPD3 KPD4 KPD5 KPD6

KPD[0. .6] KPD KPD KPD KPD KPD KPD KPD TP61 8 7 6 5 8 7 6 5 R109 R110 R111 R112 R113 R114 R115 C S0n [P.4] 0 1 2 3 4 5 6

[P.4] D[0..15] [P.4] A[1..19]


VCPU33 A2 A4 A6 A9 A11 A12 A14 A17 A19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 20L1023060 J7 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 VCPU33

VCC

C S0n

CN2 0 1K 1K 1K 1K 1K 1K 1K 22P 1 2 3 4 1 2 3 4

CN21 22P

10

74AHC244 VCPU33

C141 0.1 U K 20 U22 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74AHC244 2 4 6 8 11 13 15 17 1 19 D8 D9 D10 D11 D12 D13 D14 D15 18 16 14 12 9 7 5 3

R116 3.3 K

R 118 O PEN

R117 3.3 K

[P.4] ROMOE

n D15 D14 D5 D4 D3 D2 D9 D8

ROM WE n D7 D6 D13 D12 D11 D10 D1 D0

[P.4]

1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 GN D

SCART 1_MODE 1 IN PUT_DET R 119 R 120 R 121 R 122 0 0 0 0 CS0n DVI _SCDT SCART 1_MODE 2 SCART 2_MODE 1 SCART 2_MODE 2

[P.9] [P.9] [P.2] [P.9] [P.9] [P.9]


3 4 7 8 13 14 17 18 11 1 U24 D1 D2 D3 D4 D5 D6 D7 D8 CL K CL R GN D VCPU33 C 142 0.1 U K Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 2 5 6 9 12 15 16 19

VC C

VCPU33 C143 0.1 U K

[P.4]
D8 D9 D10 D11 D12 D13 D14 D15

20

[P.4] RESET

U23 D0 D1 D2 D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 11 R130 10 K + C144 10U 16V 1 D1 D2 D3 D4 D5 D6 D7 D8 CL K CL R

20

NM I

[P.4]

[P.4]

C S1n

VCPU33

GND

LCD12B First issue 01 / 05

10

74LVC273

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

2 5 6 9 12 15 16 19

R128

ADPW R_ON DVI_PDO MV_EN SII169_R ST Z GAFEOE SCART_FB_EN MU TE AUDIO_RESET

[P.3] [P.2] [P.3] [P.2] [P.3] [P.9] [P.7] [P.9]

VC C

MAIN BOARD

R123 R124 R125 R126 R127 R129

0 0 0 0 0 0

[P.6] LED1_SEL [P.6] LED2_SEL VIDEO_RESET [P.10,11] [P.10] DECOE [P.3] TWO_OPTIO [P.7] LCD_O N PC_AUDIO_SEL [P.2] [P.5] LVDS_EN

10

[P.4]
VCPU33

C S1n R 131 10 K

1 + C 145 10U 16V

VCC 10

74LVC273

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
(MAIN BOARD 7/11)

+12V

Main BOARD
R133 10 K J9 J8 20D0045105 TP63 5 TP65 4 TP67 3 TP70 2 TP73 1 G2 EARPHONE_MUT EAR_MUT E L19 220 OHM L21 220 OHM C 234 C 235 560P J 560P J AUDIO_R_EAR AUDI O _L_EAR R48 47 K R 132 10 K E TP64 TP68 TP71 L22 220 OHM TP74 L23 220 OHM C 147 O PEN TP66 1 2 3 4 5 6

[P.9] [P.9]

Q9 2N3904

[P.6] [P.9] [P.9]

MU TE A UDIO_L_OU T AUDIO_R_OUT

+12V Z22 0 G1 L24

TO KEYPAD BOARD

C146 O PEN

EMI Solution
+12V +5VS J12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TP77 +12V TP78 TP79 TP80 C 150 0.33U Z 1 U25 GN D VI VO 3 VC C

TO AUDIO BOARD

+9 V

+ 7809ABD2T

C 149 47U 16V

C 151 0.1U K

TP81 TP82 TP83

PW R_ON LCD_O N LCD_B R

[P.6] [P.6] [P.6]

+5VS

U27 GN D VIN VOUT

VPU3 3

L26 Z22 0

VCPU33

+ LD1117-3.3

C 156 0.1U K

C 155 47U 16V

C 157 0.1U K

TO POWER BOARD
3

U28 VIN GND VOUT

VPU2 5

L13 Z22 0

VCPU25

C 160 0.1U K

LM317M 1

R 136 681F

C 159 47U 16V

C 161 0.1U K

R137 681F MAIN BOARD

+ C162 10U 16V V33

VCC

U29 GN D VIN VOUT

+ LD1117-3.3

C 164 0.1U K

C 163 47U 16V

C 165 0.1U K

LCD12B First issue 01 / 05

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
(MAIN BOARD 8/11)

Main BOARD
+5V_FA N

J11

TP24 4 C48 0.1U K U36 +12V_FAN NC FR F NC ER E DR D 16 15 14 13 12 11 10 9 C52 0.1U K C51 0.1U K R162 15 VCC 2 VCC DXP1 ALERT DXN RESET DXP2 OUT1 FG1 CLK G768B VCC L27 +5V_FA N Z22 0 R 154 10 K +12V L28 Z22 0 +12V_FAN R161 10 K FANSPIN2 D28 TZMC5V1 MAIN BOARD +12V_FAN1 TP72 FANSPIN 1 TP69 J10 1 2 3 TP14 1 FANSPIN2 TP24 6 +12V_FAN2 TP24 5 1 2 3 TP24 7 J17 D29 TZMC5V1 +5V_FAN CLOCK_FAN 3 4 5 R159 2.2K Q7 2N3904 + R158 2.2K R160 2.2K C44 47U 25V C46 0 R166 4.7K +12V_FAN2 C4 5 2200P J 4.7K 2SB772S Q8 1 2 3 4 5 6 7 8 R 134 +5V_FA N O PEN TP76 Q1 0 2N3906 R 139 O PEN +12V_FAN

3 2 1

OPEN

TP24 3

[P.8]

CLOCK_FAN R167 R168 Y2 25.6KH Z 2M 10M

VDD AR A BR B CR C VSS CD 4049UBCM

R 151 Q6 2SB772S

4.7K

U35 R 152 4.7K

[P.4] [P.4]

SCL_5V S DA_5V +5V_FA N

R 147 R 148 R 146

0 0 10 K

14 12 11 6

SMBCLK SMBDATA

C49 10P J

C50 10PJ

+12V_FAN1 Q5 2N3904 + C3 47U 25V R 150 2.2K 1 10 R 153 2.2K R149 2.2K 9

16 OUT2 13 FG2 7 GND 8 GND

[P.8]

+5V_FA N

[P.8]

FANSPIN1

[P.8]

[P.8]

[P.8]

L25 Z22 0

LCD12B First issue 01 / 05

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
(MAIN BOARD 9/11)

Main BOARD

TP50 1

L501 R 502 1000 OHM VCC R501 75 DN501 BAV99 K 0 COMP_CYPY

[P.3,9]

+5VS

J501 TP50 2 5 6 TP50 3 3 4 TP50 4 1 2 R510 75 L502

4 V+

R 503 4.3 K R505 0V~4.85V 10 K 3.49V R 507 6.8 K R 508 10 K

R 504 10 K

U 501 1 7 8 14 SCART 1_MODE 1 SCART 1_MODE 2 SCART 2_MODE 1 SCART 2_MODE 2

R 506 1000 OHM VCC K

COMP_CBPB

[P.3,9]

[P.9]

SCART1_S WI TC H

3 2 1.40V R 509 3.9 K 5 6 10 9 12 13

IN1+ OUT 1 IN1IN2+ OUT 2 IN2IN3+ OUT 3 IN3IN4+ OUT 4 IN4GND

[P.6] [P.6] [P.6] [P.6]

DN502 BAV99

R 511 1000 OHM VCC K R514 75 DN503 BAV99

C OMP_CRPR

[P.3,9]

[P.9]

SCART2_S WI TC H

R 512 0V~4.85V

10 K

R 513 6.8 K J

Mode1 8.6-12V 1 0 0
+12V TP50 5 TP50 6 L504 L505 L506 Z22 0 +9 V Z22 0 VCC Z22 0

Mode2 1 1 0
scart 4:3 scart 16:9 Prev. status

3.5-8.6V
A

K DN504 BAV99

0-3.5V

J502 TP50 7 3 3 4 4 C501 1 1 2 2 O PEN 1 1 1K R516 22 K 2 ZD501 TZMC5V1 R515 A UD_CO MP_L

TP50 8

[P.9]

2210018551

ZD502 TZMC5V1 2

[P.4] [P.4] [P.9] [P.10] [P.6]

SCL_5V TT_SC L SCART2_S WI TC H SVVS IN PUT_DET

TP510 TP512 TP514 TP516 TP518 TP520

TP52 6

R533 A UD_COMP_R ZD503 TZMC5V1 1 1 R539 22 K

[P.9]

C502 O PEN

1K

MAIN BOARD

50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

ZD504 TZMC5V1 2

50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

TP50 TP51 TP51 TP51 TP51 TP51 TP52 TP52 TP52 TP52 TP52 TP52 TP52 TP52 TP53 TP53 TP53 TP53 TP53 TP53 TP53

9 1 3 5 7 9 1 2 3 4 5 7 8 9 0 1 2 3 4 5 6

A UDIO_RESET S DA_5V TT_SDA SCART1_S WI TC H SVHS SCART_FB_E N SCAR T_TT_BLN K SCART_TEXT_B SCART_TEXT_G SCAR T_TEXT_R OUT _S_C OUT_S_Y CVBS_VD AUD_PC_DVI_L AUD_PC_DVI_R AUD_COM P_ L A UD_COMP_R A UDIO_L_OU T AUDIO_R_OUT A UDI O _L_EAR AUDIO_R_EAR

[P.6] [P.4] [P.4] [P.9] [P.10] [P.6] [P.10] [P.10] [P.10] [P.10] [P.10] [P.10] [P.10] [P.2] [P.2] [P.9] [P.9] [P.7] [P.7] [P.7] [P.7]

20L2055050 J503

LCD12B First issue 01 / 05

11

L503

LMV324M

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
(MAIN BOARD 10/11)

VCC_A VCC_A PIN5 9 P C 504 10U Z C 505 0.1 U K IN69 C 506 1500P J C 507 390P K VCC_A PIN7 6 C 508 1500P J

Main BOARD
C503 0.1 U K V33D VCC 3 U 502 VIN GND VOUT 2 R 545 R 546 R 547 R 548 + C 510 47U 16V C511 0.1 U K C512 0.1 U K C 513 0.1 U K C514 0.1 U K C515 0.1 U K C 516 PIN1 0 PIN2 9 PIN3 6 PIN4 5 3.3 P C Y501 20.25M HZ C 519 UV 0 UV 1 UV 2 UV 3 10U 16V 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 UV 4 UV 5 UV 6 UV 7 C 517 3.3 P C V33D V33D 5 6 7 8 5 6 7 8 V33D RN502 47 RN501 47 4 3 2 1 4 3 2 1 DUV DUV DUV DUV DUV DUV DUV DUV 0 1 2 3 4 5 6 7 47 47 47 O PEN

C 509 0.1 U K

LD1117-3. 3

SVVS SVH S SVPEN VFI EL D DUV[0..7]

[P.11] [P.11] [P.11] [P.4] [P.11]

0.047U K

C518

ASGF XTAL2 XTAL1 N. C CLK5 VSTBY FPDAT/VSYA VS MSY/HS FSY/HC/HSYA AVO INTLC VSUPSY GNDSY Y C0 C1 C2 C3 GNDC VSUPC C4 C5 C6 C7

R549 75

[P.9]

OUT _S_C R 551 75

R550 C 522 R552 R554 C 526 R555 75 R 558 75 330P J

75 330P J 75 C 524 C 525

C520 330P J C 521

VCC_A 0.68U K 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GNDF VRT I2CSEL ISGND VSUPF VOUT CIN VIN1 VIN2 VIN3 VIN4 VSUPAI GNDAI VREF FB1IN AISGND

TP537

[P.9] [P.9]

OUT_S_Y

C 523 0.68U K 0.68U K

0.68U K

U5 03 VPC3230D
I2C : 0X8E
B1/CB1IN G1/Y1IN R1/CR1IN B2/CB2IN G2/Y2IN R2/CR2IN ASGF N.C/FFRSTWIN VSUPCAP VSUPD GNDD GNDCAP SCL SDA RESQ TEST VGAV YCOEQ FFIE FFWE FFRSTW FFRE FFOE CLK20

C VBS_VD

C527 10U 16V + C 528 O PEN TP538 C 532 O PEN C 533 C 534 150P J C 535 C 536 150P J C 537 C 538 150P J C 542 C 547 330P J 0.22U K 0.22U K 0.22U K 0.22U K 0.047U K

Y0 Y1 Y2 Y3 VSUPY GNDY Y4 Y5 Y6 Y7 GNDLLC VSUPLLC LLC1 LLC2 VSUPPA GNDPA A

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

RN503 47 5 4 6 3 7 2 8 1 RN504 47 5 4 6 3 7 2 8 1 R 556 R 557

DY DY DY DY DY DY DY DY

0 1 2 3 4 5 6 7

DY[0..7]

[P.11]

0 O PEN VC C C 529 1500P J C530 0.1 U K R569 1K

SVCLK

[P.11]

[P.9] [P.9] [P.9]

SCART_TEXT_B SCART_TEXT_G SCART _TEXT_R

L508 L509 L510

3.3N H 3.3N H 3.3N H

R560 R561 R562

75 75 75

VPC323XD VINB1 VING1 VI NR1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

[P.9]

SCAR T_TT _BLN K

L507

3.3N H

R559

75

C 531 22P J

R563 O PEN

VCC L511 Z22 0 + C 540 47U 16V C 544 0.1 U K

VCC_A

[P.9]

COMP_CBPB

R565

75

DECOE Y/C Output L Disable H Enable


R 564 100 VIDEO_RESET

Q501 2N3904

1K R 571 10 K

R 570

DECOE

[P.6]

[P.6]

C 545 22U 16V

[P.9]

COMP_CYPY

R 568

75

C 548 C 549 330P J

0.22U K

C539 0.22U K C543 1500P J C546 390P K

C 541 100PK R566 R567 100 100

SD A

[P.4]
MAIN BOARD

[P.9]

C OMP_CRPR

R572

75

C 550 C 551 330P J

0.22U K

LCD12B First issue 01 / 05

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
(MAIN BOARD 11/11)

Main BOARD
1 2 3 4 6 7 8 9 DY[0..7]

U504A VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 VG 0 VG 1 VG 2 VG 3 VG 4 VG 5 VG 6 VG 7 VR 0 VR 1 VR 2 VR 3 VR 4 VR 5 VR 6 VR 7 SVH S SVVS SVCLK PVCLK CREF PVVS PVH S DGB DGB DGB DGB DGB DGB DGB DGB 0 1 2 3 4 5 6 7 DB 0 DB 1 DB 2 DB 3 DB 4 DB 5 DB 6 DB 7 DG0 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DCLK DV S DH S DE N DEN G DEN B DEN R AD R AD G AD B VREFIN VREFOUT RSET COMP MV E CGMS TESTCLK 110 111 113 114 116 117 118 119 121 122 124 125 127 128 129 130 132 133 135 136 138 139 141 142 102 103 104 145 106 107 108 156 153 150 161 162 159 160 201 146 144 VDBU0 VDBU1 VDBU2 VDBU3 VDBU4 VDBU5 VDBU6 VDBU7 VDG VDG VDG VDG VDG VDG VDG VDG Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 4 3 RN505 2 47 1 4 RN506 3 2 47 1 4 3 RN507 2 47 1 4 3 RN508 2 47 1 4 3 RN509 2 47 1 4 RN511 3 2 47 1 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 L512 VGU0 VGU1 VGU2 VGU3 VGU4 VGU5 VGU6 VGU7 V R Y0 V R Y1 V R Y2 V R Y3 V R Y4 V R Y5 V R Y6 V R Y7 VBV0 VBV1 VBV2 VBV3 VBV4 VBV5 VBV6 VBV7 70 OHM

VGU[0. .7]

[P.4]
19 49 77 112 134 187 219 251 10 24 39 46 57 65 74 85 96 105 115 126 137 147 171 189 193 202 212 222 228 233 240 246 253 196 198 59 61 148 164 167

U504B Vss Vss Vss Vss Vss Vss Vss Vss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss PVss DPAVss DPDVss MPDVss MPAVss ADDVss ADAVss ADGVss AVS33B AVS33G AVS33R VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd PVdd DPAVdd DPDVdd MPDVdd MPAVdd ADDVdd ADAVdd ADGVdd AVD33B AVD33G AVD33R 5 34 93 123 140 175 205 235 14 29 42 54 64 69 80 90 101 109 120 131 143 165 180 200 208 216 224 230 237 243 249 256 197 199 58 60 149 163 166 151 154 157

P2P5V RAMA 0 RAMA 1 RAMA 2 RAMA 3 RAMA 4 RAMA 5 RAMA 6 RAMA 7 RAMA 8 RAMA 9 RAMA10 RAMA11 RAMA12 RAMA13 213 210 207 204 203 206 209 211 214 217 215 220 221 218

U 504C MA 0 MA 1 MA 2 MA 3 MA 4 MA 5 MA 6 MA 7 MA 8 MA 9 MA10 MA11 MA12 MA13 MD 0 MD 1 MD 2 MD 3 MD 4 MD 5 MD 6 MD 7 MD 8 MD 9 MD1 0 MD1 1 MD1 2 MD1 3 MD1 4 MD1 5 mRASn mCASn mWE n 255 252 248 245 242 239 236 232 231 234 238 241 244 247 250 254 225 226 227 RAMD 0 RAMD 1 RAMD 2 RAMD 3 RAMD 4 RAMD 5 RAMD 6 RAMD 7 RAMD 8 RAMD 9 RA MD10 RA MD11 RA MD12 RA MD13 RA MD14 RA MD15 RN510 R 573 RCLK R 574 0 0 223 229 MCLKFB MCL K 4 3 2 1 47 P3P3V R576 R577 R578 R580 R582 R584 R585 U 504D 10 K 10 K 10 K 10 K 10 K 0 0 0 0 O PEN O PEN 48 50 51 52 53 43 44 45 47 40 41 56 TD O TC K TD I TM S TRSTN I2CA1 I2CA2 SC L SD A XTALI XTALO TEST MCUA MCUA MCUA MCUA MCUA MCUA MCUA MCUA 0 1 2 3 4 5 6 7 168 169 170 172 173 174 176 177 178 179 181 182 183 184 185 186 190 191 192 188 V33D L513 1 Z22 0 P3P3V 5 RRASn 6 RCASn 7 RW En 8 P3P3V

P3P3V

U 505 VDDQ VDDQ VDDQ VDDQ VDD VDD VDD RAMA11 RAMA10 RAMA 9 RAMA 8 RAMA 7 RAMA 6 RAMA 5 RAMA 4 RAMA 3 RAMA 2 RAMA 1 RAMA 0 RAMA12 RAMA13 R 575 1K R CLK P3P3V RRASn RCASn RW En 35 22 34 33 32 31 30 29 26 25 24 23 20 21 19 38 37 18 17 16 39 15 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 CS CL K CK E RA S CA S WE VSSQ VSSQ VSSQ VSSQ VSS VSS VSS UDQM LDQM DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 NC/RFU NC 53 51 50 48 47 45 44 42 13 11 10 8 7 5 4 2 40 36 RA MD15 RA MD14 RA MD13 RA MD12 RA MD11 RA MD10 RAMD 9 RAMD 8 RAMD 7 RAMD 6 RAMD 5 RAMD 4 RAMD 3 RAMD 2 RAMD 1 RAMD 0

[P.10]

DY 0 DY 1 DY 2 DY 3 DY 4 DY 5 DY 6 DY 7 DUV0 DUV1 DUV2 DUV3 DUV4 DUV5 DUV6 DUV7

15 16 17 18 20 21 22 23 30 31 32 33 35 36 37 38 11 12 13 25 26 27 28 70 71 72 73 75 76 78 79 81 82 83 84 86 87 88 89 91 92 94 95 97 98 99 100 66 67 68

VRY[0..7]

[P.4]

P3P3V

DUV[0..7]

[P.10]

VDRV0 VDRV1 VDRV2 VDRV3 VDRV4 VDRV5 VDRV6 VDRV7 Y C LK YV S YH S YE N Y PEN

VBV[0..7]

[P.4]

PW 1230

[P.10] SVH S [P.10] SVVS [P.10] SVCLK [P.10] SVCLK [P.10] SVPEN [P.10] SVVS [P.10] SVH S

R579 R581 R583 TP53 9 TP54 0 R586 TP54 1 TP54 2 TP54 3 C 552 0.01U K 270 0.01U K 1 10U 0 16V 0 TP54 4

47 47 47 47

VCLK VVS VH S DECOE VPEN

[P.4] [P.4] [P.4] [P.6] [P.4]

6 12 46 52 28 41 54

49 43 9 3 27 14 1

HY57V641620HGT-6

A VDD2 A VDD1 AVD2 5

[P.4] [P.4] [P.4] [P.4]

SCL SDA DI_SCL DI_SDA

R587 R588 R596 R597

4M*16 SDRAM
P3P3V

MCUD0 MCUD1 MCUD2 MCUD3 MCUD4 MCUD5 MCUD6 MCUD7

C 557 0.1U K

C 558 0.1U K

C 559 0.1U K

C 560 0.1U K

C 561 0.1U K

C 562 0.1U K

C563 0.1 U K

R 589 C 553 C554 2 R 591 R 592

AVD3 3

Y502

10M HZ

AVD3 3 P3P3V

55

DGG0 DGG1 DGG2 DGG3 DGG4 DGG5 DGG6 DGG7 DGR DGR DGR DGR DGR DGR DGR DGR 0 1 2 3 4 5 6 7

152 155 158

R590 C555 18P J

2M C 556 18P J

RESETn MCUCS MCUWR MCUCMD MCURDY PW 1230

GN D

DGH S DGV S DGCLK PW 1230

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

8 O PEN 7 6 RN512 5 8 O PEN 7 6 RN513 5 8 O PEN 7 6 RN514 5 8 O PEN 7 6 RN515 5 8 O PEN 7 6 RN516 5 8 O PEN 7 6 RN517 5

VIDEO_RESET

P2P5V L514 AVD2 5 Z22 0 VGU[0. .7] C 564 + 22U 16V P3P3V L515 AVD3 3 Z22 0 VRY[0..7] C 569 0.1U K C 570 0.01U K C566 0.1U K C 567 0.01U K

P2P5V L516 A VDD2 Z22 0 C574 0.1U K L517 A VDD1 Z22 0 C577 0.1U K C 578 0.01U K C 575 0.01U K

VC C 3

VDG VDG VDG VDG VDG VDG VDG VDG P2P5V

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

VGU0 VGU1 VGU2 VGU3 VGU4 VGU5 VGU6 VGU7 V R Y0 V R Y1 V R Y2 V R Y3 V R Y4 V R Y5 V R Y6 V R Y7

R 595 681F

+ 2

C 579 0.1U K

C 580 0.1U K

C 581 0.1U K

C 582 0.1U K

C583 0.1U K

C 584 0.1U K

C585 0.1U K

C586 0.1U K

VDRV0 VDRV1 VDRV2 VDRV3 VDRV4 VDRV5 VDRV6 VDRV7

C 576 10U 16V

MAIN BOARD

P3P3V

C 587 0.1U K

C 588 0.1U K

C 589 0.1U K

C 590 0.1U K

C591 0.1U K

C 592 0.1U K

C593 0.1U K

C594 0.1U K

C 595 0.1U K

C596 0.1U K

C597 0.1U K

C 598 0.1U K

C 599 0.1U K

C600 0.1U K

C601 0.1U K

C602 0.1U K

C 603 0.1U K

C 604 0.1U K

C 605 0.1U K

C 606 0.1U K

C 607 0.1U K

C 608 0.1U K

C 609 0.1U K

C 610 0.1U K

LCD12B First issue 01 / 05

C 572 0.1U K

LM317M

R 594 681F

1 + C571 47U 16V

PW 1230

I2C : 0X64

Option: PW1230 output RGB format


VDBU0 VDBU1 VDBU2 VDBU3 VDBU4 VDBU5 VDBU6 VDBU7 VBV0 VBV1 VBV2 VBV3 VBV4 VBV5 VBV6 VBV7 VBV[0..7]

[P.6]

R 593

DI_RESET

C 565 10U 16V

C 568 0.1U K

U 506 P2P5V VIN VOUT 2

C573 0.1U K

POWER SUPPLY INTERFACE - INTERFACE ALIMENTATION - NETZTEIL - ALIMENTAZIONE - INTERFAZ ALIMENTACIN


SCHEMATIC DIAGRAM - SCHEMA DE PRINCIPE - SCHALTBILD - SCHEMA - ESQUEMA

PFC BOARD

R6201A 332K

C6201 1uF

R6206 22K

L6203 D6202 MUR460

R6202A 590K

R6201B 332K 450uH D6201 TR6201 SCK15056 t B+ VCC1 C6203 47uF SF10A60U R6207 22 ZCD GD CS INV L6561 C6205 C6206 1uF C6207 470p R6209 R6211 ZD6201 27V 46.4K 5 7 4 1 D6203 R6208 20K R6212C R6212 0.15R/5W R6212D 590K R6212H 590K 590K R6212G 590K PGND Q6201 20N60C3 R6212B 590K R6212F 590K R6212A 590K R6212E 590K C6202 1uF C6211 100uF/450V C6212 100uF/450V

ACEMI Board

ACCY6201

L6201 115uH BD6201 GBJ8J 1

R6202B 590K

R6201C 332K

R6202C 590K 4 2

R6201D 332K 8 3 2 6 VCC MULT COMP GND

IC651

AC+

115uH

AC+

CY6202

L6202

C6204 R6203 0.01uF 11K

1N4148

R6213 9.09K

PFC BOARD

C6208 0.01uF

C6209 R6204 0.1uF 475K

R6205 200K

C6210 0.1uF

Q6202 2N7002

EMI BOARD
F6101 CN6101 3P 1 2 3
Mainsvoltage 50HZ / 60HZ

L6101 R6101A 270K R6101B 270K CY6102 1000p R6101C 270K

VZ6101 471 L6103 1.1mH L6102

CX6101 0.47uF L6104 24mH

CX6102 0.68uF

L6105 1.1mH

AC-

AC-

EMI BOARD

3Ts

LCD12B First issue 01 / 05

PFC Board

T4A/250V

3Ts

CY6101 1000p

AC+

AC+

POWER SUPPLY INTERFACE - INTERFACE ALIMENTATION - NETZTEIL - ALIMENTAZIONE - INTERFAZ ALIMENTACIN


SCHEMATIC DIAGRAM - SCHEMA DE PRINCIPE - SCHALTBILD - SCHEMA - ESQUEMA

INVERTER POWER BOARD

R7302 47 R7301 47 D7301

C7301 C7302 1000p 1000p

V-INVERTER FMX-22SL

V-INVERTER

B+ To PFC Board Audio Power Board

1 C6301 0.01uF/500V R6301 68K/2W Q6302 MPSA44 R6308 392K R6309 100K C6312 4.7uF Q6303 PMBS3904 R6307 392K D6303 1N4148 C6311 150uF R6305 392K D6301 ES1D 3 4 C6310 47uF ZD6301 24V Q6301 STW11NB80 R6311 20K R6327 1K R6312 0.27R/2W 5 C6303 C6302 3300p R6303 392K R6304 392K D6302 ES1D R6302 68K 2

T6301 PQ3220

7 D7302 C7303A FMX-22SL 470uF C7303B 470uF C7303C 470uF C7303D 470uF C7304 0.1uF

D7303 FMX-22SL R7313

VC
R6306 392K C6315 0.1uF D6304 1N4148

15mohm R7303 22.1K R7304 1K VF R7307 75

VCC

C7307 C7308 0.1uF

R6310 7 VCC 8 R6316 1.1K R6317 Q6304 D6308 1N4148 C6308 2200p D6310 C6313 4.7uF C6307 0.1uF 1 C6306 1500p 4 U6302 PC123F1 R7312 330 R6315 11K R6314 100K D6307 1N4148 4 RT/CT COM 1 R6313 10K V REF U6301 UC3843A B 2 GND 5 C6305 100p OUT I SEN 3 10 6

C7305 1.2K C7309 0.1uF CY6301 1500p 8 7

C7306 1000p

R7306 5.1K

5 CRIN U7301 TSM101A

VRIN

CRREF OUT

VCC

CSEN

VREF

C6304 1000p

GND

CN701
LCD-ON LCD-BRI EGND 12 11 10 9 8 7 6 5 4 3 2 1

R7308 10K

CN702
10 9 8 7 6 5 4 3 2 1

R6325

R7309 1.2K

V-INVERTER
ZD7301 30V

C7310 0.1uF

V-INVERTER R7310 100

P-ON Audio Power Board VCC1


Q6305 PMBS3906 R6323 47K

D6309 1N4148

R6318 5.1K

VCC

Q6307 PMBS3904

VF 2

G
R7311 10 C7311 0.1uF U7302 PQ1CY1032Z 1 VI ON/OFF GND 5 3 4 VO FB 2 D7304A RB060L L7301 150uH D7304B RB060L R7321 3.3K R7322 1.1K C7305 470uF

VC
R6319 1.2K 2

R6322 47K R6320 7.5K 3 R6321 1.5K D6311 1N4148

R6326 1.1K Q7301 PMBS3904

7-Sep-2004

5VS

C6314 100uF

U6303 LM431

R7320 5.1K C7320 0.1uF

EGND

P-ON

LCD12B First issue 01 / 05

POWER SUPPLY INTERFACE - INTERFACE ALIMENTATION - NETZTEIL - ALIMENTAZIONE - INTERFAZ ALIMENTACIN


SCHEMATIC DIAGRAM - SCHEMA DE PRINCIPE - SCHALTBILD - SCHEMA - ESQUEMA

AUDIO POWER BOARD


R7401 47 R7401A T6401 ER28 47 D7401 10 C7401 C7402 1000p 1000p

CN704=>J12
L7401 2.7uH

12V

12V 5VS 5V

B+

5 C6401 0.01uF/500V C6402 3300p R401 68K 4 C6412 100uF D6402 UF4007 C6404 0.1uF 3 R6403 10K Q6402 PMBS3906 C6413 4.7uF 1

Q6404 PMBS3904

10CTQ150S

C7407 470uF

C7408 470uF

C7409 820uF

R7404 4.7K

VCC
R6404 2.2K

9 POWE R-ON D7402 8 10CTQ150S C7403 C7404 1000p 1000p C7410 470uF C7411 1000uF R7405 4.7K L7402 2.7uH

+16V

LCD-ON LCD-BRI

R7402 D6407 R6402 1N4148 1K Q6403 PMBS3904 R6414 10K R6413 10K C6414 4.7uF 7 6 VCC V REF U6401 UC3843A RT/CT COMP 1 R6412 10K C6415 4.7uF C6410 2200p C6409 0.022uF R7410 U6404 PC123F1 4 1 330 FB 2 GND 5 C6407 1000p C6408 220p OUT I SEN 7 47 R7402A 47 ZD6401 6.2V D6404 1N4148 Q6401 2SK3264-01 C6403 68p

R6406 4.7 R6407 22 3

L7403 3.5mm D7403 C7412 470uF L7403 2.7uH CY6401 1500p 10CTQ150S R7403 47 R7403A 47 C7405 C7406 1000p 1000p U7401 PQ1CY1032Z 1 VI ON/OFF 5 GND 3 4 VO FB 2 D7404 RB060L L7404 45uH D7405 RB060L C7413 1000uF R7406 4.7K

5 4 3 2 1

-16V

2 R6408 1K R6417 22K R6409 0.47R/2W

8 R6410 100K R6411 D6406 1N4148 11K 4 C6411 0.1uF D6405 1N4148

Power Board

CN703=>J2

12V

5V
R7407 3.4K C7414 470uF R7408 1.1K

12V

P-ON

12V
ZD7302 18V

+16V
ZD7303 24V

R7409 5.1K

C7416 0.1uF

R6415 3 2 5.1K R7413 10K 1 U7402 LM431 C7415 0.1uF R7411 11K

U6403 PC123F1

R7314 1K

5VS
D7305 1N4148 D7306 1N4148

EGND

POWER-ON
R7317 10K C7312 0.1uF Q7302 PMBS3904 R7318 10K 3 2

R6416 1K 2

R7412 2.87K

R7316 10K Q7303 PMBS3904

R7315 10K

C7313 10uF

-Sep-2004

LCD12B First issue 01 / 05

Main Board

To PFC Board

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

SCART INTERFACE / TUNER SCHEMATIC DIAGRAM - SCHEMA DE LINTERFACE PERITELEVISION / TUNER - SCHALTBILD EUROPA NORMBUCHSE / TUNER SCHEMA DELLA PRESA PERITEL / SINTONIZZATORE - ESQUEMA INTERFAZ EUROTOMA / SINTONIZADOR
( AV TUNER BOARD 1/2 )

TUNER BOARD Power in


+5V

VSYNC 1 +5V HSYNC 1 C72 10uF + FM ANT IN D AGC

U7 1 2 3 AS C27 0.1uF C75 100uF FB1 inductor 10uH +5V

C4

C3 6 5 4 3 2 1 44 43 42 41 40 0.1uF U1

R2 R3 A C5 22P C6 22P

22 22

10uF D 7 8 9 10 11 12 13 14 15 16 17

SCL1 1,2 SDA1 1,2

NC NC VDD3 DA0/P5.0 DA1/P5.1 DA2/P5.2 VSYNC HSYNC P5.3 P5.4 P5.5

4 SCL 39 38 37 36 35 34 33 32 31 30 29 5 SDA 6 +5V-T 7 +5V-T 9 SCL +33V 12 MTV312M FM-SW 13 AUDIO O/P 14 SIF/AS 15 GND 16

R1 10K 1,2 SDA1 1,2 SCL1

Y1 D C8 20pF D

P1.1 P3.2/INT0 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P6.1/AD1 P6.0/AD0 SDA

RST VDD P6.3/AD3 VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P6.2 P1.0

DA8 DA9 P4.1 P4.0 DA7 DA6/P5.6 P6.7 P6.6 P6.5 P6.4 SCL

+5V A C80 0.1uF A C48 1N4148 R5 10K 22nF BZV55B33V A A C9 R11 C10 SIF 2 100K 0.1uF A A A +5V C21 R4 NC 18 NC A R8 TV_COMP_OUT Q1 1 +5V NC R59 A A 470 R15 0 R58 100 2N3906 +5V A R60 NC Q4 TV_VIDEO 1 A C59 6.8nF A 47uF R20 510 TV_AUDIO 2 D3 C56 180pF C64 4.7nF 10K A Q3 BC847 A R6 1uF D1 C55 22nF L1 1mH R7 150 C65 R9 22

C7

12MHz

20pF D

18 19 20 21 22 23 24 25 26 27 28 IRIN

+5V R16 R17 R18 R19 R37 4.7K 4.7K 4.7K 4.7K 4.7K SCL SDA SCL1 SDA1 RST 2

VIDEO RST 2 SDA 1,2 1,2 VDD D2 SM4001 U2 LM78L05 +5V +5V FB2 2 2 R22 4R7 ,1W,2512 1 IN GND OUT 3 inductor 10uH + C15 0.1uF C11 100uF C13 0.1uF 2 C1 100uF C2 0.1uF VSYNC 1 FM-IF +5V-IF 17

FE6234

NC

+9V 1

L2 1

POWER COIL 100UH + C12 470uF L3 BEAD 70ohm 2012

A +9V J1 1 3 5 7 9 11 13 2 4 6 8 10 12 14 CON14AP TV_COMP_OUT 1 AUDIO_R 2 AUDIO_L 2 IRIN SCL SDA R26 0 1 2 3 A0 A1 A2 AT24C08 D D VSS 4 D U4 1,2 SCL1 1,2 SDA1 6 5 SCL SDA WP 7 VCC 8 C16 C20 100pF 0.1uF A A 130K 1 VSYNC R10 10K +5V A 4 R24 1 HSYNC +5V 1 2 3 U3 R23 470K

C14 0.1uF

C57 47uF A

H_OSC HD SYNCOUT VD BA7046

P_COMP VCC VIN GND

8 7 6 5 R44 470K C58 C19 1nF 1uF A A A + C17 1uF + R43 470 TV_VIDEO R25 10K C18 2200P

SC-OUT-R SC-OUT-L

R52 R53

NC NC R51 0 R50 0

TUNER BOARD

LCD12B First issue 01 / 05

SCART INTERFACE / TUNER SCHEMATIC DIAGRAM - SCHEMA DE LINTERFACE PERITELEVISION / TUNER - SCHALTBILD EUROPA NORMBUCHSE / TUNER SCHEMA DELLA PRESA PERITEL / SINTONIZZATORE - ESQUEMA INTERFAZ EUROTOMA / SINTONIZADOR
( AV TUNER BOARD 1/7 )

TV TUNER BOARD--(PAL) Sound Processor

Y2 DI P C2 3 3.3pF VCCSI F A MSPX2 18.432MHz MSPX1 A C2 4 3.3pF

R4 2 12K

R3 8 470 BPF 7 3 Q2 C28 BC848B SOT 23 56pF ANAINA C26 56pF ANAIN1

C5 0 SIF 1nF BPF 1

R3 9 330

C5 1 BPF2 910pF L8 1uH 1008 A C5 2 3.9nF BPF3

C5 3 BPF4 860pF L9 1uH 1008 A

C5 4 BPF5 10n F R4 0 3.9K BPF6 R4 1 100 U6

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

NC STANDBYQ ADR-SEL D-CTR-I/O0 D-CTR-I/O1 NC NC AUD-CL-OUT TP XTAL_OUT XTAL_IN TESTEN ANA-IN2+ ANA-INANA-IN1+ AVSUP

1,2 1,2

SCL 1 SDA1

VCCAUDIOD + C3 5 10uF D RST D RESET # D D C3 6 1.5nF C3 7 470pF C3 8 220pF D

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

I2C-CL I2C-DA I2S-CL I2S-WS I2S-DA-OUT I2S-DA-IN1 ADR-DA ADR-WS ADR-CL DVSUP DVSS I2S-DA-IN2 NC NC NC RESETQQ

DACA-R DACA-LL VREF2 DACM-R DACM-LL NC DACM-SUB NC SC2-OUT-R SC2-OUT-L VREF1 SC1-OUT-R SC1-OUT-L CAPL-A AHVSUP CAPL-M

+8VOP U9 C2 2 + 10uF AUD_ R DACMR

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

AUDIO_ R

1 2 3 4 A

OUTA INAINA+ GN D LM358

VC C OUTB INBINB+

8 7 6 5 C25 + 10uF R5 6

R5 7 100K A AUD_ R

AUDIO_ L A AUD_L DACML

AUD_L

100K

B6 BEAD 70ohm B7 VDD C6 1 + 10uF A C6 0 0.1uF BEAD 70ohm C6 2 + 10uF C6 3 0.1uF A VCCAUDIOAH +8VOP

L5 +5V 2.7uH L7 2.7uH L10 BEAD 70ohm VCCAUDIOA VCCAUDIOD VCCSI F

LCD12B First issue 01 / 05

D VCCAUDIOA C2 9 470pF A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 C30 1.5nF A + C3 1 10uF A TV_AUDI O MSP3415G PLQFP64 AVSS MONO-IN VREFTOP SC1-IN-R SC1-IN-L ASG SC2-IN-R SC2-IN-L ASG SC3-IN-R SC3-IN-L ASG SC4-IN-R SC4-IN-L AGNDC C AHVSS MONOI N VREFTO P C32 330n F + C34 0.1uF A A C33 10uF AGNDC + A C4 0 0.1uF A C4 1 CAPLM A C4 9 1nF CAPL A + C45 10uF A A A + 10uF C4 2 470pF C4 3 1.5nF + C4 4 10uF VCCAUDIOA H A C3 9 3.3uF C4 7 1nF A R5 5 N C C7 0 NC SC-OUT-R R5 4 N C C6 9 NC SC-OUT-L

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