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Proiectare VLSI

Evolutie, clasificari, tehnologii,

terminologie, principii

Istoria integrarii

SSI:

’60,

10 porti*/chip (10)

MSI:

’70,

100 -1000 porti/chip (10 2 )

LSI:

’80,

1000 10000 porti/chip (10 4 )

VLSI:

’90,

10k 100k porti/chip (10 5 )

ULSI:

1M 10M porti/chip (10 7 )

WSI, SoC, 3D-IC (>10 7 )

Poarta echivalenta = o structura NAND (NOR in

cazul IBM), realizata cu 4 tranzistoare.

Evolutia Tehnologiilor VLSI

Evolutia Tehnologiilor VLSI

Familii logice VLSI

Familii logice VLSI

Maturitatea tehnologiilor VLSI

Maturitatea tehnologiilor VLSI

Interfatarea familiilor VLSI

Interfatarea familiilor VLSI

Performante VLSI

Performante VLSI

Gama tensiunilor de alimentare

Gama tensiunilor de alimentare

Efectul tensiunii de alimentare

asupra vitezei de comutatie

Efectul tensiunii de alimentare asupra vitezei de comutatie

Tehnologii Low-Voltage

Tehnologii Low-Voltage

Structura integrata VLSI

Upper

interconnect

layers on an

microprocessor

die

Structura integrata VLSI • Upper interconnect layers on an Intel 80486 DX2 microprocessor die

Obiectivele proiectarii VLSI

Viteza / performanta

Consum de putere cat mai

mic

Arie ocupata redusa

Incapsulare adecvata

Structura generica a circuitelor VLSI

1.Transistoare

Structura generica a circuitelor VLSI 1.Transistoare nMOS pMOS CMOS logic gates + 2. Conexiuni = design
Structura generica a circuitelor VLSI 1.Transistoare nMOS pMOS CMOS logic gates + 2. Conexiuni = design
Structura generica a circuitelor VLSI 1.Transistoare nMOS pMOS CMOS logic gates + 2. Conexiuni = design

nMOS

pMOS

generica a circuitelor VLSI 1.Transistoare nMOS pMOS CMOS logic gates + 2. Conexiuni = design Circuits

CMOS logic gates

+

2. Conexiuni

= design
=
design
Circuits

Circuits

[10] http://scale.engin.brown.edu/classes/EN1600S08/

Structura interna a unui circuit integrat

Structura interna a unui circuit integrat inventatorii circuitului integrat (1958) Fiz. Robert Noyce wires transistors

inventatorii

circuitului

integrat

(1958)

circuit integrat inventatorii circuitului integrat (1958) Fiz. Robert Noyce wires transistors Jack Kilby, premiul

Fiz. Robert Noyce

inventatorii circuitului integrat (1958) Fiz. Robert Noyce wires transistors Jack Kilby, premiul Nobel 2000 [10]
inventatorii circuitului integrat (1958) Fiz. Robert Noyce wires transistors Jack Kilby, premiul Nobel 2000 [10]

wires

transistors

integrat (1958) Fiz. Robert Noyce wires transistors Jack Kilby, premiul Nobel 2000 [10]

Jack Kilby, premiul Nobel 2000

[10] http://scale.engin.brown.edu/classes/EN1600S08/

Structura integrata VLSI

Quad core from Intel: ~600 million transistors in 286 mm 2
Quad core from
Intel: ~600 million
transistors in 286
mm 2

Legea lui Moore: Numarul de tranzistioare dintr-un circuit integtrat se dubleaza la fiecare 2ani !

[10] http://scale.engin.brown.edu/classes/EN1600S08/

Ordin de marime

Human Hair ~75 m . 0.18 m 180 nm feature .
Human Hair
~75 m
.
0.18 m
180 nm
feature
.

~40,000 (65-nm node) tranzistoare incap intr-o sectiune transversala

[C. Keast]

[10] http://scale.engin.brown.edu/classes/EN1600S08/

Tehnologii VLSI

Tehnologii VLSI

Comparatie arhitecturi

Comparatie arhitecturi

Etapele principale de realizare a unui CI

1. idea (need)

Etapele principale de realizare a unui CI 1. idea (need) 2. write specifications 3. design system

2. write specifications

realizare a unui CI 1. idea (need) 2. write specifications 3. design system 5. Fabrication if
realizare a unui CI 1. idea (need) 2. write specifications 3. design system 5. Fabrication if

3. design

system

CI 1. idea (need) 2. write specifications 3. design system 5. Fabrication if satisfactory 4. analyze/
5. Fabrication if satisfactory
5. Fabrication
if satisfactory

4. analyze/ model system

5. Fabrication if satisfactory 4. analyze/ model system 6. test / work as modeled? [10]

6. test / work as modeled?

if satisfactory 4. analyze/ model system 6. test / work as modeled? [10] http://scale.engin.brown.edu/classes/EN1600S08/

[10] http://scale.engin.brown.edu/classes/EN1600S08/

Sinteza si analiza

VHDL / Verilog / SystemC

Sinteza si analiza VHDL / Verilog / SystemC compilare/ synteza schema fizica definire masca realizare conexiuni

compilare/

synteza

si analiza VHDL / Verilog / SystemC compilare/ synteza schema fizica definire masca realizare conexiuni amplasare
si analiza VHDL / Verilog / SystemC compilare/ synteza schema fizica definire masca realizare conexiuni amplasare

schema fizica

VHDL / Verilog / SystemC compilare/ synteza schema fizica definire masca realizare conexiuni amplasare layout [10]

definire masca

realizare conexiuni

amplasare layout

schema fizica definire masca realizare conexiuni amplasare layout [10] http://scale.engin.brown.edu/classes/EN1600S08/
schema fizica definire masca realizare conexiuni amplasare layout [10] http://scale.engin.brown.edu/classes/EN1600S08/

[10] http://scale.engin.brown.edu/classes/EN1600S08/

Realizare circuit

Realizare circuit tapeout mask layout patterns mask writer m a s k s Dice (taiere) wafer

tapeout

Realizare circuit tapeout mask layout patterns mask writer m a s k s Dice (taiere) wafer

mask layout patterns

Realizare circuit tapeout mask layout patterns mask writer m a s k s Dice (taiere) wafer

mask writer

Realizare circuit tapeout mask layout patterns mask writer m a s k s Dice (taiere) wafer
Realizare circuit tapeout mask layout patterns mask writer m a s k s Dice (taiere) wafer

masks

tapeout mask layout patterns mask writer m a s k s Dice (taiere) wafer printing test
Dice (taiere) wafer
Dice (taiere)
wafer

printing

test and packaging

a s k s Dice (taiere) wafer printing test and packaging chip die [10] http://scale.engin.brown.edu/classes/EN1600S08/

chip

a s k s Dice (taiere) wafer printing test and packaging chip die [10] http://scale.engin.brown.edu/classes/EN1600S08/

die

[10] http://scale.engin.brown.edu/classes/EN1600S08/

Structuri integrate VLSI

Structuri integrate VLSI

Structura de

principiu a unui

circuit generic

PLD

PLD

• Structura de principiu a unui circuit generic PLD PLD

Caracteristici PLD

 

AND

OR

PROM

Fix

Programabil

PLA

Programabil

Programabil

PAL

Programabil

Fix

PLD Programmable Logic Devices

Principiul PLA/PAL

Principiul PLA/PAL

Minterms

Implementarea unui sumator complet cu PLA

A Programmable Logic Array performs any function

in sum-of-products form.

Literals: inputs & complements

Products / Minterms: AND of literals

Outputs: OR of Minterms

Example: Full Adder

s

c out

: OR of Minterms • Example: Full Adder s  c out abc  ab abc

abc

ab

abc

abc

bc

ac

abc

AND Plane OR Plane bc ac ab abc abc abc abc a b c s
AND Plane
OR Plane
bc
ac
ab
abc
abc
abc
abc
a
b c
s c
out
Inputs
Outputs

S. Reda EN1600 SP’08

[10] http://scale.engin.brown.edu/classes/EN1600S08/

FPGA - principiu

FPGA Field Programmable Gate Arrays

Contin celule logice

programabile intern ca si functie logica si conexiuni programabile pe orizontala si verticala

Programabile sau

reprogramabile in campul de lucru

logica si conexiuni programabile pe orizontala si verticala • Programabile sau reprogramabile in campul de lucru

Structura logica FPGA

Structura logica FPGA

Chip-ul FPGA

Chip-ul FPGA

Elemente functionale tipice FPGA

Elemente logice / Logic Elements (LEs)

Conexiuni / Routing

Blocuri de intrare-iesire / Input/Output logic

Alte facilitati / Extra features

clocking

memory

memory interfaces

Multipliers

Etc.

Elementul logic FPGA generic

Elementul logic FPGA generic

Programmable logic blocks (lookup tables)

a

b

c

Required function & | y
Required function
&
|
y

y = (a & b) | !c

Truth table

a

b

c

y

0

0

0

1

0

0

1

0

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

0

1

1

0

1

1

1

1

1

1 0 1 0 1 1 0 1 1 1 1 1 Programmed LUT SRAM cells

Programmed LUT

SRAM cells 1 0 0 0 0 0 0 1 1 0 1 0 1
SRAM cells
1
0
0 0
0
0
0 1
1
0
1 0
1
0
1 1
1
1 0 0
0
1 0 1
1
1 1 0
1
1 1 1
a b c
8:1 Multiplexer

y

-Informatia programabila poate fi stocata in SRAM sau FLASH -LUT uzuale au in mod tipic 4 intrari

[10] http://scale.engin.brown.edu/classes/EN1600S08/

Arhitectura FPGA tipica

a

b

c

d

e

clock

4-input y LUT mux flip-flop q
4-input
y
LUT
mux
flip-flop
q
Switch box
Switch
box

Programmable

interconnect

Programmable

logic blocks

[10] http://scale.engin.brown.edu/classes/EN1600S08/

ASIC

ASIC-uri realizate initial pe arii de porti

(1980)

ASIC • ASIC-uri realizate initial pe arii de porti (1980) Channeled Channelless

Channeled

ASIC • ASIC-uri realizate initial pe arii de porti (1980) Channeled Channelless

Channelless

ASIC

ASIC realizat pe celule standard, avnd

functionalitate predifinita si performante

cunoscute (1990)

ASIC • ASIC realizat pe celule standard, avnd functionalitate predifinita si performante cunoscute (1990)
ASIC • ASIC realizat pe celule standard, avnd functionalitate predifinita si performante cunoscute (1990)

ASICs

vs.

FPGAs

ASICs vs. FPGAs
ASICs vs. FPGAs

Proiectarea cu FPGA vs. ASIC

Proiectarea cu FPGA vs. ASIC DFT = Design For testability http://www.xilinx.com/fpga/asic.htm

DFT = Design For testability

http://www.xilinx.com/fpga/asic.htm

Proiectarea cu FPGA vs. ASIC

Proiectarea cu FPGA vs. ASIC http://www.xilinx.com/

http://www.xilinx.com/

Programabilitate (1)

Programabilitate (1) http://www.fpga-guide.com

http://www.fpga-guide.com

Programabilitate (2)

Programabilitate (2)

Antifuzibil (antifuse) (1)

Antifuzibil (antifuse) (1) A programmable chip technology that creates permanent, conductive paths between transistors. In

A programmable chip technology that creates permanent, conductive paths between transistors.

In contrast to "blowing fuses" in the

fusible link method, which opens a

circuit by breaking apart a conductive

path, the antifuse method closes the circuit by "growing" a conductive via.

Two metal layers sandwich a layer of non-conductive, amorphous silicon. When voltage is applied to this middle

layer, the amorphous silicon is turned

into polysilicon, which is conductive.

http://encyclopedia2.thefreedictionary.com/antifuse

Antifuzibil (antifuse) (2)

Procesul fizic de realizare a caii coductuctoare (Actel)

Antifuzibil (antifuse) (2) • Procesul fizic de realizare a caii coductuctoare (Actel)

Antifuzibil (Antifuse) (2)

Procesul fizic de realizare a caii coductuctoare (Qick Logic)

Antifuzibil (Antifuse) (2) • Procesul fizic de realizare a caii coductuctoare (Qick Logic)

Structura logica programabila, cu antifuzibile

Structura logica programabila, cu antifuzibile

EPROM

Tranzistor MOS cu poarta flotanta

EPROM Tranzistor MOS cu poarta flotanta
EPROM Tranzistor MOS cu poarta flotanta
EPROM Tranzistor MOS cu poarta flotanta
EPROM Tranzistor MOS cu poarta flotanta
EPROM Tranzistor MOS cu poarta flotanta

http://web.eecs.umich.edu/~prabal/teaching/eecs373-f10/readings/rom-eprom-eeprom-technology.pdf

EPROM / EEPROM

programable technology

EPROM / EEPROM programable technology

EEPROM

EEPROM

Flash

- FLASH utilizeaza tranzistoare cu poarta flotanta ca si EEPROM

- Celule flash NOR sunt conectate in paralel si pot fi operate individual

- Celule flash NAND sunt conectate in serie, nu pot fi programaye individual iar citirea se face in serie

NOR FLASH

flash NAND sunt conectate in serie, nu pot fi programaye individual iar citirea se face in

NAND FLASH

flash NAND sunt conectate in serie, nu pot fi programaye individual iar citirea se face in

Avantaje:

SRAM

Reconfigurare dinamica

Densitate crescuta

Evolutie rapida odata cu tehnologiile de stocare

SRAM generale

Flexibilitate

Dezavantaje:

Volatile

Consum de energie ridicat

Configurare cu SRAM

Configurare cu SRAM • Aproape toate famililiile FPGA folosesc SRAM • Celulele SRAM sunt utilizate in

Aproape toate famililiile FPGA folosesc SRAM

Celulele SRAM sunt utilizate in 3 moduri:

- Implementare de functii logice LUT

- Ca blocuri de memorie inglobate (buffer stocare)

- Ca elemente de control comutatoarelor de configurare si a rutelor

Utilizare SRAM

Tranzistor de trecere comandat cu SRAM

SRAM 1 bit
SRAM 1 bit
SRAM 1 bit
SRAM

SRAM

1 bit

1 bit

SRAM 1 bit
SRAM 1 bit
SRAM 1 bit
SRAM 1 bit
SRAM 1 bit
Utilizare SRAM Tranzistor de trecere comandat cu SRAM SRAM 1 bit MUX comandat cu celule SRAM
Utilizare SRAM Tranzistor de trecere comandat cu SRAM SRAM 1 bit MUX comandat cu celule SRAM
Utilizare SRAM Tranzistor de trecere comandat cu SRAM SRAM 1 bit MUX comandat cu celule SRAM

MUX comandat cu celule SRAM

B0 MUX SRAM B1 SRAM
B0
MUX
SRAM
B1
SRAM

Nod de conectare si LUT cu SRAM

Nod de conectare si LUT cu SRAM

Matrice programabila de

comutatoare

Matrice programabila de comutatoare

Structura programabila cu SRAM

Structura programabila cu SRAM

Programmable interconnects (global)

Switch

box

Programmable interconnects (global) Switch box [10] http://scale.engin.brown.edu/classes/EN1600S08/

[10] http://scale.engin.brown.edu/classes/EN1600S08/

Programarea FPGA

Configuration data in Configuration data out I/O pin/pad = SRAM cell =
Configuration data in
Configuration data out
I/O pin/pad
=
SRAM cell
=

[10] http://scale.engin.brown.edu/classes/EN1600S08/

Facilitati oferite de FPGA moderne

Facilitati oferite de FPGA moderne

Etapele proiectarii unui sistem

Descriere

comportamentala

digital

proiectarii unui sistem Descriere comportamentala digital Sinteza Implementare fizica • Descrierea unui circuit

Sinteza

unui sistem Descriere comportamentala digital Sinteza Implementare fizica • Descrierea unui circuit folosind

Implementare

fizica

Descrierea unui circuit folosind mijloace adecvate (HDLs)

Simulare logica

Sinteza functionala pe baza instrumentelor specifice

Simulare functionala

Implementare fizica

Testare

Niveluri de proiectare VLSI

Niveluri de proiectare VLSI

Etape in proiectarea VLSI

Etape in proiectarea VLSI
Overview

Overview

Overview
Overview