library ieee;

use IEEE.std_logic_1164.all;
entity Mux4x1 is
port(G1,G2,A,B : in std_logic;
C1, C2 : in std_logic_vector(3 downto 0);
Y1, Y2 : out std_logic);
end Mux4x1;
--**************************************
library ieee;
use IEEE.std_logic_1164.all;
entity inv_gate is
port(signal A : in std_logic;
signal B : out std_logic);
end inv_gate;
architecture invDATA of inv_gate is begin
B <= not A;
end invDATA;
--*************************************
library ieee;
use IEEE.std_logic_1164.all;
entity and_4_gate is
port(signal A,B,C,D : in std_logic;
signal F : out std_logic);
end and_4_gate;
architecture and4 of and_4_gate is begin
F <= A and B and C and D;
end and4;
--**************************************
library ieee;
use IEEE.std_logic_1164.all;
entity or_4_gate is
port(signal A,B,C,D : in std_logic;
signal F : out std_logic);
end or_4_gate;
architecture or4 of or_4_gate is begin
F <= A or B or C or D;
end or4;
--******************************************
architecture Data_Flow of Mux4x1 is
signal s : std_logic_vector(2 downto 0);
begin
s <= A & B & G1;
with s select
Y1 <= C1(0) when "000",
C1(1) when "010",
C1(2) when "100",
C1(3) when "110",
wish s select
Y1 <= C2(0)
C2(1)
C2(2)
C2(3)

when
when
when
when

"000",
"010",
"100",
"110",

end Data_Flow;
--***********************************

architecture Behavioral of Mux4x1 is

signal F1 : std_logic;
signal F2 : std_logic;
begin
Mux1: process(A, B, C1, G1, F1)
variable s : std_logic_vector(2 downto 0)
begin
s := A&B&G1
case s is
when "000" => F1 <= C1(0) after 22 ns;
when "010" => F1 <= C1(1) after 22 ns;
when "100" => F1 <= C1(2) after 22 ns;
when "110" => F1 <= C1(3) after 22 ns;
when others => F1 <= 'U' after 22 ns;
end case;
end process Mux1;
Mux2: process(A, B, C2, G2, F2)
variable s : std_logic_vector(2 downto 0)
begin
s := A&B&G2
case s is
when "000" => F2 <= C2(0) after 22 ns;
when "010" => F2 <= C2(1) after 22 ns;
when "100" => F2 <= C2(2) after 22 ns;
when "110" => F2 <= C2(3) after 22 ns;
when others => F2 <= 'U' after 22 ns;
end case;
end process Mux2;

--***********************************
architecture behave of Mux4x1 is
begin
side1 : process (A, B) is begin
case std_logic_vector'(A, B, G1) is
when "000" => Y1 <= C1(0) after 22
when "010" => Y1 <= C1(1) after 22
when "100" => Y1 <= C1(2) after 22
when "110" => Y1 <= C1(3) after 22
when others => Y1 <= '0' after
end case;
end process;

ns;
ns;
ns;
ns;
22 ns;

side2 : process (A, B) is begin

case std_logic_vector'(A, B, G2) is
when "001" => Y2 <= C2(0) after 22
when "011" => Y2 <= C2(1) after 22
when "101" => Y2 <= C2(2) after 22
when "111" => Y2 <= C2(3) after 22
when others => Y2 <= '0' after
end case;
end process;

ns;
ns;
ns;
ns;
22 ns;

end behave;

--************************************
architecture Mux_4x1 of Mux4x1 is
signal Out_A_0, Out_A_1, Out_A_2, Out_A_3, Out_B_0, Out_B_1, Out_B_2, Ou
t_B_3: std_logic;
begin
Out_A_3 <= not G1 and A and B and C1(0);
Out_A_2 <= not G1 and not A and B and C1(1);
Out_A_1 <= not G1 and A and not B and C1(2);
Out_A_0 <= not G1 and not A and not B and C1(3);
Y1 <= Out_A_0 or Out_A_1 or Out_A_2 or Out_A_3 after 22 ns;
Out_B_3
Out_B_2
Out_B_1
Out_B_0

<=
<=
<=
<=

not
not
not
not

G1
G1
G1
G1

and
and
and
and

A and
not A
A and
not A

B and C2(0);
and B and C2(1);
not B and C2(2);
and not B and C2(3);

Y2 <= Out_B_0 or Out_B_1 or Out_B_2 or Out_B_3 after 22 ns;

end Mux_4x1;
architecture Structural of Mux4x1 is
component inv_gate is
port(Signal A : in std_logic;
Signal B : out std_logic);
end component;
component and_4_gate is
port(signal A,B,C,D : in std_logic;
signal F : out std_logic);
end component;
component or_4_gate is
port(signal A,B,C,D : in std_logic;
signal F : out std_logic);
end component;
signal Out_A_0, Out_A_1, Out_A_2, Out_A_3, Out_B_0, Out_B_1, Out_B_2, Out_B_3, n
otB, notA, notG1, notG2: std_logic;
begin
AND4_0 : and_4_gate
port map(A => notA, B => notB, C => notG1, D => C1(0), F => Out_A_0);
AND4_1 : and_4_gate
port map(A => A, B => notB, C => notG1, D => C1(1), F => Out_A_1);
AND4_2 : and_4_gate
port map(A => notA, B => B, C => notG1, D => C1(2), F => Out_A_2);
AND4_3 : and_4_gate
port map(A => A, B => B, C => notG1, D => C1(3), F => Out_A_3);

AND4_4 : and_4_gate
port map(A => notA, B => notB, C => notG2, D => C2(0), F => Out_B_0);
AND4_5 : and_4_gate

port map(A => A, B => notB, C => notG2, D => C2(1), F => Out_B_1);
AND4_6 : and_4_gate
port map(A => notA, B => B, C => notG2, D => C2(2), F => Out_B_2);
AND4_7 : and_4_gate
port map(A => A, B => B, C => notG2, D => C2(3), F => Out_B_3);

INV0 : inv_gate
port map (A => G1, B => notG1);
INV1 : inv_gate
port map (A => G2, B => notG2);
2
OR4_0 : or_4_gate
port map(A => Out_A_0, B => Out_A_1, C => Out_A_2, D => Out_A_3, F => Y1);
OR4_1 : or_4_gate
port map(A => Out_B_0, B => Out_B_1, C => Out_B_2, D => Out_B_3, F => Y2);
end Structural;
--************************************
library IEEE;
use IEEE.STD_lOGIC_1164.ALL;
use ieee.std_logic.unsigned.all'
use ieee.std_logic_arith.all;
entity Mux4x1_tb is
end Mux4x1_tb;
architecture tb of Mux4x1_tb is
component Mux4x1 is
port(
signal A, B, G1, G2 : in std_logic;
signal C1, C2 : in std_logic_vector(3 downto 0);
signal Y1, Y2
: out std_logic;
end component;
signal A B, G1, G2, C1, C2 : std_logic := '0';
signal C1, C2 : std_logic_vector(3 downto 0) := '0';
signal Y1, Y2
: std_logic_vector(2 downto 0);
for UUT1 : Mux4x1 use entity work.Mux4x1(Beharvioral);
for UUT2 : Mux4x1 use entity work.Mux4x1(Data_Flow)
for UUT3 : Mux4x1 use entity work.Mux4x1(Structural)
begin
UUT1: Mux4x1 port map( A => A, B =>B, C1 => C1, C2 => C2, G1 => G1, G2 =
> G2, Y1 => Y1(0), Y2 => Y2(0))
UUT2: Mux4x1 port map( A => A, B =>B, C1 => C1, C2 => C2, G1 => G1, G2 =
> G2, Y1 => Y1(1), Y2 => Y2(1))
UUT3: Mux4x1 port map( A => A, B =>B, C1 => C1, C2 => C2, G1 => G1, G2 =
> G2, Y1 => Y1(2), Y2 => Y2(2))
process
variable sAB : std_logic_vector(1 downto 0);
begin

sAB := A & B;
wait for 22 ns;
assert (sAB = "00" and Y1(0)/= C1(0)) report "Error Y1 C1(0) -Behav
ioral"
assert (sAB = "01" and Y1(0)/= C1(1)) report "Error Y1 C1(1) -Behav
ioral"
assert (sAB = "10" and Y1(0)/= C1(2)) report "Error Y1 C1(2) -Behav
ioral"
assert (sAB = "11" and Y1(0)/= C1(3)) report "Error Y1 C1(3) -Behav
ioral"
assert (sAB = "00" and Y2(0)/= C2(0)) report "Error Y2 C1(0) -Behav
ioral"
assert (sAB = "01" and Y2(0)/= C2(1)) report "Error Y2 C1(1) -Behav
ioral"
assert (sAB = "10" and Y2(0)/= C2(2)) report "Error Y2 C1(2) -Behav
ioral"
assert (sAB = "11" and Y2(0)/= C2(3)) report "Error Y2 C1(3) -Behav
ioral"
assert (sAB = "00" and Y1(1)/= C1(0)) report "Error Y1 C1(0) -Data_
Flow"
assert (sAB = "01" and Y1(1)/= C1(1)) report "Error Y1 C1(1) -Data_
Flow"
assert (sAB = "10" and Y1(1)/= C1(2)) report "Error Y1 C1(2) -Data_
Flow"
assert (sAB = "11" and Y1(1)/= C1(3)) report "Error Y1 C1(3) -Data_
Flow"
assert (sAB = "00" and Y2(1)/= C2(0)) report "Error Y2 C1(0) -Data_
Flow"
assert (sAB = "01" and Y2(1)/= C2(1)) report "Error Y2 C1(1) -Data_
Flow"
assert (sAB = "10" and Y2(1)/= C2(2)) report "Error Y2 C1(2) -Data_
Flow"
assert (sAB = "11" and Y2(1)/= C2(3)) report "Error Y2 C1(3) -Data_
Flow"
assert (sAB = "00" and Y1(2)/= C1(0)) report "Error Y1 C1(0) -Struc
tural
assert (sAB = "01" and Y1(2)/= C1(1)) report "Error Y1 C1(1) -Struc
tural
assert (sAB = "10" and Y1(2)/= C1(2)) report "Error Y1 C1(2) -Struc
tural
assert (sAB = "11" and Y1(2)/= C1(3)) report "Error Y1 C1(3) -Struc
tural
assert (sAB = "00" and Y2(2)/= C2(0)) report "Error Y2 C1(0) -Struc
tural
assert (sAB = "01" and Y2(2)/= C2(1)) report "Error Y2 C1(1) -Struc
tural
assert (sAB = "10" and Y2(2)/= C2(2)) report "Error Y2 C1(2) -Struc
tural"
assert (sAB = "11" and Y2(2)/= C2(3)) report "Error Y2 C1(3) -Struc
tural"
end process;
end;