library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL; package example1 is type t_state is (st0,st1,st2,st3,st4,st5,st6,st7,st8); type t_data is array (0 to 7) of integer range 0 to 255; end package example1; library IEEE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.example1.all; entity main1 is Port ( text : in std_logic_vector (63 downto 0); --key : in integer; clk : in std_logic; reset : in std_logic; ctext : out std_logic_vector (63 downto 0)); end main1; architecture main1_arch of main1 is --component test1 is --Port ( text : in std_logic_vector (7 downto 0); --key : in integer;

-- clk : in std_logic; --reset : in std_logic; -- ctext : out std_logic_vector (7 downto 0)); --end component; signal key : integer range 0 to 255; signal key_val : std_logic_vector (7 downto 0); signal Xor_val : std_logic_vector (63 downto 0); signal tacit_logic_1 : integer ; --std_logic_vector (7 downto 0); signal tacit_logic_2 : integer ; -- std_logic_vector (7 downto 0); signal tacit_logic : std_logic_vector (63 downto 0); signal n : integer := 8; signal reverse_value: std_logic_vector (63 downto 0);

signal decimal_value:t_data; signal ciper_text: std_logic_vector (63 downto 0);

--signal n : std_logic_vector (7 downto 0):="00001000"; signal p_state, n_state : t_state; begin process(clk,reset) begin if (reset ='1')then ctext <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; elsif (clk ='1' and clk'event) then p_state <= n_state;

else null; end if; end process; -- second process is started process(p_state,text,key) begin case p_state is when st0=> key_val <= conv_std_logic_vector(key,8) ; n_state <= st1; when st1=> Xor_val(7 downto 0) <= text (7 downto 0) Xor key_val ; Xor_val(15 downto 8) <= text (15 downto 8) Xor key_val ; Xor_val(23 downto 16) <= text (23 downto 16) Xor key_val ; Xor_val(31 downto 24) <= text (31 downto 24) Xor key_val ; Xor_val(39 downto 32) <= text (39 downto 32) Xor key_val ; Xor_val(47 downto 40) <= text (47 downto 40) Xor key_val ; Xor_val(55 downto 48) <= text (55 downto 48) Xor key_val ; Xor_val(63 downto 56) <= text (63 downto 56) Xor key_val ; n_state <= st2; when st2=> --for i in 0 to 7 loop tacit_logic_1 <= (n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n* n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n) after 10 ns; --tacit_logic_1 <= (n*n*n*n*n*n*n*n) after 10 ns;

--tacit_logic_1(2) <= (n*n*n*n*n*n*n*n) after 10 ns; --tacit_logic_1(3) <= (n*n*n*n*n*n*n*n) after 10 ns; --tacit_logic_1(4) <= (n*n*n*n*n*n*n*n) after 10 ns; --tacit_logic_1(5) <= (n*n*n*n*n*n*n*n) after 10 ns; --tacit_logic_1(6) <= (n*n*n*n*n*n*n*n) after 10 ns; --tacit_logic_1(7) <= (n*n*n*n*n*n*n*n) after 10 ns; -- end loop; n_state <= st3; when st3=> --for i in 0 to 7 loop tacit_logic_2 <= (key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key* key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*k ey*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key*key ); --tacit_logic_2 <= (key *key *key *key *key *key *key *key); --tacit_logic_2(2) <= (key *key *key *key *key *key *key *key); --tacit_logic_2(3) <= (key *key *key *key *key *key *key *key); -- tacit_logic_2(4) <= (key *key *key *key *key *key *key *key); ---tacit_logic_2(5) <= (key *key *key *key *key *key *key *key); tacit_logic_2(6) <= (key *key *key *key *key *key *key *key); tacit_logic_2(7) <= (key *key *key *key *key *key *key *key);

--end loop; n_state <= st4; when st4=> --tacit_logic (7 downto 0) <= conv_std_logic_vector(tacit_logic_1(0),8)XOR conv_std_logic_vector(tacit_logic_2(0),8);

--tacit_logic (15 downto 8) <= conv_std_logic_vector(tacit_logic_1(1),8)XOR conv_std_logic_vector(tacit_logic_2(1),8); --tacit_logic (23 downto 16) <= conv_std_logic_vector(tacit_logic_1(2),8)XOR conv_std_logic_vector(tacit_logic_2(2),8); --tacit_logic (31 downto 24) <= conv_std_logic_vector(tacit_logic_1(3),8)XOR conv_std_logic_vector(tacit_logic_2(3),8); --tacit_logic (39 downto 32) <= conv_std_logic_vector(tacit_logic_1(4),8)XOR conv_std_logic_vector(tacit_logic_2(4),8); --tacit_logic (47 downto 40) <= conv_std_logic_vector(tacit_logic_1(5),8)XOR conv_std_logic_vector(tacit_logic_2(5),8); --tacit_logic (55 downto 48) <= conv_std_logic_vector(tacit_logic_1(6),8)XOR conv_std_logic_vector(tacit_logic_2(6),8); --tacit_logic (63 downto 56) <= conv_std_logic_vector(tacit_logic_1(7),8)XOR conv_std_logic_vector(tacit_logic_2(7),8);

tacit_logic (63 downto 0) <= conv_std_logic_vector(tacit_logic_1,64)XOR conv_std_logic_vector(tacit_logic_2,64); --tacit_logic (15 downto 8) <= conv_std_logic_vector(tacit_logic_1,8)XOR conv_std_logic_vector(tacit_logic_2,8); --tacit_logic (23 downto 16) <= conv_std_logic_vector(tacit_logic_1,8)XOR conv_std_logic_vector(tacit_logic_2,8); --tacit_logic (31 downto 24) <= conv_std_logic_vector(tacit_logic_1,8)XOR conv_std_logic_vector(tacit_logic_2,8); --tacit_logic (39 downto 32) <= conv_std_logic_vector(tacit_logic_1,8)XOR conv_std_logic_vector(tacit_logic_2,8); --tacit_logic (47 downto 40) <= conv_std_logic_vector(tacit_logic_1,8)XOR conv_std_logic_vector(tacit_logic_2,8); --tacit_logic (55 downto 48) <= conv_std_logic_vector(tacit_logic_1,8)XOR conv_std_logic_vector(tacit_logic_2,8); --tacit_logic (63 downto 56) <= conv_std_logic_vector(tacit_logic_1,8)XOR conv_std_logic_vector(tacit_logic_2,8);

n_state <= st5; when st5=> reverse_value(63 downto 0) <= tacit_logic(0) & tacit_logic(1) & tacit_logic(2) tacit_logic(4) & tacit_logic(5) & tacit_logic(6) & tacit_logic(7)& & tacit_logic(3) &

tacit_logic(8) & tacit_logic(9) & tacit_logic(10) & tacit_logic(11) & tacit_logic(12) & tacit_logic(13) & tacit_logic(14) & tacit_logic(15)& tacit_logic(16) & tacit_logic(17) & tacit_logic(18) & tacit_logic(19) & tacit_logic(20) & tacit_logic(21) & tacit_logic(22) & tacit_logic(23)& tacit_logic(24) & tacit_logic(25) & tacit_logic(26) & tacit_logic(27) & tacit_logic(28) & tacit_logic(29) & tacit_logic(30) & tacit_logic(31)& tacit_logic(32) & tacit_logic(33) & tacit_logic(34) & tacit_logic(35) & tacit_logic(36) & tacit_logic(37) & tacit_logic(38) & tacit_logic(39)& tacit_logic(40) & tacit_logic(41) & tacit_logic(42) & tacit_logic(43) & tacit_logic(44) & tacit_logic(45) & tacit_logic(46) & tacit_logic(47)& tacit_logic(48) & tacit_logic(49) & tacit_logic(50) tacit_logic(51) & tacit_logic(52) & tacit_logic(53) & tacit_logic(54) & tacit_logic(55)& &

tacit_logic(56) & tacit_logic(57) & tacit_logic(58) & tacit_logic(59) & tacit_logic(60) & tacit_logic(61) & tacit_logic(62) & tacit_logic(63);

--reverse_value(15 downto 8) <= tacit_logic(8) & tacit_logic(9) & tacit_logic(10) & tacit_logic(11) & tacit_logic(12) & tacit_logic(13) & tacit_logic(14) & tacit_logic(15); --reverse_value(23 downto 16) <= tacit_logic(16) & tacit_logic(17) & tacit_logic(18) & tacit_logic(19) & tacit_logic(20) & tacit_logic(21) & tacit_logic(22) & tacit_logic(23); --reverse_value(31 downto 24) <= tacit_logic(24) & tacit_logic(25) & tacit_logic(26) & tacit_logic(27) & tacit_logic(28) & tacit_logic(29) & tacit_logic(30) & tacit_logic(31); --reverse_value(39 downto 32) <= tacit_logic(32) & tacit_logic(33) & tacit_logic(34) & tacit_logic(35) & tacit_logic(36) & tacit_logic(37) & tacit_logic(38) & tacit_logic(39); --reverse_value(47 downto 40) <= tacit_logic(40) & tacit_logic(41) & tacit_logic(42) & tacit_logic(43) & tacit_logic(44) & tacit_logic(45) & tacit_logic(46) & tacit_logic(47); --reverse_value(55 downto 48) <= tacit_logic(48) & tacit_logic(49) & tacit_logic(50) & tacit_logic(51) & tacit_logic(52) & tacit_logic(53) & tacit_logic(54) & tacit_logic(55);

--reverse_value(63 downto 56) <= tacit_logic(56) & tacit_logic(57) & tacit_logic(58) & tacit_logic(59) & tacit_logic(60) & tacit_logic(61) & tacit_logic(62) & tacit_logic(63); n_state <= st6; when st6=> decimal_value(0) <= conv_integer (reverse_value(7 downto 0)); decimal_value(1) <= conv_integer (reverse_value(15 downto 8)); decimal_value(2) <= conv_integer (reverse_value(23 downto 16)); decimal_value(3) <= conv_integer (reverse_value(31 downto 24)); decimal_value(4) <= conv_integer (reverse_value(39 downto 32)); decimal_value(5) <= conv_integer (reverse_value(47 downto 40)); decimal_value(6) <= conv_integer (reverse_value(55 downto 48)); decimal_value(7) <= conv_integer (reverse_value(63 downto 56)); n_state <= st7; when st7=> ciper_text(7 downto 0) <= conv_std_logic_vector(decimal_value(0),8); ciper_text(15 downto 8) <= conv_std_logic_vector(decimal_value(1),8); ciper_text(23 downto 16) <= conv_std_logic_vector(decimal_value(2),8); ciper_text(31 downto 24) <= conv_std_logic_vector(decimal_value(3),8); ciper_text(39 downto 32) <= conv_std_logic_vector(decimal_value(4),8); ciper_text(47 downto 40) <= conv_std_logic_vector(decimal_value(5),8); ciper_text(55 downto 48) <= conv_std_logic_vector(decimal_value(6),8); ciper_text(63 downto 56) <= conv_std_logic_vector(decimal_value(7),8); --n_state <= st7; n_state <= st8; when st8=> ctext <= ciper_text ;

-- n_state <= st0; end case; -- ctext <= ciper_text after 10 ns; end process; end main1_arch;