Bus

DDR2
Memory
Controller
Bus
External
DDR2 SDRAM
SCR
ARM
Master
Peripherals
EDMA
VPSS

DDR2
memory
controller
/2
PLLC2
/3
PLLC1
PLL2_SYSCLK2
VCLK
DDR_CLK0 DDR_CLK0
X2_CLK
SYSCLK3

DDR_D[31:0]
DDR2
memory
controller
DDR_CLK0
DDR_CLK0
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BS[2:0]
DDR_DQS[3:0]
DDR_A[12:0]
DDR_ZN
DDR_ZP
200
200

DDR_CLK0
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[12:0]
DDR_BS[2:0]
DDR_DQM[3:0]
RFR
DDR_CLK0

DDR_CLK0
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_A[12,11, 9:0]
DDR_BS[2:0]
DDR_DQM[3:0]
DCAB
DDR_A[10]
DDR_CAS
DDR_CLK0

DDR_CLK0
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_A[12,11, 9:0]
DDR_BS[2:0]
DDR_DQM[3:0]
DEAC
DDR_A[10]
DDR_CAS
DDR_CLK0

DDR_CLK0
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_BS[2:0]
DDR_DQM[3:0]
ACTV
DDR_A[12:0]
DDR_CAS
BANK
ROW
DDR_CLK0

DDR_CLK0
DDR_CKE
DDR_CS
DDR_WE
DDR_CAS
DDR_DQM[3:0]
DDR_D[31:0]
DDR_A[12:0]
DDR_RAS
DDR_DQS[3:0]
COL
BANK
DDR_A[10]
DDR_BS[2:0]
CAS Latency
D0 D1 D2 D3 D4 D5 D6 D7
DDR_CLK0

DDR_CLK0
DDR_CKE
DDR_CS
DDR_WE
DDR_CAS
DDR_DQM[3:0]
DDR_D[31:0]
DDR_A[12:0]
DDR_RAS
DDR_DQS[3:0]
COL
BANK
DDR_A[10]
DDR_BS[2:0]
DQM7
Sample
D0 D1 D2 D3 D4 D5 D6 D7
DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM8
Write Latency
DDR_CLK0

DDR_CLK0
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_BS[2:0]
COL
MRS/EMRS
DDR_A[12:0]
DDR_CAS
BANK
DDR_CLK0

DDR2 memory controller data bus

DDR_D[31:24] DDR_D[23:16] DDR_D[15:8] DDR_D[7:0]
32-bit memory device
16-bit memory device

Col. 0 Col. 1 Col. 2 Col. 3 Col. 4 Col. M1 Col. M

Row 0, bank 0
Row 0, bank 1
Row 0, bank 2
Row 0, bank P
Row 1, bank 1
Row 1, bank 0
Row 1, bank 2
Row 1, bank P
Row N, bank 2
Row N, bank 1
Row N, bank 0
Row N, bank P

0 1 2 3 M Bank 0
Row 0
Row 1
Row 2
Row N
C
o
l l
C
o
l
C
o
l
C
o
Row 0
Row N
Row 1
Row 2
C C
Bank 1
l l
0 2 1
o o
C C
l l
3 M
o o
Row 0
Row N
Row 1
Row 2
C C
Bank 2
l l
0 2 1
o o
l l l l
Row N
Row 2
Row 0
Row 1
Bank P 0 1 2 3 M
C C
l l
3 M
o o
o
C
o
C
o
C
o
C

Command/Data
Scheduler
Command FIFO
Write FIFO
Read FIFO
Registers
Command
to Memory
Write Data
to Memory
Read Data
from
Memory
Command
Data

DDR2
memory
controller
registers
Hard
Reset from
PLLC1
State
machine
VRST
VCTL_RST
DDR
PSC

PLLC2
CLKSTOP_REQ
DDR
PSC
CLKSTOP_ACK
MODCLK
MODRST
LRST
DDR2
memory
controller
VCLKSTOP_REQ
VCLKSTOP_ACK
VCLK
VRST
VCTL_RST
X2_CLK
/2
SYSCLK3
PLL2_SYSCLK2

DDR_CLK0
DDR_CLK0
DDR_CKE
DDR_CS
DDR_WE
DDR_RAS
DDR_CAS
DDR_DQM[0]
DDR_DQM[1]
DDR_DQS[0]
DDR_DQS[1]
DDR_BS[2:0]
DDR_A[12:0]
DDR_D[15:0]
DDR_DQM[2]
DDR_DQM[3]
DDR_DQS[2]
DDR_DQS[3]
DDR_D[31:16]
DDR_ZN
DDR_ZP
DDR2
memory
CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
LDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
DDR2
memory
x16bit
LDQS
DQ[15:0]
A[12:0]
BA[2:0]
UDQS
DDR2
memory
x16bit
UDM
LDM
CAS
RAS
WE
CS
CKE
CK
CK
200 200
controller
DDR_CLK0
DDR_CLK0
DDR_CKE
DDR_CS
DDR_WE
DDR_RAS
DDR_CAS
DDR_DQM[0]
DDR_DQM[1]
DDR_DQS[0]
DDR_DQS[1]
DDR_BS[2:0]
DDR_A[12:0]
DDR_D[15:0]
DDR_ZN
DDR_ZP
CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
LDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
DDR2
memory
x16bit
200
200
DDR2
memory
controller