Very Large Scale Integration II - VLSI II

Adder Topologies

Grer zbek
ITU VLSI Laboratories
Istanbul Technical University
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07.12.2013

Outline

Single Bit Addition

Carry Propagate Adders

PGK Representation & PG Diagram

Tree Adders (Parallel Prefix Adders)

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Adder Topologies

Single Bit Addition

Half Adder
Full Adder

Carry Propagate Adders

Carry Ripple (normal & inverse)

Carry Skip
Carry Select
Carry Lookahead

Tree Adders (parallel

prefix adders)

Brent Kung
Sklansky
Kogge-Stone
Ladner-Fischer
Knowles
Han-Carlson
Sparse Tree

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Single Bit Addition

Whats the deal?

All we want to do is add up a couple numbers

B
C
S

AB etc.

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Half Adder

2 bit input, 2 bit output

Used to build a Full Adder
A

S A B

Cout
S

Cout A.B

Cout

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Full Adder

Main element of n-bit adders

Consists of 2 HAs
A

Ci

Co

S A B Ci

Cout MAJ ( A, B, Ci )

Cout

Ci
S

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Carry Propagate Adders

N-bit adder called as CPA

Each sum bit consists inf. of all previous carries

Its the main problem to calculate them all quickly
AN...1 BN...1

Cout

+
SN...1

Cout

Cin

00000
1111
+0000
1111

Cin

Cout

11111
1111
+0000
0000

Cin
carries
A4...1
B4...1
S4...1

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Carry Ripple Adder

Simplest Design: Cascaded FAs

Second area efficient of all

Slowest of all
Default topology to be synthesized
A4

B4

Cout

A3

B3

C3
S4

A2

B2

C2
S3

A1

B1
Cin

C1
S2

S1

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Carry Ripple Adder Delay

Delay grows with O(N)

Every FA waits for
previous output

Cin
B1
B2
B3
B4
A1
A2
A3
A4

S1
S2
S3
S4
Cout

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Inverse Carry Ripple Adder

A4

Uses inverting FAs

Most area efficient of all

Second Slowest of all

B4

Cout

A3

B3

C3

MINORITY

A2

B2

C2

A1

B1

Cin

C1

S4

S3

S2

S1

C
Cout

Cout

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Propagate, Generate and Kill the Carry

Three operation can be defined to describe

status of carry

Propagate: Previous carry is propagated to next bit

Generate: Generate a carry bit
Kill: Kill the previous carry
Gi:i Gi Ai .Bi
Pi:i Pi Ai Bi
K i:i K i Ai Bi

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Propagate and Generate the Carry

Kill is not used mostly

Carry Merge Tree (CM)

Initial values

Gi: j Gi:k Pi:k .Gk 1: j

G0:0 G0 Cin

Pi: j Pi:k .Pk 1: j

P0:0 P0 0

Final Sum
Si Pi Gi 1:0
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PG Diagram
A4

B4

A3

B3

A2

B2

A1

B1

Cin

1: Bitwise PG logic
G4

P4

G3

P3

G2

P2

G1

P1

G0

P0

2: Group PG logic
G3:0

G2:0

G1:0

G0:0

C3

C2

C1

C0

3: Sum logic

C4
Cout

S4

S3

S2

S1

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Carry Ripple in PG Diagram 1

Gi:0 Gi Pi .Gi 1:0
A4

B4

G4

P4

A3

B3

G3

P3

A2

B2

G2

P2

A1

B1

G1

P1

Cin

G0

G3:0

G2:0

G1:0

G0:0

C3

C2

C1

C0

P0

C4
Cout

S4

S3

S2

S1

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Carry Ripple in PG Diagram 2

Bit Position

tripple t pg ( N 1)t AO txor

15

14

13

12

11

10

1-bit prop/gen
cell

delay of And/Or
in grey cell
Delay

Final SUM bit

xor

Delay grows as O(N)

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

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PG Diagram Notation
Black cell
i:k

Gray cell

k-1:j

i:k

i:j
Gi:k
Pi:k
Gk-1:j
Pk-1:j

Buffer

k-1:j

i:j

i:j

i:j
Gi:j

Gi:k
Pi:k
Gk-1:j

Gi:j

Pi:j

Both Gen/Prop

Generate only

Gi:j

Gi:j

Pi:j

Pi:j

Different load

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Carry Skip Adder

Better delay growth rate is necessary

Improves critical path delay

Cout

A16:13 B16:13

A12:9 B12:9

A8:5 B8:5

A4:1

P16:13

P12:9

P8:5

P4:1

1
0

C12
+
S16:13

1
0

C8
+
S12:9

1
0

C4
+
S8:5

B4:1

1
Cin
0

+
S4:1

Red arrows: Allowed carry paths

Blue arrow: Non-allowed carry path

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Carry Skip in PG Diagram

For k n-bit groups

(N = nk)

Delay grows as
O(N)

16

15

14

13

12

11

10

skip thru muxes

First & last group
ripple

16:0 15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

tskip t pg 2 n 1 (k 1) t AO txor
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Carry Select Adder

Precomputes sum of n-bit groups for both carry

conditions
Final Mux selects the correct sum value when correct
carry value arrives
A16:13 B16:13

A12:9 B12:9

+
Cout
+

A4:1

B4:1

C8

C4
+

Cin

S12:9

B8:5
+

S16:13

C12
1

A8:5

S8:5

S4:1

tselect t pg n (k 2) t AO tmux
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Carry Select in PG Diagram

Precomputes
sum of n-bit
groups for both
carry conditions

15

14

13

12

11

10

13:12

9:8

14:12
15:12

5:4

10:8
11:8

6:4
7:4

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

tselect t pg n 1 (k 1) t AO t xor
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Carry Lookahead Adder

Computes Generate bits in parallel

Higher-valency cells are used
A16:13 B16:13
Cout

G16:13
P16:13
+
S16:13

C12

A12:9 B12:9
G12:9
P12:9
+
S12:9

A8:5 B8:5
C8

A4:1
C4

G8:5
P8:5

B4:1

G4:1
P4:1

S8:5

S4:1

Cin

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Carry Lookahead in PG Diagram

Collecting Generate/Propagate over many cells
16

15

14

13

12

11

10

16:0 15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

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Higher Valency Cells in CLA

Difficult to design with static CMOS

i:k k-1:l l-1:m m-1:j

i:j

Gi:k
Pi:k
Gk-1:l
Pk-1:l
Gl-1:m
Pl-1:m
Gm-1:j

Gi:j

Pi:j

Pm-1:j

Recursive definition of Generate

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Tree Adders

Parallel PG calculation without linear

propagation
O(log N) delay
Suitable for large-bit adders

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Brent-Kung

Very First and Bad one

15 14 13 12 11 10

15:14

13:12

15:12

11:10

9:8

11:8

7:6

5:4

7:4

15:8

3:2

1:0

3:0

7:0

11:0

13:0

9:0

5:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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Sklansky

Least Logic Levels

15 14 13 12 11 10

15:14

13:12

11:10

15:12 14:12

15:8

14:8

11:8 10:8

13:8

9:8

Highest Fanout

7:6

7:4

5:4

6:4

3:2

3:0

1:0

2:0

12:8

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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Kogge-Stone

Least Logic Levels

15 14 13 12 11 10

Hard to P&R

15:14 14:13 13:12 12:11 11:10 10:9

9:8

8:7

7:6

6:5

5:4

4:3

3:2

2:1

15:12 14:11 13:10

3:0

2:0

15:8

14:7

13:6

12:9

11:8 10:7

9:6

8:5

7:4

6:3

5:2

4:1

12:5

11:4 10:3

9:2

8:1

7:0

6:0

5:0

4:0

1:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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Tree Adder Taxonomy

Ideal N-bit tree adder would have

Describe adder with 3-D taxonomy (l, f, t)

L = log N logic levels

Fanout of 2
No more than one wiring track between levels
Logic levels:
Fanout:
Wiring tracks:

L+l
2f + 1
2t

Known tree adders sit on plane defined by

l + f + t = L-1

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Tree Adder Taxonomy 2

l (Logic Levels)

3 (7)
Brent-Kung

f (Fanout)
2 (6)

Sklansky
3 (9)

1 (5)

2 (5)
1 (3)
0 (2)

0 (4)
0 (1)

1 (2)

2 (4)

Kogge-Stone
3 (8)

t (Wire Tracks)

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Ladner-Fischer

A bit more logic levels

15 14 13 12 11 10

15:14

13:12

15:12

11:10

9:8

11:8

15:8

13:8

15:8

13:0

7:6

5:4

7:4

7:0

11:0

High Fanout
4

3:2

1:0

3:0

5:0

9:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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Knowles [2, 1, 1, 1]

So many cells and wires

15 14 13 12 11 10

Some Fanout

15:14 14:13 13:12 12:11 11:10 10:9

9:8

8:7

7:6

6:5

5:4

4:3

3:2

2:1

15:12 14:11 13:10

3:0

2:0

15:8

14:7

13:6

12:9

11:8 10:7

9:6

8:5

7:4

6:3

5:2

4:1

12:5

11:4 10:3

9:2

8:1

7:0

6:0

5:0

4:0

1:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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Han-Carlson

A bit more logic levels

15 14 13 12 11 10

Less cells

15:14

13:12

11:10

9:8

7:6

5:4

3:2

15:12

13:10

11:8

9:6

7:4

5:2

3:0

15:8

13:6

11:4

9:2

7:0

5:0

1:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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HOMEWORK

32-bit Sparse Tree Adder

Literature Search

PG Diagram

Black cells, grey cells, buffers, muxes etc.

Gate Level Schematic

What, When, Who, Where, Why, How

One per group

Delay Model wrt gate delays

tsparse=

1 week

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Tree Adder Taxonomy 3

(f)Ladner-Fischer
15

15:14

14

13

12

13:12

11

10

11:10

15:12

9:8

13:8

15:8

13:0

7:6

11:8

15:8

5:4

3:2

7:4

1:0

l (Logic Levels)

3:0

7:0

11:0

5:0

9:0

15:0 14:0 13:0 12:0 11:0 10:0

9:0

8:0

BrentKung

7:0

6:0

5:0

4:0

3:0

2:0

1:0

0:0

LadnerFischer

LadnerFischer

f (Fanout)

3 (7)

Sklansky

2 (6)

3 (9)

(d) Han-Carlson

1 (5)

2 (5)

15 14 13 12 11 10

1 (3)
0 (2)

0 (4)
0 (1)

HanCarlson

Knowles
[4,2,1,1]

15:14

13:12

11:10

9:8

7:6

5:4

3:2

15:12

13:10

11:8

9:6

7:4

5:2

3:0

15:8

13:6

11:4

9:2

7:0

5:0

1:0

1 (2)
HanCarlson

(e) Knowles [2,1,1,1]

15 14 13 12 11 10

Knowles
[2,1,1,1]

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

2 (4)
15:14 14:13 13:12 12:11 11:10 10:9

9:8

8:7

7:6

6:5

5:4

4:3

3:2

2:1

15:12 14:11 13:10

3:0

2:0

15:8

14:7

13:6

12:9

11:8 10:7

9:6

8:5

7:4

6:3

5:2

4:1

12:5

11:4 10:3

9:2

8:1

7:0

6:0

5:0

4:0

1:0

Kogge3 (8)
Stone

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

t (Wire Tracks)

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Summary

Adders with Area-Power-Delay Tradeoffs

Architecture

Classification Logic
Levels

Max
Tracks
Fanout

Cells

Carry-Ripple

N-1

Carry-Skip n=4

N/4 + 5

1.25N

Carry-Sel. n=4

N/4 + 2

2N

Brent-Kung

(L-1, 0, 0)

2log2N 1

2N

Sklansky

(0, L-1, 0)

log2N

N/2 + 1

0.5 Nlog2N

Kogge-Stone

(0, 0, L-1)

log2N

N/2

Nlog2N

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References

http://bwrc.eecs.berkeley.edu/icbook/Slides/chapt
er11.ppt
http://www.cmosvlsi.com/lect11.pdf
http://www.eng.utah.edu/~cs5830/Slides/addersx
2.pdf
Knowles, S. (1999) A Family of Adders

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