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SERVICE MANUAL

DVD VIDEO RECORDER


3
2004
XA020

DR-M10SEF, DR-M10SEK
DR-M10SE, DR-M10SER
DR-M10BE
Area Suffix
EK ------------------------ U.K.
EF --------------------- France
ER ---- Russian Federation
E ------- Continental Europe
Northern Europe

CABLE/DBS
TV DVD

TV TV/ STANDBY/ON
MUTING VIDEO TV/CBL/DBS DVD

ABC DEF TV VOLUME

GHI JKL MNO

PQRS TUV WXYZ CH

DBS

CANCEL AUX MEMO/MARK

VCR Plus+ PROG/CHECK REC LINK TIMER

TOP MENU NAVIGATION

ENTER

MENU RETURN

PREVIOUS NEXT

SLOW PLAY/SELECT SLOW

REC STOP/CLEAR PAUSE

REC MODE LIVE CHECK

OPEN/
SET UP DISPLAY ON SCREEN CLOSE SAT REC MODE

STANDBY/ON PULL - OPEN

F1 DV DV IN
PROGRESSIVE
AUDIO SUBTITLE ANGLE SCAN

S-VIDEO VIDEO L(MONO)-AUDIO-R

Since the whole mechanism assembly unit is replaced, the DVD recorder
mechanism of this unit need not be adjusted.

TABLE OF CONTENTS
1 PRECAUTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2 SPECIFIC SERVICE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
3 DISASSEMBLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
4 ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
5 TROUBLESHOOTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

COPYRIGHT © 2004 VICTOR COMPANY OF JAPAN, LIMITED No.XA020


2004/4
SPECIFICATION
GENERAL
Power requirement AC 220 V - 240 Vd, 50 Hz/60 Hz
Power consumption Power on : 33 W
Power off : 17.6 W
Temperature Operating : 5°C to 40°C
Storage : -20°C to 60°C
Operating position Horizontal only
Dimensions (W × H × D) 435 mm × 70 mm × 346 mm
Weight 4.5 kg
VIDEO/AUDIO
Recordable disc DVD-RAM 12 cm : (4.7 GB/9.4 GB)
DVD-RAM 8 cm : (1.4 GB/2.8 GB)
DVD-R 12 cm:( 4.7 GB, 8 cm: 1.4 GB for General Ver. 2.0)
DVD-RW 4.7 GB for Ver. 1.0/1.1
Recording format DVD-RAM DVD Video Recording format
DVD-R DVD-Video format
DVD-RW DVD-Video format, DVD Video Recording format
Recording time Maximum 8 hours (with 4.7 GB disc)
(XP) : Approx. 1 hour, (SP) : Approx. 2 hours, (LP) : Approx. 4 hours, (EP) : Approx. 6 hours, (FR) :
Approx. 1 hour - 8 hours
Playable disc DVD-RAM 12 cm : (4.7 GB/9.4 GB)
DVD-RAM 8 cm : (1.4 GB/2.8 GB)
DVD-R 12 cm:( 4.7 GB, 8 cm: 1.4 GB for General Ver. 2.0)
DVD VIDEO, DVD-RW 4.7 GB
Music CD (CD-DA)
Video CD
CD-R/RW (CD-DA, Video CD/SVCD formatted discs)
Audio recording system Dolby Digital (2 ch)
Linear PCM (XP mode only)
Video recording compression system MPEG2 (CBR/VBR)
Input/Output
S-video input Y : 0.8 - 1.2 Vp-p, 75 Ω
C : 0.2 - 0.4 Vp-p, 75 Ω
S-video output Y : 1.0 Vp-p, 75 Ω
C : 0.3 Vp-p, 75 Ω
Video input 0.5 - 2.0 Vp-p, 75 Ω (pin jack)
Video output 1.0 Vp-p, 75 Ω (pin jack)
Audio input -8 dB, 50 kΩ (pin jack) Corresponding to mono (left)
Audio output -8 dB, 1 kΩ (pin jack)
i.Link 4-pin for DV input
Component video output Y : 1.0 Vp-p, 75 Ω
PB/PR : 0.7 Vp-p, 75 Ω
Corresponding to copy protection
Optical -18 dBm, 660 nm
Coaxial 0.5Vp-p,75ohms Corresponding to Dolby Digital and DTS Digital Surround
Bit stream
Selectable in digital audio output setting menu
TUNER/TIMER
Signal system PAL-type colour signal and CCIR monochrome signal, 625 lines 50 fields
TV channel storage capacity 99 positions (+AUX position)
Tuning system Frequency synthesized tuner
Channel coverage VHF 47 MHz - 89 MHz/104 MHz - 300 MHz/302MHz-470MHz
UHF 470 MHz - 862 MHz
Memory backup time Approx. 60 min.
ACCESSORIES
Provided accessories RF cable, 21-pin SCART cable, Satellite Controller, Infrared remote control unit, "R6" battery × 2
Specifications shown are for SP mode unless otherwise specified.
E.& O.E. Design and specifications subject to change without notice.

1-2 (No.XA020)
1.5 Important for laser products

1.CLASS 1 LASER PRODUCT 5.CAUTION : If safety switches malfunction, the laser is able
2.DANGER : Invisible laser radiation when open and inter to function.
lock failed or defeated. Avoid direct exposure to beam. 6.CAUTION : Use of controls, adjustments or performance of
3.CAUTION : There are no serviceable parts inside the procedures other than those specified here in may result in
Laser Unit. Do not disassemble the Laser Unit. Replace hazardous radiation exposure.
the complete Laser Unit if it malfunctions.
4.CAUTION : The CD,MD and DVD player uses invisible Please use enough caution not to
!
laser radiation and is equipped with safety switches which see the beam directly or touch it
prevent emission of radiation when the drawer is open and in case of an adjustment or operation
the safety interlocks have failed or are defeated. It is check.
dangerous to defeat the safety switches.

REPRODUCTION AND POSITION OF LABEL and PRINT

WARNING LABEL and PRINT

On mechaism assembly

1-4 (No.XA020)
SECTION 3
DISASSEMBLY
3.1 Main body section
3.1.1 Remove the top cover (See figure 1)
(1) Remove the four screws A attaching the top cover on both B
sides of the main body.
(2) Remove the five screws B attaching the top cover on the
TOP COVER
back of the main body.
(3) Raise the both sides and lower part of the rear of the top B
cover, with opening them slightly in an outward direction.
Ax2 B
And the top cover will be removed.

B
Ax2

B
Fig.1

3.1.2 Remove the front panel assembly (See figure 2, figure 3, and figure 4)
• Prior to performing the following procedure, remove the top
Hook a
cover.
• There is no need to remove the mechanism assembly.
(1) Disconnect the card wires from connector CN3001,
CN3002, CN4001 on the main board. Front panel
(2) Hooks a and b are removed respectively, and the front assembly
panel assembly is removed.
NOTE:
In case of attach a front panel assembly, please let a
card wire pass in the hole in the front part of a chassis,
respectively, and connect.
CN4001 CN3002 CN3001 Hook b

Hook a
Fig.3
Chassis of front part

Main board
Fig.2

Card wire Front panel Card wire Card wire


assembly
Fig.4

1-6 (No.XA020)
3.1.3 Remove the mechanism assembly (See figure 5)
Mechanism assembly
• Prior to performing the following procedure, remove the top
Module board C C
cover.
• There is no need to remove the front panel assembly.
(1) Disconnect the socket wire from connector CN5303 on the
power supply board.
(2) Disconnect the card wire from connector CN2201 on the
module board.
(3) Remove the four screws C attaching the mechanism as-
sembly.

CN2201 C C CN5303
Fig.5
3.1.4 Remove the module board (See figure 6, figure 7)
• Prior to performing the following procedure, remove the top DV terminal F E
cover. board
(1) Disconnect the card wire from connector CN2201 on the
module board.
(2) Remove the four screws D and E attaching the module
board.
(3) Remove the one screw F attaching the DV terminal board.
(4) Lift the module board up, and remove it. Then, the module
board is removed from the connectors CN4101, CN4102
on the main board. In attaching the module board, insert
the connector on the module board in these connectors se- D
curely.

Module board E CN2201


Fig.6
Module board CN4102

CN4101 Main board


Fig.7

(No.XA020)1-7
3.1.5 Remove the power supply board (See figure 8)
CN5302 Fastener
• Prior to performing the following procedure, remove the top
cover.
(1) Disconnect the card wire from connector CN5301 on the Power supply
power supply board. board
(2) Disconnect the socket wire from connector CN5302, Fastener
CN5303, CN5305 on the power supply board.
CN5301
(3) Disconnect the power cord from connector CN5001 on the
power supply board. CN5303
(4) Remove the two screws G attaching the power supply Fastener
board.
(5) Four fasteners are removed.

CN5001
Power cord
CN5305 G
Fig.8

3.1.6 Remove the main board (See figure 9, figure 10)


• Prior to performing the following procedure, remove the top
CN4001 CN3002 H CN3001 CN5302
cover, mechanism assembly, module board.
(1) Disconnect the card wire from connector CN3001,
CN3002, CN4001, CN5101, CN7301 on the main board
(2) Disconnect the socket wire from connector CN5302 on the
power supply board.
(3) Remove the two screws H attaching the main board.
(4) Remove the seven screws I attaching the rear panel with
CN5101
main board.

H CN7301 Power supply board


Main board
Fig.9
Rear panel

I
Fig.10

1-8 (No.XA020)
SECTION 4
ADJUSTMENT
4.1 Timer clock adjustment (for only ver.E)
If an error comes to arise for a clock, the following procedure will adjust.
Signal (A1) No signal
Mode (B) EE
Equipment (C) Frequency counter
Measuring point (D1) IC3001 pin 61
(D2) IC3001 pin 17
(D3) C3026 + and -
Adjustment part (F) C3025 (TIMER CLOCK)
Specified value (G1) 1024.008 ±0.001 Hz
(976.5549 ±0.0010 usec)

(1) Connect the frequency counter to the measuring point (D1).


(2) Connect the short wire between the short point (D2) and Vcc (5V).
(3) Short the leads of capacitor (D3) once in order to reset the microprocessor of the system controller.
(4) Disconnect the short wire between the short point (D2) and Vcc then connect it again.
(5) Adjust the Adjustment part (F) so that the output frequency becomes the specified value (G).

(No.XA020)1-9
SECTION 5
TROUBLESHOOTING
5.1 JIG Mode
The following remote control units are required to set and cancel JIG mode.
For setting : a remote control unit attached to product.
For cancellation : JIG remote control unit (part number : PTU94023B)

Remote control unit


JIG remote control unit
attached to product
CABLE/DBS
TV DVD

TV TV/ STANDBY/ON
MUTING VIDEO TV/CBL/DBS DVD

ABC DEF TV VOLUME

GHI

PQRS
JKL

TUV
MNO

WXYZ CH
JIG remote control unit
DBS

CANCEL AUX MEMO/MARK


[Data transmission] Custom code
VCR Plus+ PROG/CHECK REC LINK

TOP MENU
TIMER

NAVIGATION
Set the data code, 43:A Code
ENTER

MENU RETURN
and then press the 53:B Code
PREVIOUS

SLOW PLAY/SELECT
NEXT

SLOW

" " 3 button. Initial mode


REC STOP/CLEAR

REC MODE LIVE CHECK


PAUSE 6F:C Code
OPEN/
SET UP DISPLAY ON SCREEN CLOSE
7F:D Code
AUDIO SUBTITLE ANGLE
PROGRESSIVE
SCAN

Data code

When the main body is set to JIG mode and when the main body is under JIG mode, the remote control unit attached to product op-
erates only in "Remote Control Code 1". Since main body is in "Remote Control Code 3" when it is shipped and just after its batteries
are changed, "Remote Control Code 3" needs to be changed to "Remote Control Code 1."

< Changing Remote Control Code >


(1) Switch TV/CABLE/DBS/DVD Switch to "DVD"
(2) Press the numeric button "1" of the remote control unit while pressing the "SET UP" button of the remote control unit. Then,
press the "ENTER" button, and then release the "SET UP" button.
(3) Press the "PLAY" button of the main body for five seconds or longer while the main body is in stand-by mode, and a current
remote control code of the main body is displayed in FL indicator of the main body.
(4) While keeping the state of (3), press the "STOP" button of the remote control unit toward the main body.
(5) When FL indicator displays "DVD1," it means that the Remote Control Code has been changed to "1."

*This product has remote control codes of 1, 2, 3, and 4.


*The remote control codes "DVD 1, 2, 3, and 4" of product are the same as the remote control codes
"A, B, C, and D" of video cassette recorders manufactured in JVC.

CABLE/DBS
TV DVD
(1)
TV TV/ STANDBY/ON
MUTING VIDEO TV/CBL/DBS DVD "(2) a-c" shows the order of pressing the buttons.
ABC DEF TV VOLUME

GHI JKL MNO


(2)b
PQRS TUV WXYZ CH

DBS

CANCEL AUX MEMO/MARK

VCR Plus+ PROG/CHECK REC LINK TIMER (3),(5) (3)


TOP MENU NAVIGATION

ENTER
(2)c
MENU RETURN

PREVIOUS NEXT

SLOW PLAY/SELECT SLOW

(4)
REC STOP/CLEAR PAUSE

REC MODE LIVE CHECK

OPEN/
SET UP DISPLAY ON SCREEN CLOSE REC MODE

(2)a
SAT

DVD 1
STANDBY/ON PULL - OPEN

F1 DV DV IN
PROGRESSIVE
AUDIO SUBTITLE ANGLE SCAN

S-VIDEO VIDEO L(MONO)-AUDIO-R

1-10 (No.XA020)
5.1.1 Setting JIG mode
To display SYSTEM INFO or to upgrade firmware, the main body needs to be set to JIG mode.
(1) Turn the main body ON.
(2) Press the buttons of the remote control unit attached to product in the following order : "SET UP" → "2" → "8" → "ENTER"
(3) When a colon ":" between "hour" and "minute" of a clock in FL indicator blink, it means that the main body has been set to JIG
mode properly.
[ Example ]
Not in JIG mode In JIG mode
15 : 07 15 07

A colon blinks.

(4) Turn the main body OFF, and then turn it ON again.
*Once the main body is set to JIG mode, the JIG mode cannot be cancelled even if the power cord is pulled out from the wall
socket.

CABLE/DBS
TV DVD

TV TV/ STANDBY/ON
MUTING VIDEO TV/CBL/DBS DVD "(2) a-d" shows the order of pressing the buttons.
ABC DEF TV VOLUME

GHI JKL MNO


(2)b
PQRS TUV WXYZ CH

DBS
(2)c
CANCEL AUX MEMO/MARK

VCR Plus+ PROG/CHECK REC LINK TIMER (3)


TOP MENU NAVIGATION (1),(4)
ENTER
(2)d
MENU RETURN

PREVIOUS NEXT

SLOW PLAY/SELECT SLOW

REC STOP/CLEAR PAUSE

REC MODE LIVE CHECK

OPEN/

(2)a
SET UP DISPLAY ON SCREEN CLOSE SAT REC MODE

15:07
STANDBY/ON PULL - OPEN

F1 DV DV IN
PROGRESSIVE
AUDIO SUBTITLE ANGLE SCAN

S-VIDEO VIDEO L(MONO)-AUDIO-R

5.1.2 Canceling JIG mode


(1) Transmit "43-9D" to the main body by using JIG remote control unit.
(2) A colon ":" between "hour" and "minute" of a clock in FL indicator light.
(3) Turn the main body OFF, and then turn it ON again.

NOTE:
After repair work, be sure to cancel JIG mode. Before returning product to a user, confirm that a colon ":" between "hour" and
"minute" of a clock in FL indicator light.

(No.XA020)1-11
5.1.3 Displaying SYSTEM INFO
SYSTEM INFO contains information on firmware version of the main body and the mechanism drive, and an initialize execution menu.
(1) Set the main body to JIG mode.
(2) Transmit "43-8B" to the main body by using JIG remote control unit.
(3) SYSTEM INFO menu is displayed in the television screen.
(4) To move cursor in SYSTEM INFO, use the "", "", "", and "" buttons of a remote control unit attached to product.

< VERSION >


SYSTEM INFO
VERSION INITIALIZE INFORMATION

CPRM Key Downl oad Do n e

C-Ware / A-Ware PROD98-2 / JV C _ 4 3


Version of firmware
JVRI / Host 0076 / V 0 1 0 8 This part is updated after the firmware of the
main body is upgraded.
1394 / OSD 0053E / M T E N 0 3

Anal og / BE-R / FE-R 003 / 2 / 2 System controller version


/ Region code (Backend) / Region code (Frontend)
ENTER
EXIT
SELECT WITH [CURSORS]
SELECT THEN PRESS [ENTER]
SET UP

NOTE :
Items other than the ones described above are not used in service work.

(5) To quit the SYSTEM INFO menu, transmit "43-8B" to the main body by using JIG remote control unit.
(6) Cancel JIG mode.

5.1.4 Upgrading firmware of the main body


• Firmware upgrade disk supports CD-R media.
(1) Download a compressed file of the latest firmware in "optical disc" page in JS-NET.
(2) Decompress the file, and a file "fwupdate.bin" is generated.
(3) Write "fwupdate.bin" in CD-R in ISO9660 format.(Don’t use Packet Write software. Write in UDF format.)
(4) Set the main body to JIG mode.
(5) Transmit "43-70" to the main body by using JIG remote control unit.
(6) "UPDATE" appears in FL indicator. Load disk for upgrade on the tray, and close the tray.
(7) Upgrade processing is started automatically.
(8) Then, "FW UPDATE" appears in FL indicator. It takes approx. 6 minutes at maximum to upgrade firmware.
(9) The tray is ejected. Then, take out the disk and close the tray.
(10) Turn the main body OFF, and pull out the power cord from the wall socket. Then, plug the power cord into the wall socket.
(11) "LOADING" of FL indicator disappears. Then, turn the main body ON.
(12) Display the SYSTEM INFO menu, and check the version of the firmware.
(13) Cancel JIG mode.
ATTENTION :
Firmware may sometimes not be upgraded successfully.
If firmware is not upgraded successfully, the tray opens, and "ERROR" appears in FL indicator.
If firmware is upgraded successfully, the tray opens, and "OPEN" appears in FL indicator.
If the power cord is pulled out from the wall socket while "ERROR" appears, data in the flash memory is destroyed and the main
body cannot start: the flash memory needs to be replaced.
After upgrading procedure, pay enough attention to FL indicator when the tray opens.

When "ERROR" appears, upgrade firmware again in the following way to restore the firmware.
(1) Transmit "43-70" to the main body by using JIG remote control unit while the tray opens.
(2) When "UPDATE" appears in FL indicator, close the tray and make the main body read the disk. Upgrading starts.
(3) After (2), perform upgrading procedure (4) - (10) of 5.1.4 Upgrading firmware of the main body above.

1-12 (No.XA020)
5.2 The setting method of a region code
A region code should be set after a DVD recorder mechanism unit is replaced.
While a DVD recorder mechanism unit is in a warehouse as a stock, a region code of the drive unit is not determined.
Only replacement of a DVD recorder mechanism unit may cause abnormal playback of Disc.
Set a region code of a DVD recorder mechanism unit in the following procedure.
(1) Replace a DVD recorder mechanism unit.
(2) Turn POWER switch of the unit ON.
(3) Set the main body to JIG mode.
(4) Insert a DVD-RAM disc in the unit to make the unit read the DVD-RAM disc.(The DVD-RAM disk used in this procedure is not a
disk for upgrade. If it is a DVD-RAM disk, it is good anything.)
(5) Send "43-F2" to the unit by using JIG remote control unit.
(6) "REGION 2" is displayed on FL display.
(7) Set the unit to STANDBY.
(8) Turn the POWER switch ON.
(9) To cancel JIG MODE, send "43-9D" to the unit by using JIG remote control unit.
(10) Colon is displayed on a clock on FL display.
(11) Setting is completed in the procedure above.
5.3 Taking out a disc
5.3.1 Method 1
(1) AC Plug is pulled out at once and inserted again.
(2) It is displayed on FL display as "LOADING", and while it blinks, pushing the EJECT button of a main body is continued.
(3) After a while, a tray opens (About 20 seconds).
(4) A disk is removed, the EJECT button of a main body is pushed, and a tray is made to close.
(5) The "LOADING" blink display of FL display disappears and it will be in a standby state.
(6) If the POWER button is pushed, it will usually be operating.
5.3.2 Method 2
When a disk is not able to be taken out by operation of "Method 1", a front door is opened manually, and the EJECT button in the lower
right of a DVD recorder mechanism is pushed directly.
5.3.3 Method 3
A Disc can be taken out manually even when the main body is turned off.
(1) Open the front door.
(2) Pass a thin wire through a hole in the DVD recorder mechanism unit.
(3) The disc tray comes out slightly. Take out the disc tray manually.
DVD recorder mechanism unit

Front door Hole


Disc tray Direct EJECT button
5.4 The exchange method of a tray fitting
When DVD recorder mechanism unit is exchanged, please transplant a tray fitting from an old drive, or change for a new tray fitting.
A tray is pulled out manually, as shown in a figure, it carries out, and a tray fitting is removed.
Tray DVD recorder mechanism unit

Tray fitting

(No.XA020)1-13
VICTOR COMPANY OF JAPAN, LIMITED
AV & MULTIMEDIA COMPANY OPTICAL DISC CATEGORY 1644, Shimotsuruma, Yamato, Kanagawa 242-8514, Japan

(No.XA020)
Printed in Japan
WPC
SCHEMATIC DIAGRAMS
DVD VIDEO RECORDER

DR-M10SEF, DR-M10SEK
DR-M10SE, DR-M10SER
DR-M10BE
CD-ROM No.SML200404

Area Suffix
EK ------------------------ U.K.
EF --------------------- France
ER ---- Russian Federation
E ------- Continental Europe
Northern Europe

CABLE/DBS
TV DVD

TV TV/ STANDBY/ON
MUTING VIDEO TV/CBL/DBS DVD

ABC DEF TV VOLUME

GHI JKL MNO

PQRS TUV WXYZ CH

DBS

CANCEL AUX MEMO/MARK

VCR Plus+ PROG/CHECK REC LINK TIMER

TOP MENU NAVIGATION

ENTER

MENU RETURN

PREVIOUS NEXT

SLOW PLAY/SELECT SLOW

REC STOP/CLEAR PAUSE

REC MODE LIVE CHECK

OPEN/
SET UP DISPLAY ON SCREEN CLOSE SAT REC MODE

STANDBY/ON PULL - OPEN

F1 DV DV IN
PROGRESSIVE
AUDIO SUBTITLE ANGLE SCAN

S-VIDEO VIDEO L(MONO)-AUDIO-R

Since the whole mechanism assembly unit is replaced, the DVD recorder
mechanism of this unit need not be adjusted.

Contents
Safety precaution ------------------------ 2-2
Wiring diagram --------------------------- 2-3
Block diagrams --------------------------- 2-4
Standard schematic diagrams -------- 2-7
Printed circuit boards -------------------- 2-21

No.XA020SCH
COPYRIGHT 2004 VICTOR COMPANY OF JAPAN, LIMITED.
2004/04
Wiring diagram

CN1901
CN6901

CN4102
BB[AL5V]

MOD_B[AL5V]

TU[30V]
LOCK[L]
VIDEO_IN
AUDIO_IN

MB[SW5V]

VIDEO_OUT
AUDIO_OUT
SIF_OUT
AFT
MOD_SCL

SCL
RF_AGC
MOD_SDA

SDA

SW2
SW1
AS

NC
CONV.CTL[H]

TU[30V]
[RF_AGC]
VIDEO_IN
MOD_B[SW5V]
AUDIO_IN

NC[OPEN]
MB[SW5V]

VIDEO_OUT
AUDIO_OUT

AFT
SCL
SDA
AS
CH_SW

RSTSTA
GND
HD_AT[7]
HD_AT[8]
HD_AT[6]
HD_AT[9]
HD_AT[5]
HD_AT[10]
HD_AT[4]
HD_AT[11]
HD_AT[3]
HD_AT[12]
HD_AT[2]
HD_AT[13]
HD_AT[1]
HA_AT[14]
HD_AT[0]
HD_AT[15]
GND
KEY
DMARQ
GND CN4101

DIOW
GND
DIOR
GND
IORDY
CAB_SEL
DMACK
GND
INI_ATA
IOCSI6-
ATA_A1
PDIAG-
ATA_A0
ATA_A2
CS1FX
CS3FX
DASP-
GND

CN7301 CN7312
S/RCA OUT

CN2101

RSTSTA
GND
HD_AT[7]
HD_AT[8]
HD_AT[6]
HD_AT[9]
HD_AT[5]
HD_AT[10]
HD_AT[4]
HD_AT[11]
HD_AT[3]
HD_AT[12]
HD_AT[2]
HD_AT[13]
CN3002

HD_AT[1]
HA_AT[14]
HD_AT[0]
HD_AT[15]
GND
KEY
DMARQ
GND
DIOW
CN7101

GND
DIOR
GND
IORDY
CAB_SEL
DMACK
GND
INI_ATA
IOCSI6-
ATA_A1
PDIAG-
ATA_A0
ATA_A2
CS1FX
CS3FX
DASP-
GND
CN5102

CN1202

CN4104 CN5305

FAN8V
GND

CN1401 CN5306

GND
GND
D3.3V
D2.5V CN5001

D1.8V BLU
D1.8V BRN
JLIP_TX
JLIP_RX

D3.3V
CN1402

GND

(No.XA020SCH) 2-3
Block diagrams
DIGITAL 0 2

J4112

CN1801

CN4104
IEEE1394 TPA+ TPA- TPB+ TPB- IEEE1394
controller terminal
PHY_RESET[L] CIN VYIN SYNCDET CROUT CBOUT
PHY_LREQ PHY_CLK
IC1801
YVOUT COUT RYOUT RCOUT
PHY_CNA PHY_CTL[0],[1] Video

CN1001
PHY_DATA[0-7] PHY_LPS TO CN4101 controller
PHY_LINK_ON SHEET 10 IC1001
IEEE1394 section (SHEET 2) AO_FSYNC AO_D[0] DAC_RST[L]
AO_SCLK A_DAC_CS AO_MCLKO AP A0 to A9
DAC_SCL DAC_Y_OUT DAC_SDA DAC_CVBS_OUT
DAC_SY_OUT UDQM WE
480I[H] CAS RAS
DAC_SC_OUT
DQ0 to DQ15
SDRAM_DQ16 to 31 RA1613 to DDR_DQ16 to 31
RA1616 16M SDRAM
IC1002
VI_D2 to 9 VIDEO_RST[L] VO_D1 to 15 SPI_MOSI
DDR SDRAM DDR SDRAM
SDRAM_DQ0 to 15 RA1609 to DDR_DQ0 to 15 VIDEO_27M VIDEO_CS VIDEO_MUTE[M] SPI_CLK VIDEO_RXD
IC1601 IC1602
RA1612

SYS_RESET[L] K_BUS_CLK K_BUS_REQ K_BUS_IN K_BUS_OUT

CN1002
DDR_BA1,2
SDRAM_A0 to 15 RA1625 to DDR_A0 to 12 TO CN4102 AO_IEC958 AI_D[0] A_MUTE2[H] DAC_RST[L]
SDRAM_CKE RA1628 DDR_CKE SHEET 10
SDRAM_RAS_L DDR_RAS_L
SDRAM_CAS_L DDR_CAS_L
SDRAM_WE_L R1601 to DDR_WE_L Video signal control section (SHEET 5)
R1604

SDRAM_DQM0 to 3 DDR_DQM0 to 3
SDRAM_DQS0 to 3 R1653 to DDR_DQS0 to 3
R1660

SDRAM_CLK0,1 DDR_CLK0,1
SDRAM_CLK_L0,1 R1613 to DDR_CLK_L0,1
R1616
ATA_DATA0 to 15 RSTATA
DDR SDRAM section (SHEET 3) 20bit FET
P_CTL[H] ATA_RESET HD_AT0 to 15 ATA_A0 to 2
Bas switch
IC2201

CN2201
ATA_DMARQ
ATA_IORDY ATA_INTRQ TO
ATA_DMAACK[L] ATA_ADD0 to 4 DMARQ IORDY CS1FX CS3FX DVD
ATA_DIOW[L] ATA_DIOR[L] FET Bas switch DIOW DIOR DMACK INT_ATA Recorder unit
IC2202

ATAPI Interface section (SHEET 6)


ATA_DMAACK[L] ATA_INTRQ ATA_ADD1 to 4
ATA_DIOR[L] ATA_DIOW[L] ATA_IORDY
ATA_DAT0 to 15 ATA_RESET ATA_DMARQ
Media
processor
IC1401

SYS_RESET[L] VIDEO_RXD MADD1 to 22


IC1406 K_BUS_CLK K_BUS_REQ K_BUS_IN/OUT 65Mbit Flash
IC1407 RD/WR[L] E5_RESET[L] OE[L]/LDS[L] CS[0] IC1201

VIDEO_RST[L] SPI_MOSI SPI_CLK VIDEO_CS LH_AR6 to 21

ALE MADD6 to 21 IC1202


RD/WR[L] ALE OE[L]/LDS[L] MADD1 to 22 CS[0] F_PROT[H] E5_RESET[L]
IC1203

FLASH-ROM section(SHEET 7)
Media processor (SHEET 4)

2-4 (No.XA020SCH)
MAIN 0 3

Audio signal control section (SHEET 8) J7308 J7307


L-1 SCART Terminal
TO SHEET 11 S-VIDEO AUDIO OUT
AUDIO_OUT1[L/R] J7301

Muting A_MUTE2[H] RAPID_SW BIAS/RGB_CTL Q7310 to


DEC_OUT[L/R] Q8201,Q8202 Q7312
LINE_OUT[L/R] IC8301 IC8202 4_3[H] P50_I/O AV_YC_IN[H] TV[H] FW7301
TO SHEET 11 IC8302 DAC_SDA
AOUTL
AOUTR DAC_SCL CN7301
AUDIO_IN1[L/R] A_DAC_CS AV1_L SWITCH
AUDIO_IN2[L/R] DAC_RST[L] IC7302
2chDA converter

AUDIO_OUT1[L/R]
AO_D[0] SCR_ID LINE_OUT[L/R]
IC8201 AUDIO_IN1[L/R]

V_OUT
24bit AV2_H RGB_TH[H]
F_AUDIO[L/R] A/D AO_SCLK AO_FSYNC AO_MCLKO SWITCH
combatr IC7303 to IC7306
AI_D[0]
IC8001
VMUTE[L]
R R
TU_AUDIO[L/R] J8401 G
AV1_L G

A_MUTE1[H]
AO_IEC958 Optical digital B B TO
AV2_H SHEET 8
OUT V_OUT
J8501
ACD_RST[L] CROUT CBOUT
IC8501 COAXIAL OUT COUT YVOUT
I2C_CLK2 I2C_DATA2
Video driver
J7309
TO SHEET 13 480I[L] RCOUT RYOUT IC7301
COMPONENT
REAR1_C_IN VIDEO OUT

REAR1_YV_IN
REAR1_C_IN REAR 1_YV_IN
F_AUDIO[L/R] REAR2_C_IN REAR 2_YV_IN
REAR2_C_IN DEC_OUT[L/R] AUDIO_IN2[L/R]
CN4001

TO CN7102 Video controller REAR2_Y_IN


IC4001 YTODIGI CTODIGI Input/output terminal section
SHEET 14
FRONT_VIDEO (SHEET 11)
J7302
FRONT_Y_IN
FRONT_C_IN I2C_DATA_A/V I2C_CLK_A/V L-2 SCART Terminal

SYNC_DET
I2C_CLK2 I2C_DATA2 SCR_ID 4_3[H] RGB_TH[H] AV1_YC_IN[H] BIAS/RGB_CTL AV1_L AV2_H
IC4201 RAPID_SW V_MUTE[L] TV[H] P50_I/O

SECAM_DET[H] SEPA_IN[H]
IC4301 P.MUTE[H] K_BUS_OUT SYS_RESET[L] K_BUS_IN P_CTL[H] K_BUS_CLK FAN_CTL
K_BUS_REQ SYNC_DET VD R.PAUSE SAT_CTL P.SAVE
SYNC+BGP.IN
SECAM
HD_FROM_PDC IC4304 ADC_RST[L] A_MUTE[H] AV1_L AV2_H I2C_CLK2 I2C_DATA2
System controller
TU_VIDEO IC3001
SYNC_DET I2C_DATA_A/V I2C_CLK_A/V
SECAM_DET[H] I2C_DATA2 I2C_CLK2 SEPA_IN[H]
Audio / video signal input control section (SHEET 9)
STB RC_IN S_CLK LED_OUT
I2C_DATA2 I2C_CLK2 TU_DATA TU_CLK S_DATA_TOSYS
TU_V_MUTE[H] SW1 SW2 AFC RF_AGC S_DATA_FRSYS
RCOUT COUT 480I[H] RYOUT YVOUT CBOUT CROUT
System controller section(SHEET 12)
CN4101

AO_FSYNC AO_D[0] DAC_RST[L] AO_SCLK A_DAC_CS AO_MCLKO CN3001 CN3002


TO CN1001 DAC_SCL DAC_SDA
SHEET 5 TO CN7001 TO CN7101
SHEET 14 SHEET 14
YTODIGI CTODIGI
AI_D[0] A_MUTE2[H] AO_IEC958
CN4102

TO CN1002 TU_V_MUTE[H] TU_VIDEO


K_BUS_REQ K_BUS_OUT K_BUS_CLK K_BUS_IN SYS_RESET[L] Muting
SHEET 5 Q6031
P_MUTE[H] P_CTL[H] SYNC_DET VD VIDEO_OUT
Tuner
CN5101

TO CN5301 TU6001 TV Multiplex TU_AUDIO[L/R]


FAN_CTL P.CTL[H] P.SAVE TO SHEET 8
SHEET 1 sound processor
TU_DATA AFC RF_AGC
IC6701
TU_CLK SW1 SW2
J4109
R.PAUSE I2C_DATA2 I2C_CLK2
AV COMPULINK
Tuner section(SHEET 13)
SAT_CTL
SAT CONTROL
Signal input/output terminal section(SHEET 10)

(No.XA020SCH) 2-5
SW.REG 0 1

D2.5V

CN5302
2.5V REG.
IC5305 TO CN5102
AC-DC SHEET 10
AC IN D5001 D1.8V
1.8V REG.
P.SAVE[L]
IC5302

CN5301
Switching TO CN5101
3.3V REG. V3.3V
regurator Power SHEET 10
IC5303
IC5101 transformer D5.0V
T5001
5V REG.
IC5304

3.3V REG.
IC5308

1.8V REG.
IC5307 DV3.3V

CN5304
DC1.8V
TO DVD Recorder unit
DC5V DV12V

CN5305
FAN
TO Fan assembly
Power supply section (SHEET 1)

SW/DISPLAY 2 8

KEY1,KEY2
FL Display driver
IC7001

1G to 12G Operation switch


S1 to S16 S7001

FL Display
DI7001 STB S_DATA_FRSYS
S_DATA_TOSYS S_CLK
CN7001

LIGHTING Remote controller RC-IN TO CN3001


D7043 IC7002
S12 to S15
BLUE_LED

FL Display section (SHEET 14)

OPERATE 2 7
CN7101

S12 to S15 KEY1,KEY2 Operation switch


TO CN3002 S7132,S7134,S7135
S7113 to S7115

J7001
Front S-video IN
FRONT C/Y
FRONT VIDEO J7002
CN7102

TO CN4001
SHEET 9 Front A/V IN
F.AUDIO[L/R]

Operation switch section (SHEET 14)

2-6 (No.XA020SCH)
Standard schematic diagrams
Power supply section
## CN5301
B5501
CP DC3.9[+]
D5201 CP5301 R5310 DC3.9[-]
10ERB20 1.5A /125 Q5310 8.2
ERA18-02 2SD2144S/UV/ -29V
C5201 2SC3576
220 AL-12V
/6.3
Parts are safety assurance parts. FR
FAN_CTL
AL12V
When replacing those parts make D5207 R5314 P.CTL[H]
47
# sure to use the specified one. AU01Z
ERA18-02 1/4W SW12V
F5001 # T5001 1SR153-400 C5206 R5327 R5328 R5317
CN5001 /250 LF5002 QQS0263-001 10ERB20 18 /50 680 820 2.2k D5V
1F4G
D5306 D5307 SW5V
D5209
RK34
1SS133
1SS270A
MTZJ27C
RD27ES/B3/ SW5V TO CN5101
R5103 C5102 L5205
AL5.3V SHEET 10
68k 4700p 33u P.SAVE[L]
2W /1k Q5308 R5318 IC5304
2SD1858/QR/ 1k Q5302 MM1565AF C5320 GND
DTC114EKA 470p
UN2211 /50 GND
RT1N141C Cont Cn GND
# VA5001 C5001 # C5002 D5001 K5102 Q5301
QAF0039-431 0.068 0.022 D3SBA60 QQR0678-001 DTA114EKA GND V3.3V
QAF0024-431 /250 /250 GBJ4J # QQR0621-001 UN2111 Sub
QAF0023-431 C5101 R5332 RT1P141C NC BT2
QAF0055-431 C5003 100p D5304 470 C5317 D5302
D5102 /1k C5207 C5307 MTZJ5.6C 100 MTZJ12B C5312 Vin Vout 48V
AU01 1500 /10 100/10 RD5.6ES/B3/ /10 RD12ES/B2/ 0.01 /50
IC5101 ERA18-02 C5319 C5321 GND
STR-G6653-F9 R5101 1SR153-400 1 /10 22 /50
68k 10ERB40 GND
2W 1F4G D5208 L5204 # D5305
RK34 33u GND
D5101 ## B5502 # D5313 # D5312
AU01 1S4 1A3G 17V
OCP/ D5103 ERA18-02 D5210 AW04 10EDB20 # IC5308 # # IC5307 #
FB S D Vcc GND AU01Z 1SR153-400 RK34 SBO40 ERA15-02 MM1663DH C5325 MM1561JF C5331
ERA18-02 10ERB40 C5208 C5308 470p 470p
1SR153-400 1F4G 2200 /10 100 /10 /50 /50
10ERB20 R5329 ## Cont Cn SW Cn
1F4G 10k B5505
Q5315 GND GND GND
2SA1585S/QR/ Sub
R5105 GND NC NC
68
R5330 Vin Vout Vin Vout
C5104 470
470p
/1k C5103
27 /35 C5202 C5304 # # # #
1200 100 C5324 C5332 C5329 C5330
/10 /10 1 /10 22 /50 1 /10 22 /50
L5201
D5105 33u #
AU01Z IC5305
ERA18-02 MM1662GH CN5304
1SR153-400 D5202 IC5302 # C5318
10ERB20 RK34 D5311 PQ5EV3 D5318 470p /50 DV12V
R5106 1F4G 1S4 1A3G
AW04 Cont Cn GND
3.9k D5106
AU01Z R5102 SBO40 10EDB20
ERA15-02 GND GND GND
TO DVD-RAM
ERA18-02 1.2k
D5104
1SS133
1SR153-400
10ERB20
##
B5301 GND NC DV5V DRIVE
1SS270A 1F4G D5204 I O G ref SW
RK34 Vin Vout DV3.3V for except europe
C5106 L5202 C5303 C5310 DC1.8V
0.01 /50 33u 1 /10 22 /50
GND
R5107 PC5101 D5203 D5310 D5309 D5308
680 PC123Y22FZ RK34 RK34 RK34 RK34
LTV-817M/BC/ R5104
R5108 1k
0.33 C5107 R5319
C5105 1W 220p 3.0k
470p /50 C5203 C5305
/50 2200 100 D5315
/10 /10 1A3G #
10EDB20
C5316 ERA15-02 CN5303
100
R5323 R5324 R5320 /10
1.2k 1k 4.7k DV12V TO DVD-RAM
GND
D5206 GND
DRIVE
AU01Z
ERA18-02
1SR153-400
R5321
47k
C5205
4.7 DV5V for only europe
10ERB20 /100 ##
1F4G R5331 B5503 IC5303
10k # MM1563DF
B5304 R5308 B5303 C5314
390 Q5316 470p /50
2W 2SA1585S/QR/
Cont Cn CN5302
D5205 L5203 ## D5317 ## D5316 GND D1.8V
R5301 RK34 33u RL2Z RL2Z Sub
# 220 R5336 R5337 NC D1.8V
B5001 10k 470
# R5307 Vin Vout D1.8V
390
# C5204
2200
C5306
100
2W
Q5317 D2.5V TO CN5102
C5004 /16 /16 DTC114EKA
/250
D5314
UN2211
RT1N141C
C5313
1 /10 C5315 B5302 GND SHEET 10
1SS133 B5504 22 /50 D3.3V
R5302 1SS270A
4.7k Q5303 Q5304 ## GND
R5303 R5304 DTA114EKA DTC114EKA IC5306
UN2111 ## MM1563EF ## GND
MY

1.5k 6.8k RT1P141C UN2211 B5506 C5327


SG5001 RT1N141C 470p /50 GND
C5301 Cont Cn
MY

# # 0.15 /50 D5211


R5001 C5005 AU01Z GND
4.7M 100p ERA18-02 Sub
1/2W /250 C5302 R5305 1SR153-400 NC
0.033 /50 20k 10ERB20 Q5305
1F4G 2SD2144S/UV/ Vin Vout
IC5301 2SC3576 ##
TL431/A/ R5306 C5326
MM1431AT 3.9k L5206 1 /10
UTCTL431 33u ##
L5431 ## D5212 C5311
AU01Z 22 /50
# VA5003 ERA18-02
QAF0039-431 1SR153-400
QAF0024-431 10ERB20 R5333
QAF0023-431 1F4G 100
QAF0055-431 1/2W R5334 Q5313
10k 2SA1585S/QR/

D5301 C5209 C5309 D5303 C5322 C5323 CN5305


MTZJ15A 680 100 MTZJ11C 100 2.2
RD15ES/B1/ /16 /16 RD11ES/B3/ /16 /50 R5335
1k FAN
GND
TO FAN UNIT
## D5214 Q5314
AU01Z DTC114EKA
ERA18-02 UN2211
1SR153-400 ## ## RT1N141C
10ERB20 C5211 L5208
1F4G 180 33u
/25

SHEET 1

(No.XA020SCH) 2-7
IEEE1394 section

# B1802 B1801 D3.3V

OPEN

# #
# C1806 L1802 # L1801 C1804 C1803
10 /6.3 0.1 10 /6.3
OPEN 10u C1814
C1813 # OPEN
OPEN C1805
0.1 # R1820

10k
C1810

# C1809 12p

C1808 12p
OPEN

# K1801
# X1801
NAX0551-001X

1801_X0
#

1801_XI

0‘
NAX0666-001X SHORT

# C1807

# R1822
0.1
#
IC1801
TSB41AB2PAP

D3.3V

DGND
DGND

XO

NC
NC

AGND
AGND
DVDD
DVDD

AVDD
AVDD
XI

RESET
PLLGND
PLLGND
PLLVDD
PHY_RESET[L]
PHY_LREQ LREQ AGND
# R1801 0‘
PHY_CLK SYSCLK NC
# R1802 0‘
PHY_CNA CNA NC
TO SHEET 4 PHY_CTL[0] CTL0 NC
PHY_CTL[1] CTL1 NC
PHY_DATA[0-7] PHY_DATA[0]
PHY_DATA[0-7] D0 NC # R1819
PHY_DATA[1] 750
PHY_LPS D1 AVDD _0.5%
PHY_DATA[2]
PHY_LINK_ON D2 R1
PHY_DATA[3] #
GND D3 R0 CN1801
PHY_DATA[4] # R1818 # T1801 QGB2027L1-10X
D4 AGND 5.6k
PHY_DATA[5] _0.5% NQR0444-001X
D5 TPBIAS0
PHY_DATA[6] TPA0+ TPA+
D6 TPA0+
PHY_DATA[7] TPA0-
D7 TPA0-
TPB0+ TPA-
PD TPB0+
LPS TPB0- TO CN4104
TPB+
NC AGND SHEET 10

BRIDGE
C/LKON

TESTM

TEST0
DGND
DGND

AGND
DVDD
DVDD

AVDD
AVDD
CPS
PC0
PC1
PC2
ISO
TPB0- TPB-

56
56
56
56
# R1812

R1813
# R1814
270p # R1815
R1816
# R1805 0‘

0‘
# R1807

390k
10k

10k

#
0.1

0.1
TPBIAS0

5.1k
OPEN

1
1k

# C1812
10k
10k

OPEN
R1806

R1808

# R1809
# R1810
# C1811
##
10k

# C1801

# C1802
# R1817
R1823
0‘
##

R1811
# R1821
RA1801 RA1802
R1803
R1804

10k 10k
GND

SHEET 2

2-8 (No.XA020SCH)
DDR SDRAM section

SDRAM_DQ[0] SDRAM_DQ[0] DDR_DQ[0]


RA1601 SDRAM_DQ[1] SDRAM_DQ[1] RA1609 DDR_DQ[1]
100 SDRAM_DQ[2] SDRAM_DQ[2] 22 DDR_DQ[2]
SDRAM_DQ[3] SDRAM_DQ[3] DDR_DQ[3]
SDRAM_DQ[4] SDRAM_DQ[4] DDR_DQ[4]
RA1602 SDRAM_DQ[5] SDRAM_DQ[5] RA1610 DDR_DQ[5]
100 SDRAM_DQ[6] SDRAM_DQ[6] 22 DDR_DQ[6]
C1637
OPEN SDRAM_DQ[7] SDRAM_DQ[7] DDR_DQ[7]
SDRAM_DQ[8] SDRAM_DQ[8] DDR_DQ[8]
RA1603 SDRAM_DQ[9] SDRAM_DQ[9] RA1611 DDR_DQ[9]
C1638
0.1 100 SDRAM_DQ[10] SDRAM_DQ[10] 22 DDR_DQ[10]
SDRAM_DQ[11] SDRAM_DQ[11] DDR_DQ[11]
SDRAM_DQ[12] SDRAM_DQ[12] DDR_DQ[12]
RA1604 SDRAM_DQ[13] SDRAM_DQ[13] RA1612 DDR_DQ[13]
100 SDRAM_DQ[14] SDRAM_DQ[14] 22 DDR_DQ[14]
SDRAM_DQ[15] SDRAM_DQ[15] DDR_DQ[15]

DDR_DQ[0] DDR_DQ[16]
SDRAM_DQ[16] SDRAM_DQ[16] DDR_DQ[16] DDR_DQ[1] RA1617 DDR_DQ[17] RA1621
RA1605 SDRAM_DQ[17] SDRAM_DQ[17] RA1613 DDR_DQ[17] DDR_DQ[2] 100 DDR_DQ[18] 100
100 SDRAM_DQ[18] SDRAM_DQ[18] 22 DDR_DQ[18] DDR_DQ[3] DDR_DQ[19]
SDRAM_DQ[19] SDRAM_DQ[19] DDR_DQ[19] DDR_DQ[4] DDR_DQ[20]
SDRAM_DQ[20] SDRAM_DQ[20] DDR_DQ[20] DDR_DQ[5] RA1618 DDR_DQ[21] RA1622
RA1606 SDRAM_DQ[21] SDRAM_DQ[21] RA1614 DDR_DQ[21] DDR_DQ[6] 100 DDR_DQ[22] 100
100 SDRAM_DQ[22] SDRAM_DQ[22] 22 DDR_DQ[22] DDR_DQ[7] DDR_DQ[23]
C1639
OPEN SDRAM_DQ[23] SDRAM_DQ[23] DDR_DQ[23] DDR_DQ[8] DDR_DQ[24]
SDRAM_DQ[24] SDRAM_DQ[24] DDR_DQ[24] DDR_DQ[9] RA1619 DDR_DQ[25] RA1623
RA1607 SDRAM_DQ[25] SDRAM_DQ[25] RA1615 DDR_DQ[25] DDR_DQ[10] 100 DDR_DQ[26] 100
C1640
0.1 100 SDRAM_DQ[26] SDRAM_DQ[26] 22 DDR_DQ[26] DDR_DQ[11] DDR_DQ[27]
SDRAM_DQ[27] SDRAM_DQ[27] DDR_DQ[27] DDR_DQ[12] DDR_DQ[28]
SDRAM_DQ[28] SDRAM_DQ[28] DDR_DQ[28] DDR_DQ[13] RA1620 DDR_DQ[29] RA1624
RA1608 SDRAM_DQ[29] SDRAM_DQ[29] RA1616 DDR_DQ[29] DDR_DQ[14] 100 DDR_DQ[30] 100
100 SDRAM_DQ[30] SDRAM_DQ[30] 22 DDR_DQ[30] DDR_DQ[15] DDR_DQ[31]
SDRAM_DQ[31] SDRAM_DQ[31] DDR_DQ[31]

SSTL2_VDD

VTT C1641 C1643


OPEN OPEN

SDRAM_A[0] DDR_A[0] C1621 C1622 C1623 C1624 C1625


SDRAM_A[1] RA1625 DDR_A[1] C1642 0.1 0.1 0.1 0.1 0.1 C1644
0.1 0.1
SDRAM_A[2] 10 DDR_A[2]
SDRAM_A[3] DDR_A[3]
SDRAM_A[4] DDR_A[4] R1617 27 DDR_DQM[0] R1623 27 DDR_DQM[2]
SDRAM_A[5] RA1626 DDR_A[5] R1618 27 DDR_DQM[1] R1624 27 DDR_DQM[3]
SDRAM_A[6] 10 DDR_A[6] R1619 100 DDR_DQS[0] R1625 100 DDR_DQS[2]
SDRAM_A[7] DDR_A[7] R1620 100 DDR_DQS[1] R1626 100 DDR_DQS[3]
SDRAM_A[8] DDR_A[8] R1621 27 DDR_CLK[0] R1627 27 DDR_CLK[1]
SDRAM_A[9] RA1627 DDR_A[9] R1622 27 DDR_CLK_L[0] R1628 27 DDR_CLK_L[1]
SDRAM_A[10] 10 DDR_A[10]
SDRAM_A[11] DDR_A[11]

IC1701 SDRAM_A[12] DDR_A[12]


PQ015YZ01Z RA1628
SDRAM_A[14] 10 DDR_BA[0] C1649 IC1601 #1 C1651 IC1602 #2
OPEN OPEN
SDRAM_A[15] DDR_BA[1]
DDR_A[0] DDR_DQ[7] DDR_A[0] DDR_DQ[16]
A0 D0 A0 D0
K1702 C1650 DDR_A[1] DDR_DQ[6] DDR_A[1] DDR_DQ[17]
SHORT 0.1 A1 D1 A1 D1
SDRAM_A[17] R1642 10 DDR_CS[0] DDR_A[2] DDR_DQ[5] C1652 DDR_A[2] DDR_DQ[18]
A2 D2 0.1 A2 D2
DDR_A[3] DDR_DQ[4] DDR_A[3] DDR_DQ[19]
A3 D3 A3 D3
SDRAM_CKE R1601 10 DDR_CKE DDR_A[4] DDR_DQ[3] DDR_A[4] DDR_DQ[20]
R1702 A4 D4 A4 D4
R1701 1k SDRAM_RAS_L R1602 10 DDR_RAS_L DDR_A[5]
A5 D5
DDR_DQ[2] DDR_A[5]
A5 D5
DDR_DQ[21]
C1703 270 SDRAM_CAS_L R1603 10 DDR_CAS_L DDR_A[6] DDR_DQ[1] DDR_A[6] DDR_DQ[22]
0.1 A6 D6 A6 D6
SDRAM_WE_L R1604 10 DDR_WE_L DDR_A[7] DDR_DQ[0] DDR_A[7] DDR_DQ[23]
C1704 R1707 A7 D7 A7 D7
100 OPEN DDR_A[8] DDR_DQ[15] DDR_A[8] DDR_DQ[24]
K1701 /6.3 A8 D8 A8 D8
SHORT DDR_A[9] DDR_DQ[14] DDR_A[9] DDR_DQ[25]
A9 D9 A9 D9
DDR_A[10] DDR_DQ[13] DDR_A[10] DDR_DQ[26]
A10/AP D10 A10/AP D10
C1702 DDR_A[11] DDR_DQ[12] DDR_A[11] DDR_DQ[27]
100 /6.3 A11 D11 A11 D11
DDR_A[12] DDR_DQ[11] DDR_A[12] DDR_DQ[28]
D3.3V A12 D12 A12 D11
C1701 DDR_BA[0] DDR_DQ[10] DDR_BA[0] DDR_DQ[29]
0.1 BA0 D13 BA0 D13
T T OS DDR_A[0] DDR_BA[1] DDR_DQ[9] DDR_BA[1] DDR_DQ[30]
BA1 D14 BA1 D14
RA1629 DDR_A[1] DDR_DQ[8] DDR_DQ[31]
D15 D15
C1707 C1708 C1710 C1709 47 DDR_A[2]
0.1 47 /6.3 47 /6.3 OPEN C1645 CS CS
OPEN DDR_A[3] DDR_CKE DDR_CKE
CKE CKE
DDR_A[4] DDR_RAS_L DDR_RAS_L
RAS RAS
RA1630 DDR_A[5] DDR_CAS_L DDR_CAS_L
C1646 CAS CAS
0.1 47 DDR_A[6] DDR_WE_L DDR_WE_L
WE WE
DDR_A[7] DDR_DQM[0] DDR_DQM[2]
LDM NC LDM NC
DDR_A[8] DDR_DQM[1] DDR_DQM[3]
UDM NC UDM NC
RA1631 DDR_A[9] DDR_DQS[0] DDR_DQS[2]
LDQS NC LDQS NC
47 DDR_A[11] DDR_DQS[1] DDR_DQS[3]
UDQS NC UDQS NC
DDR_A[12]
CLK NC CLK NC
CLK NC CLK NC
RA1632 DDR_BA[0]
NC NC
47 DDR_BA[1]
DDR_A[10] C1655 C1657
C1705 OPEN VREF OPEN VREF
R1703 OPEN VDD GND VDD GND
2.2k
_0.5% C1656 VDD GND C1658 VDD GND
R1644 47 0.1 0.1
VDD GND VDD GND
R1704
2.2k VDDQ GNDQ VDDQ GNDQ
_0.5% C1706 R1605 47 DDR_CKE
D3.3V 0.1 VDDQ GNDQ VDDQ GNDQ
R1606 47 DDR_RAS_L
GND VDDQ GNDQ VDDQ GNDQ
R1607 47 DDR_CAS_L
SSTL2_VDD VDDQ GNDQ VDDQ GNDQ
SDRAM_DQ[0-15] R1608 47 DDR_WE_L
SDRAM_DQ[0-15] VDDQ GNDQ VDDQ GNDQ
SDRAM_DQ[16-31]
SDRAM_DQ[16-31]
SDRAM_A[14-17]
SDRAM_A[14-17]

OS

OS
SDRAM_A[0-12]
SDRAM_A[0-12]
SDRAM_CKE C1601 C1602
SDRAM_CKE 220 /4V 220 /4V
SDRAM_RAS_L
SDRAM_RAS_L
SDRAM_CAS_L R1645 OPEN SDRAM_DQM[0] SDRAM_DQM[0] R1653 0‘ DDR_DQM[0]
SDRAM_CAS_L
SDRAM_WE_L R1646 OPEN SDRAM_DQM[1] SDRAM_DQM[1] R1654 0‘ DDR_DQM[1]
SDRAM_WE_L
SDRAM_DQM[0] R1647 OPEN SDRAM_DQM[2] SDRAM_DQM[2] R1655 0‘ DDR_DQM[2]
SDRAM_DQM[0]
SDRAM_DQM[1] R1648 OPEN SDRAM_DQM[3] SDRAM_DQM[3] R1656 0‘ DDR_DQM[3] 3 9 15 55 61 1 81 33 3 9 15 55 61 1 81 33
TO SHEET 4 SDRAM_DQM[1]
SDRAM_DQM[2]
SDRAM_DQM[2]
C1647
R1649 100 SDRAM_DQS[0] SDRAM_DQS[0] R1657 22 DDR_DQS[0]
SDRAM_DQM[3] OPEN R1650 100 SDRAM_DQS[1] SDRAM_DQS[1] R1658 22 DDR_DQS[1]
SDRAM_DQM[3] C1605 C1606 C1607 C1608 C1609 C1610 C1611 C1612 C1613 C1614 C1615 C1616 C1617 C1618 C1619 C1620
SDRAM_DQS[0] R1651 100 SDRAM_DQS[2] SDRAM_DQS[2] R1659 22 DDR_DQS[2] 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1
SDRAM_DQS[0]
SDRAM_DQS[1] R1652 100 SDRAM_DQS[3] SDRAM_DQS[3] R1660 22 DDR_DQS[3]
SDRAM_DQS[1] C1648
SDRAM_DQS[2] 0.1 R1609 OPEN SDRAM_CLK[0] SDRAM_CLK[0] R1613 0‘ DDR_CLK[0]
SDRAM_DQS[2]
SDRAM_DQS[3] R1610 OPEN SDRAM_CLK[1] SDRAM_CLK[1] R1614 0‘ DDR_CLK[1]
SDRAM_DQS[3]
SDRAM_CLK[0] R1611 OPEN SDRAM_CLK_L[0] SDRAM_CLK_L[0] R1615 0‘ DDR_CLK_L[0]
SDRAM_CLK[0]
SDRAM_CLK[1] R1612 OPEN SDRAM_CLK_L[1] SDRAM_CLK_L[1] R1616 0‘ DDR_CLK_L[1]
SDRAM_CLK[1]
SDRAM_CLK_L[0]
SDRAM_CLK_L[0]
SDRAM_CLK_L[1]
SDRAM_CLK_L[1]
GND C1653
OPEN
SDRAM_VREF

C1654
0.1

SHEET 3

(No.XA020SCH) 2-9
Media processor section
AO_D[0] SDRAM_A[14-17]
SDRAM_A[14-17]
AO_SCLK SDRAM_VREF
SDRAM_CLK_L[1]
AO_FSYNC SDRAM_CLK_L[1]
TO SHEET 5 AO_IEC958
AO_MCLKO
SDRAM_CLK[1]
SDRAM_CLK_L[0]
SDRAM_CLK[1]
SDRAM_CLK_L[0]
SDRAM_CLK[0]
AI_D[0] SDRAM_CLK[0]
SDRAM_WE_L

TL1488

TL1487
TL1431
TL1430
TL1429
VIDEO_MUTE[H] SDRAM_WE_L
SDRAM_CKE
TO SHEET 2 TO SHEET 3

SDRAM_CLK_L[1]

SDRAM_CLK_L[0]
PHY_CNA SDRAM_CKE

100

100
100

100

100

100
100

SDRAM_DQM[3]

SDRAM_DQM[2]

SDRAM_DQM[1]
SDRAM_DQS[3]

SDRAM_DQS[2]

SDRAM_DQS[1]
0‘
SDRAM_RAS_L

SDRAM_RAS_L
SDRAM_CAS_L

SDRAM_DQ[31]
SDRAM_DQ[30]
SDRAM_DQ[29]
SDRAM_DQ[28]
SDRAM_DQ[27]
SDRAM_DQ[26]
SDRAM_DQ[25]
SDRAM_DQ[24]

SDRAM_DQ[23]
SDRAM_DQ[22]
SDRAM_DQ[21]
SDRAM_DQ[20]
SDRAM_DQ[19]
SDRAM_DQ[18]
SDRAM_DQ[17]
SDRAM_DQ[16]

SDRAM_DQ[15]
SDRAM_CLK[1]

SDRAM_CLK[0]
0‘
0‘

SDRAM_WE_L
480I[H] SDRAM_RAS_E

SDRAM_A[17]

SDRAM_A[15]
SDRAM_A[14]

SDRAM_A[12]
SDRAM_A[11]
SDRAM_A[10]

SDRAM_DQM[0]
SDRAM_CKE

SDRAM_DQS[0]
OPEN

SDRAM_DQ[14]
SDRAM_DQ[13]
SDRAM_DQ[12]
SDRAM_DQ[11]
SDRAM_DQ[10]
SDRAM_CAS_L

SDRAM_A[9]
SDRAM_A[8]
SDRAM_A[7]
SDRAM_A[6]
SDRAM_A[5]
SDRAM_A[4]
SDRAM_A[3]
SDRAM_A[2]
SDRAM_A[1]
SDRAM_A[0]

SDRAM_DQ[9]
SDRAM_DQ[8]

SDRAM_DQ[7]
SDRAM_DQ[6]
SDRAM_DQ[5]
SDRAM_DQ[4]
SDRAM_DQ[3]
SDRAM_DQ[2]
SDRAM_DQ[1]
SDRAM_DQ[0]
SDRAM_CAS_L
SDRAM_DQM[0-3]

TL1435

TL1434
TL1433
TL1432
R1483
R1482
R1481
R1480

R1479

R1478
R1477
R1476

R1475
R1474

R1473
SDRAM_DQM[0-3]
TO SHEET 5 SDRAM_DQS[0-3]
SDRAM_A[0-12]
SDRAM_DQS[0-3]
SDRAM_A[0-12]
SDRAM_DQ[16-31]
SDRAM_DQ[16-31]
SDRAM_DQ[0-15]
SDRAM_DQ[0-15]

AO_MCLKO

SDRAM_CLK_L[1]
A2_FSYNC/GPIOExt[34]
AI_D[1]/GPIO[6]

AO_D[3]
AO_D[2]
AO_D[1]
AO_D[0]

SDRAM_DQM[3]

SDRAM_DQM[2]

SDRAM_DQM[1]

SDRAM_DQM[0]
AI_MCLKO

AO_MCLKI/GPIOExt[33]

AO2_D[0]
AO_FSYNC

SDRAM_CLK[1]
A2_SCLK/GPIOExt[31]

SDRAM_WE[L]
AI_D[0]

SDRAM_CKE

SDRAM_DQS[3]

SDRAM_DQS[2]

SDRAM_DQS[1]

SDRAM_DQS[0]
AO_SCLK

SDRAM_VREF
AI_MCLKI/GPIOExt[32]
AI_FSYNC

SDRAM_DQ[9]
SDRAM_DQ[8]

SDRAM_DQ[7]
SDRAM_DQ[6]
SDRAM_DQ[5]
SDRAM_DQ[4]
SDRAM_DQ[3]
SDRAM_DQ[2]
SDRAM_DQ[1]
SDRAM_DQ[0]
AI2_D/GPIO[7]

SDRAM_RAS[L]
SDRAM_CAS[L]

SDRAM_DQ[31]
SDRAM_DQ[30]
SDRAM_DQ[29]
SDRAM_DQ[28]
SDRAM_DQ[27]
SDRAM_DQ[26]
SDRAM_DQ[25]
SDRAM_DQ[24]

SDRAM_DQ[23]
SDRAM_DQ[22]
SDRAM_DQ[21]
SDRAM_DQ[20]
SDRAM_DQ[19]
SDRAM_DQ[18]
SDRAM_DQ[17]
SDRAM_DQ[16]

SDRAM_DQ[15]
SDRAM_DQ[14]
SDRAM_DQ[13]
SDRAM_DQ[12]
SDRAM_DQ[11]
SDRAM_DQ[10]
AI_SCLK

AO_IEC958

SDRAM_CLK[0]

SDRAM_A[9]
SDRAM_A[8]
SDRAM_A[7]
SDRAM_A[6]
SDRAM_A[5]
SDRAM_A[4]
SDRAM_A[3]
SDRAM_A[2]
SDRAM_A[1]
SDRAM_A[0]
SDRAM_A[17]
SDRAM_A[16]
SDRAM_A[15]
SDRAM_A[14]
SDRAM_A[13]
SDRAM_A[12]
SDRAM_A[11]
SDRAM_A[10]
SDRAM_CLK_L[0]
R1471 100
ALE
R1470 1k R1472 0‘
RST[L]
R1469 1k C1459 OPEN
MCONFIG
CS0_8BIT
R1468 100
CLKI LDS[L]/OE[L]
TL1402 R1467 100
CLKX UDS[L]/UWE[L]
TL1437 R1466 100
CLKO_DAC/GPIOExt[35] GPIO[0]
R1408 1k R1465 100
BYPASS_PLL GPIO[1]
D3.3V TL1403 TL1486
EPD[L] GPIO[2] ALE
TL1404 TL1485
RSTO[L] GPIO[3] OE[L]/LDS[L]
R1409 10k R1462 100
TCK GPIO[4]/PCMCIA_IOW[L] UWE[L]/UDS[L]
TL1407 R1410 10k R1461 100
TDI GPIO[5]/PCMCIA_IOR[L] ELINK_INT[L]
R1411 100 R1460 100
TDO WR[L]/LWE[L] RD/WR[L]
R1412 10k R1459 100
TMS WAIT[L] WAIT[L]
R1413 10k
TRST[L]
VI_D[0]
DTACK[L]
CS[5]
R1458 100
DTACK[L]
CS[1]
TO SHEET 7
VI_D[1] CS[4] CS[0]
VI_D[2]
VI_D[2] CS[3] MADD[22]
VI_D[3] MADD[1-5]
VI_D[3] CS[2] MADD[1-5]
VI_D[4] R1453 100 CS[1] MADD[6-21]
VI_D[4] CS[1] MADD[6-21]
VI_D[5] R1452 100 CS[0] /MDT[0-15]
VI_D[5] CS[0]
VI_D[6]
VI_D[6] MADDR[26]
VI_D[7]
VI_D[7] MADDR[25]
VI_D[8]
VI_D[8] MADDR[24]
VI_D[9]
VI_D[9] MADDR[23]
R1414 1k R1451 100 MADD[22]
VI_E[0] MADDR[22]
R1415 1k R1450 100 MADD[5]
VI_VSYNC[0] MADDR[5]
V3.3V MADD[4]
VI_CLK[0] MADDR[4]
K1407
SHORT
R1416
R1417
1k
1k
VI_CLK[1]
VI_VSYNC[1]/IvGPIOExt[45]
MADDR[3]
MADDR[2]
RA1411
100
MADD[3]
MADD[2]
PHY_RESET[L] TO SHEET 2
R1402 TL1489 MADD[1]
0Ω VI_E[1]/IvGPIOExt[29] MADDR[1]
MADD[21]
VO2_D[0] MADDR[21]/MDATA[15]
RA1410 MADD[20]
VO2_D[1] MADDR[20]/MDATA[14]
100 MADD[19]
VO2_D[2] MADDR[19]/MDATA[13]
MADD[18]
VO2_D[3] MADDR[18]/MDATA[12]
C1450 MADD[17]
0.1 VO2_D[4] MADDR[17]/MDATA[11]
RA1409 MADD[16]
VO2_D[5] MADDR[16]/MDATA[10]
100 MADD[15]
VO2_D[6] MADDR[15]/MDATA[9]
X1401 MADD[14]
NAX0580-001X VO2_D[7] MADDR[14]/MDATA[8]
MADD[13]
VO2_D[8] MADDR[13]/MDATA[7]
RA1408 MADD[12]
VO2_D[9] MADDR[12]/MDATA[6]
VO_D[0] 100 MADD[11]
VO_D[0]/IvGPIOExt[0] MADDR[11]/MDATA[5]
VO_D[1] MADD[10]
VO_D[1]/IvGPIOExt[1] MADDR[10]/MDATA[4]
VO_D[2] RA1401 MADD[9]
VO_D[2]/IvGPIOExt[2] MADDR[9]/MDATA[3]
VO_D[3] 100 RA1407 MADD[8]
VO_D[3]/IvGPIOExt[3] MADDR[8]/MDATA[2]
VO_D[4] 100 MADD[7]
VO_D[5]
VO_D[4]/IvGPIOExt[4]
VO_D[5]/IvGPIOExt[5]
IC1401 MADDR[7]/MDATA[1]
MADDR[6]/MDATA[0]
MADD[6] DAC_RST[L] TO SHEET 5
VO_D[6] RA1402 ATA_ADD[0]
VO_D[6]/IvGPIOExt[6] ATAPI_ADDR[0]
VO_D[7] 100 ATA_ADD[1]
VO_D[7]/IvGPIOExt[7] ATAPI_ADDR[1]
VO_D[8] ATA_ADD[2]
VO_D[8]/IvGPIOExt[8] ATAPI_ADDR[2]
VO_D[9] ATA_ADD[3]
VO_D[9]/IvGPIOExt[9] ATAPI_ADDR[3]
VO_D[10] RA1403 ATA_ADD[4]
VO_D[10]/IvGPIOExt[10] ATAPI_ADDR[4]
VO_D[11] 100 ATA_DAT[15]
VO_D[11]/IvGPIOExt[11] ATAPI_DATA[15]
VO_D[12] ATA_DAT[14]
VO_D[12]/IvGPIOExt[12] ATAPI_DATA[14]
VO_D[13] ATA_DAT[13]
VIDEO_27M VO_D[13]/IvGPIOExt[13] ATAPI_DATA[13]
VI_D[2-9] VO_D[14] RA1404 ATA_DAT[12]
VI_D[2-9] VO_D[14]/IvGPIOExt[14] ATAPI_DATA[12]
VO_D[0-15] VO_D[15] 100 ATA_DAT[11]
VO_D[0-15] VO_D[15]/IvGPIOExt[15] ATAPI_DATA[11]
100 ATA_DAT[10]
R1419 VO_E/IvGPIOExt[30] ATAPI_DATA[10]
TL1412 ATA_DAT[9]
VO_ACTIVE ATAPI_DATA[9]
TL1490 ATA_DAT[8]
VO_HSYNC ATAPI_DATA[8]
TL1491 ATA_DAT[7]
VO_VSYNC ATAPI_DATA[7]
TO SHEET 5 DAC_CVBS_OUT
R1421 OPEN
R1420 100
R1485 OPEN
VO_CLK
DAC1_OUT
ATAPI_DATA[6]
ATAPI_DATA[5]
ATA_DAT[6]
ATA_DAT[5]
R1422 OPEN R1486 OPEN ATA_DAT[4]
DAC_SY_OUT DAC2_OUT ATAPI_DATA[4]
R1423 OPEN R1487 OPEN ATA_DAT[3]
DAC_SC_OUT DAC3_OUT ATAPI_DATA[3]
R1424 OPEN R1488 OPEN ATA_DAT[2]
DAC_Y_OUT DAC4_OUT ATAPI_DATA[2]
R1425 OPEN R1489 OPEN ATA_DAT[1] ATA_ADD[0-4]
DAC_PB_OUT DAC5_OUT ATAPI_DATA[1] ATA_ADD[0-4]
R1426 OPEN R1490 OPEN ATA_DAT[0] ATA_DAT[0-15]
DAC_PR_OUT DAC6_OUT ATAPI_DATA[0] ATA_DAT[0-15]
VDDI1.8 C1452 0.1
V3.3V R1493 DAC_DVSS_1 ATAPI_RESET ATA_RESET
DAC_DVDD ATAPI_DMAACK[L] ATA_DMAACK[L]

K1408
0Ω C1453
0.1
DAC_VDD_0
DAC_VDD_3
ATAPI_DMARQ
ATAPI_IORDY
ATA_DMARQ
ATA_IORDY
TO SHEET 6
SHORT OPEN D1401 D1402 DAC4_OUTB ATAPI_INTRQ ATA_INTRQ
C1454 DAC2_OUTB ATAPI_DIOR[L] ATA_DIOR[L]
USB_AVDD_0 ATAPI_DIOW[L] ATA_DIOW[L]
USB_AVDD_1 ATAPI2_RESET
C1455 0.1
USB_AGND_0 ATAPI2_DMAACK[L]
C1456 OPEN R1498 10k
USB_AGND_1 ATAPI2_DMARQ
TL1413 R1497 10k
DPLUS_0 ATAPI2_IORDY
TL1414 R1496 10k
DMINUS_0 ATAPI2_INTRQ
TL1415 HOST_PO_0 ATAPI2_DIOR[L]
R1491 1k
HOST_OC_0 ATAPI2_DIOW[L]
TL1417 DPLUS_1 ATAPI2_ADDR[0]
TL1418 DMINUS_1 ATAPI2_ADDR[1]
TL1419 HOST_PO_1/GPIOExt[43] ATAPI2_ADDR[2]
R1427 100 TL1420
HOST_OC_1/GPIOExt[44] ATAPI2_ADDR[3]
USB_48MHz/GPIOExt[36] ATAPI2_ADDR[4]
PHY_DATA[7] TL1464
1394_PHY_DATA[7] ATAPI2_DATA[15]
PHY_DATA[6] TL1463
1394_PHY_DATA[6] ATAPI2_DATA[14]
PHY_DATA[5] RA1405 TL1462
1394_PHY_DATA[5] ATAPI2_DATA[13]
PHY_DATA[4] 100 TL1461
1394_PHY_DATA[4] ATAPI2_DATA[12]
PHY_DATA[3] TL1460
1394_PHY_DATA[3] ATAPI2_DATA[11]
PHY_DATA[2] TL1459
1394_PHY_DATA[2] ATAPI2_DATA[10]
PHY_DATA[1] RA1406 TL1458
1394_PHY_DATA[1] ATAPI2_DATA[9]
PHY_DATA[0-7] PHY_DATA[0] 100

SIO_UART1_CTS/GPIOExt[42]
SIO_UART1_RTS/GPIOExt[41]
TL1457

SIO_UART2_RX/GPIOExt[37]
PHY_DATA[0-7] 1394_PHY_DATA[0] ATAPI2_DATA[8]

SIO_UART2_TX/GPIOExt[38]

SIO_SPI_CS[0]/GPIOExt[24]
SIO_SPI_CS[1]/GPIOExt[25]
R1428 100 TL1456
PHY_CTL[1] 1394_PHY_CTL[1] ATAPI2_DATA[7]
R1429 100

SIO_IRTX1/GPIOExt[40]
TL1455

SIO_IRRX/GPIOExt[39]
PHY_CTL[0] 1394_PHY_CTL[0] ATAPI2_DATA[6]
TO SHEET 2 PHY_LREQ
R1430
R1431
100
100
1394_LREQ ATAPI2_DATA[5] TL1454

SIO_UART2_CTS
SIO_UART2_RTS
PHY_LPS 1394_LPS ATAPI2_DATA[4] TL1453

SIO_UART1_RX
SIO_UART1_TX

SIO_SPI_MOSI
SIO_SPI_MISO

SIO_SPI_CS[2]
SIO_SPI_CS[3]
TL1452

SIO_SPI_CLK
PHY_LINK_ON 1394_LINK_ON ATAPI2_DATA[3]
TL1451
BIAS_5V01
BIAS_5V00
VDDP_19A

VDDP_08A

SIO_IRTX2
PHY_CLK 1394_PHY_CLK ATAPI2_DATA[2]
VDD25_01
VDD25_00
VDD25_02
VDD25_03
VDD25_04
VDD25_05
VDD25_06
VDD25_08

XTALVDD

XTALVSS
VDDP_19
VDDP_20
VDDP_21
VDDP_01
VDDP_02
VDDP_03
VDDP_04

VDDP_09
VDDP_10

GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND

SIO_SDA
SIO_SCL
REFVDD
AGND_0
AGND_1
AGND_2
AGND_3

REFVSS
AVDD_1
AVDD_1
AVDD_2
AVDD_3

TL1450
VDD_14
VDD_30
VDD_15
VDD_23
VDD_00
VDD_01
VDD_02
VDD_03
VDD_08
VDD_09

ATAPI2_DATA[1]

VREF
ATAPI2_DATA[0] TL1449

DIGI3.3V
D2.5V
TO SHEET 5

OPEN
OPEN
B1401
D1.8V

100
100

100

100
100

100
LC1401

0Ω
GND OPEN NQR0415-002X

R1445 100

TL1436

TL1422

TL1423
TL1424

TL1448
TL1425
C1403 K1402

R1432
R1433

R1434
R1435

R1436
R1437
R1438
R1439

R1440
0.1 SHORT K_BUS_CLK
T T R1446 100
C1442 K_BUS_REQ
0.1
C1401 C1402
0.1 0.1
C1404 C1405 C1406
100
/6.3
0.1 0.1
SSTL2_VDD C1419 C1420
OPEN 10
/6.3
C1421C1422 C1423 C1424 C1425
0.1 0.1 0.1 0.1 0.1
K1403
SHORT
R1447
R1448
100
100
SYS_RESET[L]
K_BUS_OUT
TO SHEET 5
B1402 LC1402 D1403 R1449 100

OPEN
R1492
OPEN NQR0415-002X K_BUS_IN
1SS355
C1444 R1441

SN74HCT08APW
# K1404 0.1 10k

SN74LV08APW
T

0.1 _1%
C1408 C1409 C1440 C1441 C1411 C1412 C1427 C1428 C1429C1430

1.18k

4.7k
4.7k
0.1 0.1 0.1 0.1 100 0.1 10 0.1 0.1 0.1

0.01
/6.3 /6.3

IC1404

IC1405
D5.0V
B1403 LC1403 K1401 K1405 # K1406
D5.0V OPEN NQR0415-002X SHORT OPEN

S1401
OPEN
C1417

R1401
C1447
C1448

R1443
R1444
D1.8V
TO SHEET 5 D2.5V
0.1
C1418
0.1 T T
GND
C1413 C1414 C1415 C1416 C1434 C1435 C1436 C1437 C1438 C1439 C1445 C1446 C1457 C1458
100 0.1 OPEN 0.1 OPEN 10 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1
C1433 C1432 C1431 C1426 /6.3 C1449 /6.3
TL1495
TL1494
TL1493

TL1492
0.1 0.1 0.1 0.1 C1443 C1407 C1410
0.1 0.1 0.1 0.1
D3.3V
SSTL2_VDD
TO SHEET 3 VDDI1.8 E5_RESET[L]
GND UART2_TX
UART2_RX
TO SHEET 7

CN1402
CN1403

A_DAC_CS

VIDEO_RXD
GND

VIDEO_CS
RX

JLIP_TX
D5.0V

D3.3V

JRIP_RX
TX

GND

SPI_CLK

SPI_CLK
SPI_MOSI

SPI_MOSI
A_MUTE2[H]
VIDEO_RST[L]

TO SHEET 5
TO SHEET 5
SHEET 4

2-10 (No.XA020SCH)
Video signal controller section

VDDI1.8
DIGI3.3V
IC1002
D2.5V HY57V161610DTC8
K4S161622D-TC80
D1.8V C1042
0.1
GND
VDD VSS
K_BUS_OUT DQ0 DQ15
DQ0 DQ15
TO SHEET 4 K_BUS_IN
P_CTL[H] RA1003
DQ1
DQ1 DQ14
DQ14
RA1005
10k 10k
R1036 VSSQ VSSQ
SYS_RESET[L] CR 1k DQ2 DQ13
DQ2 DQ13
AI_D[0] R1035 C1043 DQ3 DQ12
0.1 DQ3 DQ12 C1047
K_BUS_REQ Q1002 0.1
0 VDDQ VDDQ C1088
A_MUTE2[H] DQ4 DQ11
DQ4 DQ11 OPEN
K_BUS_CLK DQ5 DQ10
DQ5 DQ10
R1037 VSSQ VSSQ
100 DQ6 DQ9
_0.5% DQ6 DQ9
CN1002 C1044 DQ7 DQ8
RA1004 0.1 DQ7 DQ8 C1046 RA1006
K1002 10k 0.1 10k
SHORT C1070 VDDQ VDDQ
OPEN UDQM
NQR0129-002X K1003 LDQM N.C/RFM
WE R1033
SHORT K1004 WE( L) UDQM
CAS 27M_SDRAM470
NQR0129-002X K1005 R1039 CAS( L) CLK
CB 1k R1030 RAS
SHORT K1006 10k RAS( L) CKE
R1038 R1032
SHORT K1007 CS( L) N.C 10k
Q1003 A9
0 BA A9
R1031 AP A8
10k A10/AP A8
A0 A7
A0 A7
A1 A6
SHORT K1008 R1040 A1 A6
B1008 100 A2 A5
_0.5% C1045 A2 A5
0.1 A3 A4
TO CN4102 SHORT K1009 LC1001
OPEN C1071 OPEN
A3
VDD VSS
A4

SHEET 10
C1066 C1067
OPEN OPEN R1042
Y 1k

NQR0129-002X K1010 R1041 C1041


Q1004 K1019 10
0 T /6.3
D5.0V SHORT

C1031 C1030 C1029 C1028 C1027 C1026 C1025 C1024


OPEN 0.1 OPEN OPEN OPEN 0.1 OPEN OPEN

R1043 C1095
150 10
K1001 _0.5% /6.3
SHORT
C1078 C1079 C1054 C1055 C1056
OPEN OPEN 0.1 0.1 0.1 C1072 OPEN
C1096 R1010
0.1 OPEN

C1057 C1059 C1061 C R1045


0.1 0.1 0.1 1k

UDQM
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9

DQ8
DQ7
DQ6

DQ5
DQ4
DQ3

DQ2
DQ1
DQ0

RAS
CAS
WE
R1044

AP
A9

A6
A7
A8

A3
A4
A5

A0
A1
A2
0 Q1005
D5.0V
AO_IEC958
TO SHEET 4

WE
0VDDE
0VDDI

0VDDI

LUDQM
A10
DQ9

DQ8
DQ7
DQ6

DQ5
DQ4
DQ3

DQ2
DQ1
DQ0

RAS
CAS
VDDE

OUTV
VSS

VSS
VDDI
A9

A6
A7
A8

A3
A4
A5

A0
A1
A2
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

0VDDE

0VDDE
0VSS

0VSS

0VDDI
V3.3V
##
GND R1047
VC2 OUTH TL1031

C1073 VC3 VDOUT TL1032


OPEN C1058 VC0 CLKOSD TL1033
C1036 OPEN
0.1 VC1 HDOUT TL1034
## 0VDDI HDCVF
R1049 YSO3
RY 1k 0VSS YSO3
C1032 0.1 YSO2
CN1001 TL1001 # # R1048 0.1 DAY_COMP YSO2
## DAY_VREF VSS
TL1002 Q1006 R1021 C1033
0
3.3k R1024 DAY_AVSS1 0VDDI
TL1003 R1022 TL1035 C1021
1.5k DAY_VRO CSYNC OPEN
_0.5% _0.5% 2.7k _0.5% YSO1
## C1037 OPEN DAY_AVDD1 YSO1
TL1005 R1051 YSO0 C1020
270 DAYO YSO0 0.1
TL1006 _0.5% C1038 0.1
DAY_AVDD2 VDDE
RA1001
C1074 DAY_AVSS2 0VSS 0
OPEN YSO3 VI_D[9]
DACB_AVSS2 VDCVF
TL1009 C1039 0.1 CSO3 YSO2 VI_D[8]
DACB_AVDD2 CSO3
TL1010 CSO2 YSO1 VI_D[7]
## DACBO CSO2
TL1011 R1053 C1040 OPEN YSO0 VI_D[6]
RC 1k DACB_AVDD1 VSS
TO CN4101 # # R1052
##
C1034 0.1
DACB_COMP 0VDDI
CSO1 C1016
CSO3
CSO2
VI_D[5]
VI_D[4]
DACB_AVSS1 IC1001 CSO1 OPEN
SHEET 10 TL1014 0 Q1007
C1035 0.1
DACR_AVSS1
JCP8059
RESVD
CSO0
CSO1
CSO0
VI_D[3]
VI_D[2]
DACR_COMP CSO0 R1006
C1087 OPEN RA1002
## DACR_AVDD1 MONI1 R1007 0
R1055 0
180 DACRO RESHD R1004
TL1018 _0.5% C1060 0.1 10k
DACR_AVDD2 MONI2
SHORT K1011 C1075 0 C1015
OPEN DACR_AVSS2 0VDDE 0.1
TL1020
DARC_AVSS1 VSS R1005
SHORT K1012 C1089 0.1 VO_D[14]
B1004 DARC_AVDD1 CSI6
OPEN VO_D[15] 10k
B1007 C1065 DARCO CSI7 R1003
SHORT K1013 4.7 C1014
DARYO ZCNT 0.1
SHORT K1014 C1090 0.1 0
DARY_AVDD1 0VDDE
SHORT K1015 C1069 L1004 ## C1062 0.01
OPEN 10µ R1056 DARY_AVSS1 VDDI
SHORT K1016 2.2k Q1009 C1093 0.1 VO_D[11] C1013
R1046 DARY_VREF CSI3 OPEN
K1017 R1050 VO_D[12]
SHORT 1.5k DARY_VRO CSI4
LC1002 Q1008 _0.5% 3.3k R1028 VO_D[13] C1012
OPEN R1057 UMZ1N _0.5% 2.7k _0.5% DACO CSI5 0.1
T
K1018 C1051 C1052 C1063 33 BC847PN DAC_AVDD1 VDDI
SHORT 10 /6.3 0.1 OPEN BC846PN C1091 0.1
DAC_AVSS1 VSS
C1094 0.1 VO_D[8]
TL1097 DAC_VREF CSI0
C1092 VO_D[9]
0.1 DAC_VRO CSI1
LC1004 R1071 R1054 R1027 VO_D[10]
OPEN C1076 1.5k 3.3k 2.7k 0VDDI CSI2
OPEN _0.5% _0.5% VO_D[5]
R1059 0VSS YSI5
470 VO_D[2]
BLK1 YSI2
VO_D[6]
BLK2 YSI6

ADC_AVDD1

ADC_AVDD2
ADY_AVDD1

ADY_AVDD2

ADC_AVSS1

ADC_AVSS2
ADY_AVSS1

ADY_AVSS2
C1077 VO_D[3]
0.1 BLK3 YSI6

PLL_VSS

PLL_RST
ADC_RH

ANATST
ADY_RH

ADC_RL
ADY_RL
SIMTST

SDOUT

AMUTE
0VDDE

0VDDI

0VDDI
VDDE
SCLK

TRST

0VSS

0VSS
ADCI
SDIS

ADYI

YSI1
YSI4
YSI7
YSI0
TMS

TDO

VPD
TCK

VSS

RST

CLK

INH
INV
TDI
CS
R1068 R1066 R1062
2.2k 100 OPEN
_0.5%

220 _0.5%
TL1098

0.1
0.1
TL1091

TL1093
R1069

R1060 R1002

R1061 R1001
2.2k Q1010

0
0
0
0

C1017
C1018
AO_D[0] _0.5%

0
SPI_CLK D3.3V B1001
Q1011

22k
22k
AO_SCLK

R1013
R1015
R1014
R1029

R1012

R1072
TL1099 K1020
SPI_MOSI NQR0129-002X LC1003
OPEN
AO_MCLKO
R1070
A_DAC_CS 1.2k C1002
C1097 C1098 _0.5% C1004 C1003
DAC_RST[L] 0.1 0.1 R1067 R1065 C1001 0.1 0.1 C1005
120 120 22 0.1
TO SHEET 4 T T 10

OPEN

OPEN
AO_FSYNC /6.3

C1010

C1011
/6.3
DAC_CVBS_OUT
C1006 C1007 C1008 C1009
DAC_SY_OUT OPEN 0.1 .1 0 0.1

OPEN

27M_8059

OPEN OPEN
R1020 C1023
DAC_SC_OUT R1009
TL1092 10k

R1018 1SS355

VO_D[1]
VO_D[4]
VO_D[7]
VO_D[0]
DAC_Y_OUT

D1002
DAC_PB_OUT

C1019
##

C1022
R1034 VI_D[2-9]

0.01
DAC_PR_OUT 10k VI_D[2-9]
VO_D[0-15]

1SS355
D3.3V VO_D[0-15]

0
27M_VIDEO R1019 0

D1001
VIDEO_27M
VIDEO_MUTE[H]
VIDEO_RXD
R1017 0
TO SHEET 4
OPEN
OPEN
OPEN
OPEN

## VIDEO_RST[L]
Q1001 SPI_MOSI
VIDEO_CS
C1048
C1049
C1053
C1050

SPI_CLK
UN221E-X 480I[H]
DTC144WKA-X
RT1N44HC-X

SHEET 5
(No.XA020SCH) 2-11
ATAPI Interface section

ATA_DAT[7] RA2201 FE_DAT[7]


ATA_DAT[8] OPEN FE_DAT[8]
ATA_DAT[6] FE_DAT[6]
ATA_DAT[9] FE_DAT[9]
ATA_DAT[5] RA2202 FE_DAT[5]
ATA_DAT[10] OPEN FE_DAT[10]
ATA_DAT[4] FE_DAT[4]
ATA_DAT[11] FE_DAT[11]
ATA_DAT[3] RA2203 FE_DAT[3]
ATA_DAT[12] OPEN FE_DAT[12]
ATA_DAT[2] FE_DAT[2]
ATA_DAT[13] FE_DAT[13]
ATA_DAT[1] RA2204 FE_DAT[1]
ATA_DAT[14] OPEN FE_DAT[14]
ATA_DAT[0] FE_DAT[0]
ATA_DAT[15] FE_DAT[15]
RA2205
OPEN

IC2201 SN74CBTD16210

NC 1OE
1A1 2OE
ATA_DAT[7]
1A2 1B1
ATA_DAT[8] FE_DAT[7]
1A3 1B2
ATA_DAT[6] FE_DAT[8]
1A4 1B3
ATA_DAT[9] FE_DAT[6]
1A5 1B4 CN2201
ATA_DAT[5] FE_DAT[9] R2204 33
1A6 1B5 RSTATA
GND GND GND
ATA_DAT[10] FE_DAT[5] FE_DAT[7] # K2201
1A7 1B6 HD_AT[7]
ATA_DAT[4] FE_DAT[10] FE_DAT[8] RA2208 # K2202
1A8 1B7 HD_AT[8]
ATA_DAT[11] FE_DAT[4] FE_DAT[6] 33 # K2203
1A9 1B8 HD_AT[6]
ATA_DAT[3] FE_DAT[11] D5.0V FE_DAT[9] # K2204
1A10 1B9 HD_AT[9]
ATA_DAT[12] FE_DAT[3] FE_DAT[5] # K2205
2A1 1B10 HD_AT[5]
ATA_DAT[2] FE_DAT[12] FE_DAT[10] RA2209 # K2206
2A2 2B1 HD_AT[10]
FE_DAT[2] R2217 FE_DAT[4] 33 # K2207
VCC 2B2 22k HD_AT[4]
ATA_DAT[13] FE_DAT[13] FE_DAT[11] # K2208
C2201 2A3 2B3 HD_AT[11]
0.1 FE_DAT[3] # K2209
D5.0V GND GND HD_AT[3]
ATA_DAT[1] FE_DAT[1] Q2201 FE_DAT[12] RA2210 # K2210
D3.3V 2A4 2B4 UN221E-X HD_AT[12]
ATA_DAT[14] FE_DAT[14] DTC144WKA-X FE_DAT[2] 33 # K2211
P_CTL[H] 2A5 2B5 RT1N44HC-X HD_AT[2]
TO SHEET 4 ATA_RESET
ATA_DAT[0]
2A6 2B6
FE_DAT[0] FE_DAT[13] # K2212
HD_AT[13]
ATA_DAT[0-15] ATA_DAT[15] FE_DAT[15] FE_DAT[1] # K2213
ATA_DAT[0-15] 2A7 2B7 HD_AT[1]
ATA_ADD[0] FE_DAT[14] RA2211 # K2214
GND 2A8 2B8 HD_AT[14]
ATA_ADD[1] FE_DAT[0] 33 # K2215
2A9 2B9 HD_AT[0]
ATA_ADD[2] FE_DAT[15] # K2216
2A10 2B10 HD_AT[15]
GND
TO DVD-RAM
R2205 82
DMARQ
DRIVE
R2203 GND
4.7k R2206 22
GND DIOW
RA2206
GND
OPEN R2207 22
DIOR
GND
R2208 82
IORDY
RA2207
CAB_SEL
ATA_ADD[3] OPEN R2209 22
DMACK
ATA_ADD[4]
GND
R2210 82
INT_ATA

C2202 0.1 R2211 33 # K2217


ATA_A1

IC2202 SN74CBT3245A R2212 33 # K2218


ATA_A0
R2213 33 # K2219
NC VCC ATA_A2
R2214 33 # K2220
ATA_DIOW[L] A1 OE CS1FX
R2215 33 # K2221
ATA_DIOR[L] A2 B1 CS3FX
DIOR
ATA_DMAACK[L] A3 B2 D3.3V

TO SHEET 4 ATA_DMARQ A4 B3 GND


ATA_IORDY A5 B4 D2201
R2216 OPEN
ATA_INTRQ A6 B5
ATA_ADD[0-4] ATA_ADD[3] OPEN
ATA_ADD[0-4] A7 B6
ATA_ADD[4]
A8 B7
R2201 R2202 GND B8
10k 5.6k

SHEET 6

2-12 (No.XA020SCH)
FLASH-ROM section

C1207 IC1203
0.1

LH_AR[22]
SN74LVC373APW-X

OE VCC
LH_AR[14] LH_AR[21]
Q0 Q7
IC1201 MADD[14] MADD[21]
MBPL65LM90TN D0 D7
K1201 MADD[15] MADD[20]
SHORT D1 D6
LH_AR[16] LH_AR[17] LH_AR[15] LH_AR[20]
A15 A16 Q1 Q6
LH_AR[15] LH_AR[16] LH_AR[19]
A14 VCCQ Q2 Q5
LH_AR[14] MADD[16] MADD[19]
A13 VSS D2 D5
LH_AR[13] MADD[21] C1203 MADD[17] MADD[18]
A12 DQ15 0.1 D3 D4
LH_AR[12] MADD[13] LH_AR[17] LH_AR[18]
A11 DQ7 Q3 Q4
LH_AR[11] MADD[20]
A10 DQ14 GND LE
LH_AR[22] LH_AR[10] MADD[12]
A9 DQ6 C1204
LH_AR[9] MADD[19] 47 /6.3
A8 DQ13
R1216 MADD[11]
100 A21 DQ5
LH_AR[21] MADD[18]
A20 DQ12
64MBIT MADD[10]
WE FLASH DQ4
R1222 0Ω
RESET MEMORY VCC
B1202 OPEN R1223 4.7k MADD[17]
ACC DQ11
R1224 4.7k MADD[9]
B1204 WP DQ3 C1206 IC1202
LH_AR[20] MADD[16] 0.1 SN74LVC373APW-X
A19 DQ10
LH_AR[19] MADD[8]
A18 DQ2
LH_AR[18] MADD[15]
R1225 10k A17 DQ9 OE VCC
LH_AR[8] MADD[7] LH_AR[6] LH_AR[13]
A7 DQ1 Q0 Q7
LH_AR[7] MADD[14] MADD[6] MADD[13]
A6 DQ8 D0 D7
LH_AR[6] MADD[6] MADD[7] MADD[12]
A5 DQ0 D1 D6
LH_AR[5] LH_AR[7] LH_AR[12]
A4 OE Q1 Q6
LH_AR[4] LH_AR[8] LH_AR[11]
A3 VSS Q2 Q5
LH_AR[3] MADD[8] MADD[11]
A2 CE D2 D5
LH_AR[2] MADD[9] MADD[10]
A1 A0 D3 D4
LH_AR[9] LH_AR[10]

R1226

4.7k
Q3 Q4
LH_AR[1] GND LE

TL1215 TL1216 CN1202

D3.3V GND
B1205 OPEN
GND UART2_CTS
R1227 100
UART2_RX UART2_RX
R1228 100
UART2_TX UART2_TX
B1206 OPEN
CS[0] UART2_RTS

TO SHEET 4 CS[1] CS_L[1]


ALE ALE
E5_RESET[L] RST[L]
MADD[1-5] MADD[5]
MADD[1-5] MADD[5]
MADD[6-21] MADD[4]
MADD[6-21] MADD[4]
MADD[3]
MADD[22] MADD[3]
MADD[21] MADD[2]
MADD[2]
MADD[1] R1217 100 LH_AR[1] MADD[20] MADD[1]
MADD[1]
MADD[2] R1218 100 LH_AR[2] MADD[19] RA1201 MADD[21]
10k MADD[21]/MDT[15]
MADD[3] R1219 100 LH_AR[3] MADD[18] MADD[20]
MADD[20]/MDT[14]
MADD[4] R1220 100 LH_AR[4] MADD[17] MADD[19]
MADD[19]/MDT[13]
MADD[5] R1221 100 LH_AR[5] MADD[16] MADD[18]
RA1202 MADD[18]/MDT[12]
MADD[15] 10k D3.3V MADD[17]
MADD[17]/MDT[11]
MADD[14] MADD[16]
MADD[16]/MDT[10] Not use
MADD[13] MADD[15]
MADD[15]/MDT[9]
MADD[12] MADD[14]

4.7k

4.7k

4.7k
MADD[14]/MDT[8]
MADD[11] RA1203 GND
MADD[10] 10k MADD[13]
MADD[13]/MDT[7]
MADD[9] MADD[12]

R1229

R1230

R1231
MADD[12]/MDT[6]
MADD[8] RA1204 C1208 MADD[11]
10k OPEN MADD[11]/MDT[5]
MADD[7] MADD[10]
TL1217 MADD[10]/MDT[4]
MADD[6] MADD[9]
MADD[9]/MDT[3]
MADD[8]
MADD[8]/MDT[2]
B1207 MADD[7]
OPEN MADD[7]/MDT[1]
MADD[6]
DTACK[L] MADD[6]/MDT[0]
WAIT[L] DTACK[L]/WAIT[L]
B1208
ELINK_INT[L] MEDUSA_INT[L]
TO SHEET 4 OE[L]/LDS[L] OE[L]/LDS[L]
UWE[L]/UDS[L] UWE[L]/UDS[L]
RD/WR[L] RD/WR[L]
GND

GND

SHEET 7
(No.XA020SCH) 2-13
Audio signal control section

AV1_L
AV2_H
D8202
I2C_CLK2
TO SHEET 12 I2C_DATA2
1SS133

A_MUTE1[H] D8201 OPEN


ADC_RST[L] R8220
4.7k
_0.5%
R8218 C8208 Q8202
_0.5% R8222 470p DTA144WKA
4.3k 120 R8223
Q8201 220
C8206 _0.5% DTC144WKA
4700p R8221
C8005 R8046 C8210
1/50 R8017 10k R8217 120 C8207 C8209 220 C8217 R8250
TU_AUDIO[R] R8040 4.3k _0.5% 470p 0.1 47 /25 470 R8252
TO SHEET 13 20k _0.5% /16 6.8k
TU_AUDIO[L] C8007 56K R8219
1/50 R8019 4.7k R8249 Q8205
_0.5% 47k R8047
_0.5% 27k 2SC2412K/QRS/
C8008 15k
1/50 R8020 R8214 C8205

1SS355
D8001
C8001 R8001 C8002 R8002 _0.5% 47k R8041 4.7k
_0.5%
470p
IC8202
R8234
100p 51k 100p 51k C8009 R8038 82K BA15218F 47k
1/50 R8021 R8212 R8216
_0.5%
_0.5% 47k 4.3k 120 R8224 R8233

R8042
OPEN

R8044
39K

1.8K
_0.5% 220 47k
F_AUDIO[R] C8203
TO SHEET 9 4700p R8215

R8039
IC8001 C8211 C8212
F_AUDIO[L] AK5365VQ 0.1 220 /16
R8211 120 C8215 R8242
_0.5% C8204

0.1
AUDIO_IN1[R] 4.3k 470p 47 /25 470 R8244

R8045
_0.5% 6.8k

82K

3.3K
R8043
AUDIO_IN1[L]

C8220
R8213

4.7k
TO SHEET 11 AUDIO_IN2[R] C8010 4.7k R8241 Q8203 AUDIO_OUT1[R]
1/50 _0.5% 27k 2SC2412K/QRS/
AUDIO_IN2[L] AUDIO_OUT1[L]
R8022
R8007 R8008 R8013 R8014 R8015 R8016
47k 47k 47k 47k 47k 47k 47k LINE_OUT[L] TO
_0.5% C8201
C8202 0.1 LINE_OUT[R] SHEET 11
C8011 470 DEC_OUT[L]
1/50 /6.3 IC8301 C8305
K8201 LA7151M-X 4.7 /50 DEC_OUT[R]
R8023 NQR0339-001X C8308
47k R8315
_0.5% IC8201 4.7 /50
AK4381VT C8304 47
C8012 C8307 4.7 /50
1/50 4.7 /50

VDD

VSS
DZFR
DZFL

AOUTR+
AOUTL+

AOUTR-
AOUTL-
R8024 R8301
47k 100
_0.5%
C8306 C8303
4.7 /50 4.7 /50
R8037
OPEN C8302

MCLK

LRCK

CCLK
0.1

BICK

CDTI
SDTI

PDN

CSN
C8301
R8303 470 /16

C8014 R8026 470


R8202 R8203 R8204 R8305
1 /50 20k 47 47 47 6.8k
R8201 R8304
R8036 47 27k
Q8301
R8031 47 2SC2412K/QRS/
20k R8035
_0.5% R8306
L8001 C8029 OPEN 47 470
D3.3V C8021 R8308
OPEN 4.7 /50 R8205 6.8k
D5V R8307
27k
AL12V OPEN Q8302
TO SHEET 10 AL-12V
2SC2412K/QRS/

R8206 R8316
GND 10k IC8302
LA7151M-X C8315 47
V3.3V 4.7 /50
C8318
4.7 /50
C8022 R8032 C8024 C8026 C8028 R8033 R8034 C8314
4.7 /50 20k 47 47 C8317 4.7 /50
_0.5% R8302 4.7
0.1 0.1 0.1 /50
C8023 100
L8501 C8503 100 /6.3 C8027
C8025 100 /6.3 4.7 C8313
R8506 1u 4.7 /50 4.7 /50 /50 4.7 /50
K8001 K8002
10 C8504
150P C8501 NQR0339-001X NQR0339-001X C8312 0.1

C8316
R8504 100
/16
C8505 82 C8502 C8311
330P
K8501 R8505 0.1 470 /16
10 R8309
# J8501 NQR0227-004
C8506 470
0.1 R8311
R8502
560 6.8k
R8310 Q8303
27k 2SC2412K/QRS/
R8501 R8312
4.7
R8323 470
R8503 R8321 220 10k R8313 R8314
560 27k
IC8501 R8324 6.8k
SN74LV08APW C8321 C8322 3.3k Q8304
220 0.1 2SC2412K/QRS/
/16 A_MUTE2[H]
R8507
DAC_SDA
560 R8322
220 DAC_SCL
K8401
C8402 NQR0339-001X A_DAC_CS
0.1 C8401 IC8303 DAC_RST[L]
100 /6.3 R8326
BA15218F
AO_FSYNC
TO
3.3k
AO_D[0] SHEET 10
R8325 AO_SCLK
10k C8324 C8323
AO_MCLKO
0.1 220 /16
AI_D[0]
AO_IEC958

SHEET 8

2-14 (No.XA020SCH)
Audio/Video signal input control section

# C4318
0.1

# C4319 GND VCC


470p
C/R1 GND #
# R4319 C4310
12k 470p
RE1 C/R2
# R4311
12k
A1 RE2

B1 A2
# D4301
1SS133 # L4301
Q1 B2 10u

# R4317 # R4318
Q1 Q2 # IC4301
22k 10k

# C4311
OPEN
# LA7357M
R4306 # C4306
GND Q2 1.2k 0.01
# # R4312
Q4301 #
# IC4304 # R4307 0‘
74HC4538D R4304
22k 10k

# C4302 # C4307 # C4308


0.01
47 /16 0.01
# # # # FSC_IN
C4301 # C4304 Q4302 Q4303 R4320 # C4309
0.01 0 0.01
TO SHEET 12 443[H] 0.01
# R4302 0
VCC

DET.ADJ #
R4309
# # 2.2k

TO #
R4301
R4303 #
L4302
#
C4303
#
R4305
5.6k
R4308
22k
#
C4305
SW5V
SHEET 10 GND
560
OPEN OPEN OPEN 0.01 #
R4310
8.2k

L4006
R4011 0‘ 10u
TO I2C_DATA_A/V
R4012 0‘
I2C_CLK_A/V
SHEET 12 GND ##

C4072 100 /6.3


R4046 R4049 C4071
SEPA_IN[H] 3.3k 180 0.1
R4042
OPEN Q4006
2SC2412K/QRS/-X

## C4073 ## L4008
L4202 SHORT
2SC3928A/QRS/-X

12u
R4048
B4002 0

L4002 R4204 C4204


10u SHORT ## 0

220p
X4001 R4050 1

OPEN
QAX0576 10k

R4052
QAX0579 R4202
Q4005 C4069 OPEN

## R4051
OPEN R4044 820p
470

R4203 10K
L4201 R4201

0