051-7099 M1

8
1
CK
APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
SCHEM,MLB,M1
ZONE
ECN
ENG
APPD
DESCRIPTION OF CHANGE
DATE
DATE
428208PRODUCTION RELEASED 03/04/06

?
03/03/2006
D
(.csa)
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
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Contents
Table of Contents
System Block Diagram
Power Block Diagram
BOM Configuration
Functional / ICT Test
Signal Aliases
CPU 1 OF 2-FSB
CPU 2 OF 2-PWR/GND
CPU Decoupling & VID
CPU MISC1-TEMP SENSOR
CPU ITP700FLEX DEBUG
NB CPU Interface
NB PEG / Video Interfaces
NB Misc Interfaces
NB DDR2 Interfaces
NB Power 1
NB Power 2
NB Grounds
NB (GM) Decoupling
NB Config Straps
SB: 1 OF 4
SB: 2 of 4
SB: 3 OF 4
SB: 4 OF 4
SB Decoupling
SB Misc
M1 SMBus Connections
DDR2 SO-DIMM Connector A
DDR2 SO-DIMM Connector B
Memory Active Termination
Memory Vtt Supply
DDR2 VRef
CLOCKS
Clock Termination
Mobile Clocking
PATA Connector
ETHERNET CONTROLLER
Ethernet Connector
Yukon Power Control
FIREWIRE CONTROLLER
FireWire Port Power
Date
Sync
N/A
(.csa)
Page
TABLE_TABLEOFCONTENTS_HEAD
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
11/16/2005
M42
11/16/2005
M42
(MASTER)
(MASTER)
10/07/2005
M42
10/12/2005
M42
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
11/16/2005
M38
09/08/2005
(M38)
11/16/2005
M38
11/16/2005
M38
11/16/2005
M42
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
10/12/2005
M42
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
10/12/2005
M42
(MASTER)
(MASTER)
(MASTER)
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
46
49
52
55
57
58
59
60
61
62
63
64
65
66
67
75
76
77
78
79
80
81
82
84
85
86
87
88
89
90
91
93
94
97
98
99
100
104
Date
Contents
Sync
FireWire Ports
Internal USB Connections
External USB Connector
Left I/O Board Connector
PCI-E Connections
SMC
SMC Support
LPC+ Debug Connector
Thermal Sensors
Current & Voltage Sensing
SPI BOOTROM
ALS Support
Fan Connectors
Sudden Motion Sensor (SMS)
TPM
IMVP6 CPU VCore Regulator
5V / 1.5V Power Supply
2.5V & 1.2V Regulators
1.8V Supply
3.3V / 1.05V Power Supplies
3.3V G3Hot Supply & Power Control
Power Aliases
PBus-In & Battery Connectors
ATI M56 PCI-E
GPU (M56) Core Supplies
ATI M56 Core Power
ATI M56 Frame Buffer I/F
GPU Straps
GDDR3 Frame Buffer A
GDDR3 Frame Buffer B
ATI M56 GPIO/DVO/Misc
ATI M56 Video Interfaces
Internal Display Connectors
External Display Connector
M1 Specific Connectors
LVDS Interface Pull-downs
Revision History
M1 Net Properties
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
10/07/2005
M38
(MASTER)
(MASTER)
07/20/2005
M42
(MASTER)
(MASTER)
(MASTER)
(MASTER)
11/16/2005
M42
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
11/16/2005
M38
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
N/A
N/A
(MASTER)
(MASTER)
(MASTER)
08/29/2005
(M42)
(MASTER)
(MASTER)
DIMENSIONS ARE IN MILLIMETERS
Apple Computer Inc.
METRIC
XX
X.XX
DRAFTER
Schematic / PCB #s
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
051-7099
SCHEM,MLB,M1
SCH
CRITICAL
820-1881
PCBF,MLB,M1
PCB
CRITICAL
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
X.XXX
BOM OPTION
TITLE
DO NOT SCALE DRAWING
SCHEM,MLB,M1
NONE
DRAWING
SIZE
TITLE=M1_MLB
ABBREV=DRAWING
LAST_MODIFIED=Fri Mar
3 15:00:30 2006
THIRD ANGLE PROJECTION
MATERIAL/FINISH
NOTED AS
APPLICABLE
DRAWING NUMBER
REV.
051-7099
D
SHT
OF
104
GDDR3
Frame Buffer
128MB/256MB
P.70-71
INVERTER
CONNECTOR
Core Duo
(Yonah)
CPU
THERMAL
SENSOR
P.10
ITP700FLEX
CPU Debug
Connector
P.11
479 BGA
P.7-9
P.74
D
J2800
LCD Panel
PWM
P.74,77
Dual-Channel LVDS
S-Video/Composite
DVI-I/DL Connector
w/TV-Out Support
FSB
ATI M56P
GPU
Lower Connector
PCIe x16
CH.A
945GM
NB
Dual-Channel TMDS
P.75
DDR2 SO-DIMM A
P.65-69,72-73
P.28
J2900
DDR2 SO-DIMM B
CH.B
DDR2 VTT
Upper Connector
& REGULATOR
1466UFCBGA
RJ45 (Ethernet)
Connector
ENET
Yukon Gig-E
Controller
P.38
1394a (FireWire)
Connector
P.42
Yukon Power
PCIe x1
PCI
P.40
ICH7-M
PCIe x1
USB
PCIe x1
P.44
HDD/IR/BT
Connector
P.76
P.32
DMI x4
P.41
Right USB 2.0
Connector
BUFFER
FW323-06 FireWire
Controller
Port Power
P.30-31
DDR2 VREF
P.12-20
P.39
P.37
FW
P.29
SB
SATA
Left I/O &

Audio Board
Connector
USB
USB
USB x2
Azalia (HD-Audio)
P.45
Camera
Connector
P.43
USB
Geyser KB /
TP Connector
P.43
USB
ODD
Connector
P.36
P.21-26
B
SMBus
PATA
66MHZ
16BITS
LPC 33MHZ
BootROM
SB SMBus
Temperature
Sensors
SMC SMBus
SMC
SMBus x5
LPC
Debug
Connector
P.56
P.49
P.57-64,66
System Block Diagram
ALS
P.53,76
SYNC_MASTER=N/A
SYNC_DATE=N/A
P.27
P.50
TPM
H8S/2116
P.27
P.33-34
Power
Supplies
SPI
P.52
CK410 Clock
Controller
609 BGA
SMS

P.55
Battery SMBus
Connector
Fan
Connectors
P.64
P.54
PWM/Tach
P.47-48

Analog
Sensors
SIZE
P.51
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7099
D
OF
104
U8000
ENABLE
J5500
LIO Flex
Connector
3.425
G3Hot
(LT3470)
PPDCIN_G3H
18.5V - 9V
Q7610
PP5V_S3
5.0V
PP3V42_G3H
3.425V
SMC_PM_G2_ENABLE
PM_SLP_S3_L
5V
1.5V
Q7615
U7600
Q3820
ENABLES
J8200
LIO Power
Connector
D
PM_SLP_S4_LS5V
5V/1.5V
S5/S0
PPBUS_G3H
12.6V - 9V
(LTC3728)
PP5V_S5
5.0V
PP5V_S0
5.0V
PP1V5_S0
1.5V
PP5V_S0_IDE_ODD
5V
PM_SLP_S3_LS5V
ODD_PWR_EN_L (SB GPIO14)
PGOOD
Q7945
NC
SMC_PM_G2_ENABLE
3.3V
ENABLES
PM_SLP_S4_LS5V
PP3V3_S5
3.3V
S5
PGOOD
Q7720
RSMRST_PWRGD
PM_SLP_S3_L
2.5V
S3
(LTC3411)
U7950
PP2V5_S3
2.5V
PP2V5_S0
2.5V
ENABLE
J5500
Inverter
PGOOD
1.05V
(ISL6269)
PM_SLP_S4_L
1.2V
ENABLE
IMVP_PWRGD_IN/ALL_SYS_PWRGD
PM_SLP_S3_L
PP1V8_S3
1.8V
S3
PP1V2_S3
1.2V
PP1V2_S0
1.2V
(LTC3412)
U8500
PGOOD
ENABLE
PM_SLP_S3_LS5V_L
NC
GPU VCore
S0
PGOOD
NC
Q7770
PGOOD
U7800
PM_SLP_S3_LS5V_L
NC
PM_SLP_S3BATT
U7750
ENABLE
PP1V05_S0
1.05V
S0
Connector
1.8V
S3
(ISL6269)
PM_SLP_S3BATT
PM_SLP_S3BATT
U7700
ENABLE
(ISL6269)
PPVCORE_S0_CPU
1.25V - 0.8V
VR_PWRGOOD_DELAY
PP3V3_S3AC
3.3V
ENABLE
U7530
CPU VCore
S0
(ISL6262)
"IMVP6"
PGOOD
PP3V3_S3
3.3V
U7900
IMVP_VR_ON
IMVP_PWRGD_IN
Q4300
PPVCORE_S0_GPU
1.1V - 0.95V
Q7947
PP3V3_S0
3.3V
(ISL6269)
PGOOD
PM_SLP_S3_L
NC
U3100
Q7845
0.9V (Vtt)
S0
(BD3533FVM)
Power Block Diagram
PM_SLP_S3_LS5V
ENABLE
PP0V9_S0
0.9V
SYNC_MASTER=N/A
Q4565
PP1V8_S0
1.8V

PPBUS_S5_FWPORT

12.6V - 9V

SIZE
APPLE COMPUTER INC.
PM_SLP_S3_LS5V_L
SYNC_DATE=N/A
SHT
NONE
REV.
051-7099
SCALE
FWPWR_EN_L
DRAWING NUMBER
D
OF
104
"Better" BOM
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
630-7569
PCBA,1.83GHZ,128VRAM_M1_MBPRO_15
EEE_VHT,M1_COMMON,CPU_1_83GHZ,VRAM_SAM128
TABLE_BOMGROUP_ITEM
"Best" BOM
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
630-7570
EEE_VHU,M1_COMMON,CPU_2_0GHZ,VRAM_SAM256
TABLE_BOMGROUP_ITEM
BOM
D "CTO"
BOM NUMBER
TABLE_BOMGROUP_HEAD
BOM NAME
BOM OPTIONS
TABLE_BOMGROUP_ITEM
630-7571
EEE_VHV,M1_COMMON,CPU_2_16GHZ,VRAM_SAM256
BOMOPTION Groups
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
M1_COMMON
ALTERNATE,COMMON,M1_COMMON1,M1_COMMON2,M1_COMMON3
M1_COMMON1
BOOTROM_DEVEL,ENET_LOM_DISABLE,ENETPWR_S3AC,GPU_BB_CTL,GPUTHM_A_GPU,HSTHMSNS_HAS
M1_COMMON2
ITP,INVERTER_BUF,KBDLED_HAS,LPCPLUS,LVDS_PD,MEMVREF_S3,MEMVTT_EN_PU
M1_COMMON3
RTUSB_ESD,SMC_PRGRM,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU
VRAM_HY128
GPU_MEM_HYNIX,VRAM_128_HYNIX
VRAM_SAM128
VRAM_128_SAMSUNG
VRAM_HY256
GPU_MEM_256M,GPU_MEM_HYNIX,VRAM_256_HYNIX
VRAM_SAM256
GPU_MEM_256M,VRAM_256_SAMSUNG
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Bar Code Label / EEE #s

C
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
826-4393
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:VHT]
CRITICAL
BOM OPTION
EEE_VHT
M1,1.83GHZ,SAM128
826-4393
[EEE:VHU]
CRITICAL
EEE_VHU
M1,2.0GHZ,SAM256
826-4393
[EEE:VHV]
CRITICAL
EEE_VHV
M1,2.16GHZ,SAM256
CRITICAL
Module Parts
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
333S0354
IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA
U8900,U8950,U9000,U9050
CRITICAL
VRAM_128_SAMSUNG
333S0350
U8900,U8950,U9000,U9050
CRITICAL
VRAM_256_SAMSUNG
333S0358
U8900,U8950,U9000,U9050
CRITICAL
VRAM_128_HYNIX
333S0351
U8900,U8950,U9000,U9050
CRITICAL
VRAM_256_HYNIX
337S3282
IC,YDC,CO,1.83G,31W,667M,2M,479BGA
U0700
CRITICAL
CPU_1_83GHZ
337S3267
U0700
CRITICAL
CPU_2_0GHZ
337S3268
U0700
CRITICAL
CPU_2_16GHZ
341S1873
IC,EFI,BOOTROM DEVELOPMENT (NEW),M1
U6301
CRITICAL
BOOTROM_DEVEL
338S0274
IC,SMC,HS8/2116
U5800
CRITICAL
SMC_BLANK
341S1875
IC,PRGRM,SMC (NEW),M1
U5800
CRITICAL
SMC_PRGRM
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
338S0268
IC,FW32306,1394A LINK,BGA,129P
U4400
CRITICAL
338S0269
IC,945GM,SOUTHBRIDGE
U1200
CRITICAL
338S0270
IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO
U4101
CRITICAL
338S0309
IC,ATI,M56P,GRPHSCTRL,880BGA,LF
U8400
CRITICAL
341S1789
IC, TPM, 28-PIN TSSOP
U6700
CRITICAL
341S1797
IC,EEPROM,SERIAL IIC,8KBIT,SO8
U4102
CRITICAL
343S0385
IC,SB,652BGA
U2100
CRITICAL
353S1235
IC,CPU VOLTAGE REGULATOR,IMVP,TWO PHASE
U7530
CRITICAL
359S0101
IC,CY28445-5,CLOCK GEN,68PIN QFN
U3301
CRITICAL
BOM OPTION
Alternate Parts
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
128S0094
128S0095
BOM OPTION
REF DES
COMMENTS:
128S0060
ALL
330uF,2V,9MOHM,D2
128S0060
ALL
330uF,2V,6MOHM,D2
128S0081
128S0061
ALL
150uF,6.3V,25MOHM,C2
128S0077
128S0086
ALL
7mOhm alt for 8mOhm
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
BOM Configuration
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
OF
D
104
Functional Test Points

Power Supply NO_TESTs
NO_TEST
Fan Connectors
EXPOSED_VIA
TRUE
TRUE
IMVP6_RBIAS
IMVP6_COMP
TRUE
TRUE
P5VS5_RUNSS
P1V5S0_RUNSS
TRUE
TRUE
P2V5S3_MODE
P2V5S3_SHDNRT
TRUE
TRUE
P1V2S3_RT
P1V2S3_RUNSS
TRUE
TRUE
P1V8S3_COMP
P1V8S3_FSET
TRUE
TRUE
P3V3S5_COMP
P3V3S5_FSET
TRUE
TRUE
P1V05S0_COMP
P1V05S0_FSET
TRUE
P3V42G3H_FB
TRUE
TRUE
GPUVCORE_COMP
GPUVCORE_FSET
TRUE
GPUBBP_ADJ
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
58 62
59
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
54 63
54
54
54
60
60
TRUE
TRUE
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
LPC_AD<0>
LPC_AD<1>
LPC_FRAME_L
PM_CLKRUN_L
BOOT_LPC_SPI_L
SMC_TMS
DEBUG_RST_L
SMC_TRST_L
SMC_TDO
SMC_MD1
SMC_TX_L
FWH_INIT_L
PCI_CLK_PORT80_LPC
LPC_AD<2>
LPC_AD<3>
INT_SERIRQ
PM_SUS_STAT_L
SMC_TDI
SMC_TCK
SMC_RST_L
SMC_NMI
SMC_RX_L
SV_SET_UP
49 63
49 63
61
61
61
62
66
66
7 12 79
7 12 79
7 12 79
7 12 79
7 12 79
7 12 79
7 12 79
7 12 79
7 12 79
7 12 79
21 47 49 56
21 47 49 56
21 47 49 56
22 47 49
47 48 49
26 49
47 49
47 48 49
47 49
47 48 49
21 48 49
34 49
21 47 49 56
21 47 49 56
23 47 49 56
23 47 48 49 56
47 48 49
47 48 49
47 48 49
47 49
47 48 49
23 49
7 12 79
Left ALS Connector
7 12 79
FUNC_TEST
7 12 79
=PP3V3_S3_LTALS
ALS_GAIN
LTALS_OUT
GND
TRUE
TRUE
TRUE
TRUE
Misc EXPOSED_VIA Nets
63 76
6 47 76
53 76
Camera Connector
EXPOSED_VIA
FUNC_TEST
DMI_N2S_P<1..0>
DMI_N2S_N<1..0>
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
=PP5V_S3_CAMERA
=USB2_CAMERA_N
=USB2_CAMERA_P
=SMBUS_ATS_SDA
=SMBUS_ATS_SCL
GND
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
14 22
14 22
21 34
21 34
43 63
6 43
6 43
27 43
27 43
Thermal Diode Connectors

FUNC_TEST
HSTHMSNS_DX_P
HSTHMSNS_DX_N
RSFSTHMSNS_D_P
RSFSTHMSNS_D_N
TRUE
TRUE
TRUE
TRUE
27 64
64
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
=PP1V5_S0_LIO
=PPDCIN_G3H_LIO
=PP5V_S5_LIO
=PP3V42_G3H_LIO
PP5V_S0_AUDIO_PWR
PP5V_S0_AUDIO
GND_AUDIO_PWR
GND_AUDIO
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
ACZ_SDATAIN<0>
ACZ_SDATAOUT
ACZ_BITCLK
ACZ_RST_L
EXCARD_OC_L
LTUSB_OC_L
LIO_BATT_ISENSE
SMC_SYS_ISET
SMC_BATT_ISET
SMC_BATT_CHG_EN
SMC_BC_ACOK
SMC_ADAPTER_EN
LIO_P3V3S0_EN_L
LIO_DCIN_ISENSE
LIO_P3V3S3_EN
SMC_BATT_TRICKLE_EN_L
SYS_ONEWIRE
MINI_CLKREQ_L
SMC_EXCARD_CP
EXCARD_CLKREQ_L
SMC_EXCARD_PWR_EN
LIO_PLT_RESET_L
ACZ_SYNC
=USB2_LT_N
=USB2_LT_P
=USB2_EXCARD_N
=USB2_EXCARD_P
=PCIE_EXCARD_R2D_N
=PCIE_EXCARD_R2D_P
=PCIE_EXCARD_D2R_N
=PCIE_EXCARD_D2R_P
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
=PCIE_MINI_R2D_N
=PCIE_MINI_R2D_P
=PCIE_MINI_D2R_N
=PCIE_MINI_D2R_P
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
=SMBUS_LIO_SMC_SCL
=SMBUS_LIO_SMC_SDA
=SMBUS_LIO_SB_SCL
=SMBUS_LIO_SB_SDA
PCIE_WAKE_L
45 63
45 63
45 63
45 63
45
45
45
45
23 40 47 49 56
7 12 79
7 12 79
27 64
FUNC_TEST
FUNC_TEST
61
47 48 64
Left I/O Data Connector
39 59
SMC_BS_ALRT_L
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
GND_BATT
54
59
EXPOSED_VIA property indicates that the net

should have a via with 10-mil soldermask
opening for use as engineering probe point.
TRUE
TRUE
TRUE
TRUE
FAN_RT_PWM
FAN_RT_TACH
59
EXPOSED_VIA
TRUE
FAN_LT_PWM
FAN_LT_TACH
FUNC_TEST property removed

since these test points
are not on the proper side
for Functional Test points.
58 62
66
FSB_A_L<31..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>
FSB_BNR_L
FSB_BREQ0_L
FSB_D_L<63..0>
FSB_DBSY_L
FSB_DINV_L<3..0>
FSB_DRDY_L
FSB_DSTBN_L<3..0>
FSB_DSTBP_L<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<4..0>
FUNC_TEST
=PP5V_S0_FAN_LT
57
CPU FSB NO_TESTs

NO_TEST
Battery Digital Connector
FUNC_TEST
57
21 45 79
21 45 79
21 45 79
21 45 79
6 45 48
6 45
45 51
45 47
45 47
45 47 48
45 47 48
41 45 47 48
45 62
45 51
45 62
45 47 48
45 47 48
34 45
45 47 48
34 45
45 47
26 45
21 45 79
6 45
6 45
6 45
6 45
45 46
45 46
45 46
45 46
34 45
34 45
45 46
45 46
45 46
45 46
34 45
34 45
27 45
27 45
27 45
27 45
23 37 45
50
50
Left I/O Power Connector
50
50
FUNC_TEST
TRUE
TRUE
Other Func Test Points

FUNC_TEST
=PPBUS_G3H_LIO_CONN
GND
63 64
Request for at least 10 GND test points
TRUE
=PP1V05_S0_REG
TRUE
TRUE
PM_SYSRST_L
SMC_ONOFF_L
NOTE: 10 additional GND test points are

called out separately in these notes.
51 61 63
23 26 47
43 47 48 51
Current Sense Calibration

FUNC_TEST
2 TPs per
TRUE
TRUE
ISENSE_CAL_EN
=PP5V_S0_ISENSECAL
TRUE
TRUE
TRUE
TRUE
=PP1V8_S3_REG
=PP1V5_S0_REG
PPVCORE_S0_GPU
PPVCORE_S0_CPU
Functional / ICT Test

SYNC_MASTER=N/A
51 60 63
58 63
SYNC_DATE=N/A
63

63
GND
TRUE
8 TPs, 2 with each of above TP pairs

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
OF
D
104
USB Port "A" (Debug Port) = Right USB 2.0 Port
NC_CPU_A32_L
TP_CPU_A32_L
NC_MEM_A_A<15..14>
TP_CPU_A33_L
NC_MEM_B_A<15..14>
TP_CPU_A34_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_A33_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_A34_L
28
MEM_B_A<15..14>
29
NB_CFG<4..3>
14
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_NB_CFG<4..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
MEM_A_A<15..14>
MAKE_BASE=TRUE
NC_CPU_A35_L
TP_CPU_A35_L
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_NB_CFG<6>
NB_CFG<6>
MAKE_BASE=TRUE
NC_CPU_A36_L
TP_CPU_A36_L
TP_CPU_A37_L
TP_CPU_A38_L
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_NB_CFG<8>
NB_CFG<8>
NB_CFG<11..10>
MAKE_BASE=TRUE
NC_CPU_A38_L
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_NB_CFG<15..14>
NB_CFG<15..14>
MAKE_BASE=TRUE
NC_CPU_A39_L
TP_CPU_A39_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_APM0_L
NC_CPU_APM1_L
TP_CPU_APM0_L
TP_CPU_APM1_L
TP_CPU_EXTBREF
TP_CPU_HFPLL
ALS_GAIN
=RTALS_GAIN
53
MAKE_BASE=TRUE
TP_NB_CFG<17>
=USB2_RT_N
44
=RTUSB_OC_L
14
NB_CFG<17>
TP_NB_CFG<13..12>
NB_CFG<13..12>
USB2_RT_N
RTUSB_OC_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_HFPLL
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_SPARE0
TP_CPU_SPARE0
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_SPARE1
TP_CPU_SPARE1
43
=USB_TRACKPAD_P
=USB_TRACKPAD_N
NC_CPU_SPARE2
NC_CPU_SPARE4
USB_TRACKPAD_P
USB_TRACKPAD_N
UNUSED_USB_B_OC_L
22
USB_B_N
22
USB_B_OC_L
22
MAKE_BASE=TRUE
NC_ENET_CTRL12
ENET_CTRL12
NC_ENET_CTRL25
ENET_CTRL25
USB Port "C" = Left USB 2.0 Port
37
45 5
=USB2_LT_P
45 5
=USB2_LT_N
USB2_LT_P
USB_C_P
22
USB_C_N
22
USB_C_OC_L
22
USB_D_P
22
USB_D_N
22
USB_D_OC_L
22
MAKE_BASE=TRUE
37
MAKE_BASE=TRUE
NO_TEST=TRUE
USB2_LT_N
MAKE_BASE=TRUE
14
LTUSB_OC_L
MAKE_BASE=TRUE
USB Port "D" = Camera
14
43 5
=USB2_CAMERA_P
43 5
=USB2_CAMERA_N
USB2_CAMERA_P
MAKE_BASE=TRUE
14
USB2_CAMERA_N
USB Port "E" = ExpressCard
23
TP_SB_XOR_T5
21
TP_SB_XOR_U5
21
TP_SB_XOR_V3
21
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SB_XOR_V3
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_SB_XOR_V4
NC_SB_XOR_V4
=USB2_EXCARD_P
45 5
=USB2_EXCARD_N
TP_SB_XOR_W3
MAKE_BASE=TRUE
NO_TEST=TRUE
USB2_EXCARD_N
USB_E_P
22
USB_E_N
EXCARD_OC_L
22
USB_E_OC_L
22
MAKE_BASE=TRUE
USB Port "F" = IR Receiver
ENET_LOM_DISABLE
R0600
21
22
NC_SB_XOR_W3
USB2_EXCARD_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
48 45 5
MAKE_BASE=TRUE
NO_TEST=TRUE
45 5
Ethernet Power Management Support
NC_SB_XOR_U5
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
SUS_CLK_SB
NC_SB_XOR_T5
USB_B_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_CPU_SPARE4
22
MAKE_BASE=TRUE
TP_SB_SUS_CLK
TP_CPU_SPARE2
22
USB_A_OC_L
MAKE_BASE=TRUE
UNUSED_USB_D_OC_L
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
22
USB_A_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_CPU_EXTBREF
USB_A_P
MAKE_BASE=TRUE
43
14
14
USB2_RT_P
MAKE_BASE=TRUE
USB Port "B" = Trackpad (Geyser)
NOTE: NB_CFG<13..12> require test access
MAKE_BASE=TRUE
NO_TEST=TRUE
44
45 5
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
47
=USB2_RT_P
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_NB_CFG<11..10>
MAKE_BASE=TRUE
NO_TEST=TRUE
SMC_RSTGATE_L
MAKE_BASE=TRUE
76 47 5
MAKE_BASE=TRUE
NC_CPU_A37_L
TP_SMC_RSTGATE_L
44
IN
SB_GPIO30
37
ENET_LOM_DIS_L
OUT
76
=USB_IR_P
76
=USB_IR_N
USB_IR_N
USB_F_P
22
USB_F_N
22
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
21
USB_IR_P
MAKE_BASE=TRUE
USB Port "G" = Bluetooth (M13P)
NOTE: BOM options "USB_G_OC_PU" and

"ENET_LOM_DISABLE" are mutually-exclusive.
76
=USB_BT_P
76
=USB_BT_N
USB_BT_P
USB_G_P
22
USB_G_N
22
MAKE_BASE=TRUE
USB_BT_N
MAKE_BASE=TRUE
USB Port "H" = Reserved (PCI-E Mini Card)

TP_USB2_HP
USB_H_P
22
USB_H_N
22
MAKE_BASE=TRUE
TP_USB2_HN
MAKE_BASE=TRUE
Trace deleted to make room for other diffpairs over RAM connector.
Chassis connection to be made at the mounting hole northwest of the DVI connector
ZT0600
HOLE-VIA-P5RP25
1
GND_CHASSIS_DVI_TOP
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MAKE_BASE=TRUE
=GND_CHASSIS_DVI2
=GND_CHASSIS_DVI4
75
75
Chassis connection to be made at the mounting hole southwest of the USB connector
ZT0601
HOLE-VIA-P5RP25
1
GND_CHASSIS_DVI_BOT
VOLTAGE=0V
MAKE_BASE=TRUE
=GND_CHASSIS_DVI1
=GND_CHASSIS_DVI3
=GND_CHASSIS_DVI5
=GND_CHASSIS_ENET
=GND_CHASSIS_FW_EMI
=GND_CHASSIS_FW_PORT1
=GND_CHASSIS_RTUSB
75
75
75
38
42
42
44
Signal Aliases
Chassis connection to be made at the mounting hole east of the LVDS connector
ZT0602
HOLE-VIA-P5RP25
1
SYNC_MASTER=N/A
GND_CHASSIS_LVDS
VOLTAGE=0V
MAKE_BASE=TRUE
=GND_CHASSIS_LCD1
=GND_CHASSIS_LCD2
=GND_CHASSIS_LCD3
=GND_CHASSIS_LCD4
SYNC_DATE=N/A
74
74

74
74

GND_CHASSIS_INVERTER
VOLTAGE=0V
MAKE_BASE=TRUE
SH0600 2
OG-503040
SHLD-SM-LF
SIZE
=GND_CHASSIS_INVERTER
74
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
OF
D
104
OMIT
U0700
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
79 12 5
79 12 5
79 12 5
79 12 5
79 12 5
79 12 5
79 12 5
79 12 5
IO
79 12 5
79 12 5
79 21
21
79 21
79 21
79 21
79 21
79 21
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
OUT
IN
IN
IN
IN
IN
6
6
6
6
6
6
6
6
6
6
FSB_REQ_L<0>K3 REQ0*
FSB_REQ_L<1>H2 REQ1*
FSB_REQ_L<2>K2 REQ2*
FSB_REQ_L<3>J3 REQ3*
FSB_REQ_L<4>L5 REQ4*
FSB_A_L<17> Y2 A17*
FSB_A_L<18> U5 A18*
FSB_A_L<19> R3 A19*
FSB_A_L<20> W6 A20*
FSB_A_L<21> U4 A21*
FSB_A_L<22> Y5 A22*
FSB_A_L<23> U2 A23*
FSB_A_L<24> R4 A24*
FSB_A_L<25> T5 A25*
FSB_A_L<26> T3 A26*
FSB_A_L<27> W3 A27*
FSB_A_L<28> W5 A28*
FSB_A_L<29> Y4 A29*
FSB_A_L<30> W2 A30*
FSB_A_L<31> Y1 A31*
FSB_ADSTB_L<1>
V4 ADSTB1*
CPU_A20M_L A6 A20M*
CPU_FERR_L A5 FERR*
CPU_IGNNE_L C4 IGNNE*
CPU_STPCLK_LD5 STPCLK*
CPU_INTR
C6 LINT0
CPU_NMI
B4 LINT1
CPU_SMI_L
A3 SMI*
TP_CPU_A32_L
AA1 RSVD1
TP_CPU_A33_L
AA4 RSVD2
TP_CPU_A34_L
AB2 RSVD3
TP_CPU_A35_L
AA3 RSVD4
TP_CPU_A36_LM4 RSVD5
TP_CPU_A37_LN5 RSVD6
TP_CPU_A38_LT2 RSVD7
TP_CPU_A39_LV3 RSVD8
TP_CPU_APM0_L
B2 RSVD9
TP_CPU_APM1_L
C3 RSVD10
TP_CPU_HFPLL
B25 RSVD11
BR0*
79 12 5
F1
79 12 5
INIT*
LOCK*
H4
RESET*
RS0*
B1
F3
F4
G3
G2
RS1*
RS2*
TRDY*
HIT*
HITM*
79 12
H5
F21
E1
D20
B3
IERR*
79 12 5
G6
E4
79 12
79 12 5
79
79 21
79 12 5
79 12 11
79 12
79 12
79 12
79 12
79 12 5
79 12 5
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
FSB_BREQ0_L
FSB_IERR_L
CPU_INIT_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
FSB_HIT_L
FSB_HITM_L
=PP1V05_S0_CPU
7 8 9 11 63
IO
R0702
54.9
IO
IO
1%
1/16W
MF-LF
2402
IO
IO
IO
IO
PLACE TESTPOINT ON
FSB_IERR_L WITH A GND
0.1" AWAY
IN
IO
IN
IN
IN
IN
=PP1V05_S0_CPU
IN
7 8 9 11 63
IO
IO
R0703
54.9
1
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
PROCHOT*
THERMDA
THERMDC
THERMTRIP*
BCLK0
BCLK1
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
D21
A24
A25
C7
A22
A21
79 11
79 11
79 11
79 11
79 11
79 11
11 7
11 7
11
11 7
11
26 11
48
10
10
48 21 14
34
34
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
IO
OMIT
1%
1/16W
MF-LF
2402
IO
IO
U0700
YONAH D32*
FSB_D_L<0> E22 D0*
CPU
FSB_D_L<1> F24 D1*
D33*
BGA
FSB_D_L<2> E26 D2*
D34*
(2 OF 4)
FSB_D_L<3> H22 D3*
D35*
1R0704
FSB_D_L<4>
F23 D4*
D36*
68
FSB_D_L<5>
G25 D5*
D37*
5%
1/16W
FSB_D_L<6>
E25 D6*
D38*
MF-LF
2402
FSB_D_L<7> E23 D7*
D39*
FSB_D_L<8>
K24 D8*
D40*
CPU_PROCHOT_L TO SMC
FSB_D_L<9> G24 D9*
CPU_PROCHOT_L
D41*
AND
CPU
VR
TO
INFORM
CPU_THERMD_P
FSB_D_L<10> J24 D10*
D42*
CPU IS HOT
CPU_THERMD_N
FSB_D_L<11> J23 D11*
D43*
FSB_D_L<12>
H26
D44*
D12*
PM_THRMTRIP_L
FSB_D_L<13> F26 D13*
D45*
FSB_D_L<14> K22 D14*
D46*
PM_THRMTRIP#
FSB_D_L<15>
H25 D15*
D47*
SHOULD CONNECT TO
FSB_CLK_CPU_P
FSB_DSTBN_L<0>
H23 DSTBN0*
DSTBN2*
ICH7-M
AND
GMCH
FSB_CLK_CPU_N
FSB_DSTBP_L<0>
G22 DSTBP0*
DSTBP2*
WITHOUT T-ING (NO
FSB_DINV_L<0>
J26 DINV0*
DINV2*
STUB)
FSB_D_L<16> N22 D16*
D48*
FSB_D_L<17> K25 D17*
D49*
FSB_D_L<18>
P26 D18*
D50*
TP_CPU_EXTBREF
FSB_D_L<19> R23 D19*
D51*
FSB_D_L<20> L25 D20*
D52*
TP_CPU_SPARE0
FSB_D_L<21> L22 D21*
D53*
TP_CPU_SPARE1 SPARE[7-0],HFPLL:
FSB_D_L<22> L23 D22*
D54*
TP_CPU_SPARE2 ROUTE TO TP VIA AND
FSB_D_L<23> M23 D23*
D55*
TP_CPU_SPARE3 PLACE GND VIA W/IN 1000 MILS
FSB_D_L<24> P25 D24*
D56*
TP_CPU_SPARE4
FSB_D_L<25> P22 D25*
D57*
TP_CPU_SPARE5
FSB_D_L<26> P23 D26*
D58*
TP_CPU_SPARE6
FSB_D_L<27> T24 D27*
D59*
TP_CPU_SPARE7
FSB_D_L<28> R24 D28*
D60*
=PP1V05_S0_CPU
FSB_D_L<29> L26 D29*
D61*
FSB_D_L<30> T25 D30*
D62*
FSB_D_L<31> N24 D31*
D63*
1R0705
FSB_DSTBN_L<1>
M24 DSTBN1*
DSTBN3*
1K
FSB_DSTBP_L<1>
N25 DSTBP1*
1%
DSTBP3*
1/16W
FSB_DINV_L<1>
M26 DINV1*
MF-LF
DINV3*
2402
CPU_GTLREF
AD26 GTLREF
COMP0
IO
79 12 5
IO
79 12 5
IO
IN
79 12 5
IO
IN
79 12 5
IO
IO
IO
79 12 5
OUT
IN
IO
IN
79 12 5
IO
79 12 5
IO
OUT
79 12 5
IO
79 12 5
IO
OUT
79 12 5
IO
OUT
79 12 5
IO
OUT
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
IN
79 12 5
IO
IN
79 12 5
IO
OUT
79 12 5
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
T22
D2
F6
D3
C1
AF1
D22
C23
C24
B
11 7
XDP_TMS
R0720
54.9
1
11 7
XDP_TCK
79 12 5
IO
79 12 5
IO
IO
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
79 12 5
IO
7 8 9 11 63
79
LAYOUT NOTE: 0.5"

R0706
CPU_TEST1
2.0K
1%
1/16W
MF-LF
2402
OUT 34
R0721
54.9
OUT 34
OUT
1%
402
11 7
IO
79 12 5
79 12 5
79 12 5
1%
402
XDP_TDI
IO
63 11 9 8 7
=PP1V05_S0_CPU
IO
79 12 5
34
A2 NC
MAX LENGTH
C26 TEST1
CPU_TEST2
CPU_BSEL<0>
CPU_BSEL<1>
CPU_BSEL<2>
NOSTUFF
D25
B22
B23
C21
TEST2
MISC
COMP1
COMP2
COMP3
DPRSTP*
BSEL0
DPSLP*
BSEL1
BSEL2
DPWR*
PWRGOOD
SLP*
PSI*
R0730
0
R0722
54.9
1
DATA GRP2
79 12 5
DRDY*
DBSY*
79 12 5
DATA GRP3
IO
BPRI*
DEFER*
H1
E2
G5
DATA GRP0
IO
79 12 5
ADS*
BNR*
DATA GRP1
IO
79 12 5
ADDR GROUP0
IO
79 12 5
CONTROL
IO
XDP/ITP SIGNALS
IO
79 12 5
THERM
79 12 5
79 12 5
HCLK
IO
FSB_A_L<3> J4 A3*
YONAH
FSB_A_L<4> L4 A4*
CPU
FSB_A_L<5> M3 A5*
BGA
FSB_A_L<6> K5 A6*
(1 OF 4)
FSB_A_L<7> M1 A7*
FSB_A_L<8> N2 A8*
FSB_A_L<9> J1 A9*
FSB_A_L<10> N3 A10*
FSB_A_L<11> P5 A11*
FSB_A_L<12> P2 A12*
FSB_A_L<13> L1 A13*
FSB_A_L<14> P4 A14*
FSB_A_L<15> P1 A15*
FSB_A_L<16> R1 A16*
FSB_ADSTB_L<0>
L2 ADSTB0*
ADDR GROUP1
IO
79 12 5
RESERVED
79 12 5
AA23
AB24
V24 79
V26 79
W25 79
U23 79
U25 79
U22 79
AB25
W22 79
Y23 79
AA26
Y26 79
Y22 79
AC26
AA24
W24 79
Y25 79
V23 79
79
12 5
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
79
12 5
79
12 5
79
12 5
R26
U26
U1
V1
E5
B5
D24
D6
D7
AE6
79
12 5
12 5
12 5
12 5
12 5
12 5
12 5
79
12 5
12 5
12 5
79
12 5
12 5
12 5
79
12 5
79
12 5
12 5
12 5
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
12 5
79
79
79
79
57 21
79 21
79 12
79 21
12
57
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTBN_L<2>
FSB_DSTBP_L<2>
FSB_DINV_L<2>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTBN_L<3>
FSB_DSTBP_L<3>
FSB_DINV_L<3>
CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_SLPCPU_L
CPU_PSI_L
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
LAYOUT NOTE:
COMP0,2 CONNECT WITH
TRACE LENGTH SHORTER
COMP1,3 CONNECT WITH
TRACE LENGTH SHORTER
IO
IO
IO
IO
ZO=27.4OHM, MAKE
THAN 0.5".
ZO=55OHM, MAKE
THAN 0.5".
IO
R0716
27.4
IO
IO
IO
IO
IO
IO
IO
2
1% 402
R0718
27.4
IO
IN
402
R0717
54.9
1
R0719
54.9
1
1%
402
IN
IN
IN
IN
IN
402
NOSTUFF
1R0707
R0712
51
1K
1%
402
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9
CPU 1 OF 2-FSB
WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50
SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM
TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)
SYNC_MASTER=M42
SYNC_DATE=11/16/2005

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
OF
D
104
OMIT
=PPVCORE_S0_CPU
OMIT
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
U0700
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_68
VCC_69
YONAH VCC_70
CPU VCC_71
BGA
(3 OF 4)
VCC_72
VCC_6
VCC_73
VCC_7
VCC_8
VCC_74
VCC_75
VCC_9
VCC_76
VCC_10
VCC_11
VCC_77
VCC_78
VCC_12
VCC_13
VCC_79
VCC_80
VCC_14
VCC_81
VCC_15
VCC_16
VCC_82
VCC_83
VCC_17
VCC_84
VCC_18
VCC_19
VCC_85
VCC_86
VCC_20
VCC_87
VCC_21
VCC_22
VCC_88
VCC_89
VCC_23
VCC_24
VCC_90
VCC_91
VCC_25
VCC_92
VCC_26
VCC_27
VCC_93
VCC_94
VCC_28
VCC_95
VCC_29
VCC_30
VCC_96
VCC_97
VCC_31
VCC_98
VCC_32
VCC_33
VCC_99
VCC_100
VCC_34
VCC_35
VCCP_1
VCC_36
VCCP_2
VCC_37
VCC_38
VCCP_3
VCCP_4
VCC_39
VCCP_5
VCC_40
VCC_41
VCCP_6
VCCP_7
VCC_42
VCCP_8
VCC_43
VCC_44
VCCP_9
VCCP_10
VCC_45
VCC_46
VCCP_11
VCCP_12
VCC_47
VCCP_13
VCC_48
VCC_49
VCCP_14
VCCP_15
VCC_50
VCCP_16
VCC_51
VCC_52
VCC_53
VCCA
VCC_54
VCC_55
VID0
VCC_56
VCC_57
VID1
VID2
VCC_58
VID3
VCC_59
VCC_60
VID4
VID5
VCC_61
VID6
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
AD6
AF5
AE5
AF4
AE3
AF2
AE2
A4
A8
A11
A14
A16
A19
A23
A26
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
8 9 51 63
(CPU CORE POWER)
=PP1V05_S0_CPU
7 9 11 63
(CPU IO POWER 1.05V)
=PP1V5_S0_CPU
VCCA=1.5 ONLY
(CPU INTERNAL PLL POWER 1.5V)

CPU_VID<0>
OUT
CPU_VID<1>
OUT
CPU_VID<2>
OUT
CPU_VID<3>
OUT
CPU_VID<4>
OUT
CPU_VID<5>
OUT
CPU_VID<6>
OUT
9 79
9 79
9 79
9 79
9 79
SUPPLY=PPVCORE_S0_CPU
VID FOR CPU POWER

IF NO USE, NEED PULL-UP OR
PULL-DOWN
1
8 9 51 63
R0802
100
9 79
1%
1/16W
MF-LF
9 79
2402
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCCSENSE
AF7
VCC_67
VSSSENSE
AE7
CPU_VCCSENSE_P
OUT
57 79
CPU_VCCSENSE_N
OUT
57 79
R0803
1
LAYOUT NOTE: CONNECT R0803100
1%
TO TP_VSSSENSE WITH NO
1/16W
MF-LF
STUB.
2402
LAYOUT NOTE:
PROVIDE A TEST POINT (WITH NO STUB)
TO CONNECT A DIFFERENCTIAL PROBE
LAYOUT NOTE:
BETWEEN VCCSENSE AND VSSSENSE AT THE
CPU_VCCSENSE_P/CPU_VCCSENSE_N USE
LOCATION WHERE THE TWO 54.9 OHM
ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.
RESISTORS TERMINATE THE 55 OHM
TRANSMISSION LINE
LAYOUT NOTE:
VCCSENSE AND VSSSENSE LINES
SHOULD BE OF EQUAL LENGTH
U0700
VSS_1
VSS_82
VSS_2
YONAH VSS_83
CPU VSS_84
VSS_85
VSS_3
VSS_4
VSS_5
BGA
(4 OF 4)
VSS_86
VSS_6
VSS_7
VSS_87
VSS_88
VSS_8
VSS_9
VSS_89
VSS_90
VSS_10
VSS_91
VSS_11
VSS_12
VSS_92
VSS_93
VSS_13
VSS_94
VSS_14
VSS_15
VSS_95
VSS_96
VSS_16
VSS_97
VSS_17
VSS_18
VSS_98
VSS_99
VSS_19
VSS_20
VSS_100
VSS_101
VSS_21
VSS_102
VSS_22
VSS_23
VSS_103
VSS_104
VSS_24
VSS_105
VSS_25
VSS_26
VSS_106
VSS_107
VSS_27
VSS_108
VSS_28
VSS_29
VSS_109
VSS_110
VSS_30
VSS_31
VSS_111
VSS_112
VSS_32
VSS_113
VSS_33
VSS_34
VSS_114
VSS_115
VSS_35
VSS_116
VSS_36
VSS_37
VSS_117
VSS_118
VSS_38
VSS_119
VSS_39
VSS_40
VSS_120
VSS_121
VSS_41
VSS_42
VSS_122
VSS_123
VSS_43
VSS_124
VSS_44
VSS_45
VSS_125
VSS_126
VSS_46
VSS_127
VSS_47
VSS_48
VSS_128
VSS_129
VSS_49
VSS_130
VSS_50
VSS_51
VSS_131
VSS_132
VSS_52
VSS_53
VSS_133
VSS_134
VSS_54
VSS_135
VSS_55
VSS_56
VSS_136
VSS_137
VSS_57
VSS_138
VSS_58
VSS_59
VSS_139
VSS_140
VSS_60
VSS_141
VSS_61
VSS_62
VSS_142
VSS_143
VSS_63
VSS_64
VSS_144
VSS_145
VSS_65
VSS_146
VSS_66
VSS_67
VSS_147
VSS_148
VSS_68
VSS_149
VSS_69
VSS_70
VSS_150
VSS_151
VSS_71
VSS_152
VSS_72
VSS_73
VSS_153
VSS_154
VSS_74
VSS_75
VSS_155
VSS_156
VSS_76
VSS_157
VSS_77
VSS_78
VSS_158
VSS_159
VSS_79
VSS_160
VSS_80
VSS_81
VSS_161
VSS_162
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24
CPU 2 OF 2-PWR/GND
SYNC_MASTER=M42

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
OF
D
104
D
CPU VCORE HF AND BULK DECOUPLING
63 51 8
=PPVCORE_S0_CPU
4x 470uF. 20x 22uF 0805

1
C0900
22UF
C0901
22UF
20%
2 6.3V
CERM
805
C0902
22UF
20%
2 6.3V
CERM
805
C0903
22UF
20%
2 6.3V
CERM
805
C0904
22UF
20%
2 6.3V
CERM
805
C0905
22UF
20%
2 6.3V
CERM
805
C0906
22UF
20%
2 6.3V
CERM
805
20%
2 6.3V
CERM
805
C0907
22UF
20%
2 6.3V
CERM
805
C0908
22UF
20%
2 6.3V
CERM
805
CPU VCORE VID Connections
C0909
22UF
Resistors to allow for override of CPU VID

Will probably be removed before production
20%
2 6.3V
CERM
805
R0990
79 8
C0910
22UF
C0911
22UF
20%
2 6.3V
CERM
805
C0912
22UF
20%
2 6.3V
CERM
805
20%
2 6.3V
CERM
805
C0913
22UF
20%
2 6.3V
CERM
805
C0914
22UF
20%
2 6.3V
CERM
805
C0915
22UF
20%
2 6.3V
CERM
805
C0916
22UF
20%
2 6.3V
CERM
805
C0917
22UF
20%
2 6.3V
CERM
805
C0918
22UF
20%
2 6.3V
CERM
805
CRITICAL
1
470uF-8MOHM
20%
3 2 2.5V
POLY
D2T
CRITICAL
C0950
CRITICAL
C0952
470uF-8MOHM
22UF
79 8
20%
2 6.3V
CERM
805
20%
3 2 2.5V
POLY
D2T
20%
3 2 2.5V
POLY
D2T
C0954
79 8
R0992
5%
1/16W
MF-LF
402
20%
3 2 2.5V
POLY
D2T
79 8
79 8
79 8
CPU_VID<4>
R0993
R0994
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R0995
R0996
5%
1/16W
MF-LF
402
CPU_VID<5>
CPU_VID<6>
5%
1/16W
MF-LF
402
CPU_VID<3>
470uF-8MOHM
R0991
CPU_VID<1>
CPU_VID<2>
5%
1/16W
MF-LF
402
CRITICAL
C0953
470uF-8MOHM
C0919
79 8
CPU_VID<0>
IMVP6_VID<0>
57
IMVP6_VID<1>
57
IMVP6_VID<2>
57
IMVP6_VID<3>
57
IMVP6_VID<4>
57
IMVP6_VID<5>
57
IMVP6_VID<6>
57
5%
1/16W
MF-LF
402
VCCA (CPU AVdd) Decoupling

63 8
=PP1V5_S0_CPU
1x 10uF, 1x 0.01uF
C0980 1
10uF
20%
6.3V 2
X5R
603
C0981
0.01UF
20%
2 16V
CERM
402
VCCP (CPU I/O) Decoupling

63 11 8 7
=PP1V05_S0_CPU
1x 470uF, 6x 0.1uF 0402
C0935 1
470uF
20%
2.5V 2 3
TANT
D2T
C0936
0.1UF
20%
2 10V
CERM
402
C0937
0.1UF
20%
2 10V
CERM
402
C0938
0.1UF
20%
2 10V
CERM
402
C0939
0.1UF
20%
2 10V
CERM
402
C0940
0.1UF
20%
2 10V
CERM
402
C0941
0.1UF
20%
2 10V
CERM
402
CRITICAL
NOTE: This cap is shared

between CPU and NB
CPU Decoupling & VID
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
OF
D
104
CPU ZONE THERMAL SENSOR

63
=PP3V3_S0_THRM_SNR
C
LAYOUT NOTE:
ADD GND GUARD TRACE
FOR CPU_THERMD_P AND
CPU_THERMD_N
LAYOUT NOTE:
ROUTE CPU_THERMD_P AND
CPU_THERMD_N ON SAME
LAYER.
10 MIL TRACE
10 MIL SPACING
R1005
C1002
10K
0.1UF
5%
1/16W
MF-LF
2 402
10%
2 16V
X5R
402
PLACEHOLDER ADT7461A
R1006
10K
5%
1/16W
MF-LF
2 402
CRITICAL 1
VDD
R1001
OUT
CPU_THERMD_P
499
1%
1/16W
MF-LF
402
50
(TO CPU INTERNAL THERMAL DIODE)
THRM_CPU_DX_P 2
THRM_CPU_DX_N 3
D+
D-
ALERT*/ 6
THM2*
THM* 4
ADT7461
MSOP
C1001
THRM_ALERT_L
THRM_ALERT
SCLK 8
SDATA 7
27
27
0.001uF
R1002
IN
50
U1001
CPU_THERMD_N
499
10%
50V
2 CERM
402
SMB_THRM_CLK
SMB_THRM_DATA
IO
IO
GND
5
1%
1/16W
MF-LF
402
PLACE U1001 NEAR THE U1200
CPU MISC1-TEMP SENSOR

SYNC_MASTER=M42

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
10
OF
D
104
CPU ITP700FLEX DEBUG SUPPORT

C
C
ITPCONN
63 11 9 8 7
CRITICAL
=PP1V05_S0_CPU
J1101
ITP
52435-2872
F-RT-SM
1
R1101
R1103
54.9 54.9
1%
1/16W
MF-LF
2402
29
1%
1/16W
MF-LF
2402
OUT
OUT 7
7
OUT
IN
R1102
22.6
XDP_TDO
OUT
1%
1/16W
MF-LF
402
ITP
IN
CPU_XDP_CLK_N
CPU_XDP_CLK_P
IN
(FROM CK410M HOST 133/167MHZ)
79 34
IN
R1100
79 12 7
22.62
1
FSB_CPURST_L
XDP_TCK
OUT
79
1%
1/16W
MF-LF
402
IO
IO
63 26 23
=PP3V3_S5_SB_PM
IO
R1104
240
IO
5%
1/16W
MF-LF
2402
IO
IO
(AND WITH RESET BUTTON)
OUT
26 7
XDP_TRST_L
(TCK)
XDP_TCK
ITP_TDO
ITP
7
XDP_TDI
XDP_TMS
XDP_DBRESET_L
63 11 9 8 7
(FBO)
ITPRESET_L
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
=PP1V05_S0_CPU
1 C1100
0.1UF
10%
2 16V
X5R
402
1
2
3
NC 4
5
NC 6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NC 24
25
26
27
28
(DBA#)INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

(DEBUG PORT ACTIVE)
(DBR#)
TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC
(DEBUG PORT RESET)
30
518S0320
R1106
680
ITP TCK SIGNAL LAYOUT NOTE:
5%
MF-LF
ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTORS TCK PIN TO 1/16W
CPUS
402
2
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO
ITP700FLEX
CONNECTORS FBO PIN.
CPU ITP700FLEX DEBUG

SYNC_MASTER=M42

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
11
OF
D
104
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
63 34 19 12
R12201
R1225
54.9
221
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
R1221
24.9
1%
1/16W
MF-LF
402 2
R1226
100
1%
1/16W
MF-LF
2 402
C1226
0.1uF
10%
16V
2 X5R
402
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
=PP1V05_S0_FSB_NB
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
79 7 5
IO
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
NB_FSB_XRCOMP
NB_FSB_XSCOMP
NB_FSB_XSWING
63 34 19 12
E1 HXRCOMP
E2 HXSCOMP
E4 HXSWING
NB_FSB_YRCOMP
NB_FSB_YSCOMP
NB_FSB_YSWING
=PP1V05_S0_FSB_NB
R1230
R1235
54.9
221
1%
1/16W
MF-LF
402 2
34
IN
34
IN
FSB_CLK_NB_P
FSB_CLK_NB_N
HD0*
HD1*
HD2*
HD3*
HD4*
HD5*
HD6*
HD7*
HD8*
HD9*
HD10*
HD11*
HD12*
HD13*
HD14*
HD15*
HD16*
HD17*
HD18*
HD19*
HD20*
HD21*
HD22*
HD23*
HD24*
HD25*
HD26*
HD27*
HD28*
HD29*
HD30*
HD31*
HD32*
HD33*
HD34*
HD35*
HD36*
HD37*
HD38*
HD39*
HD40*
HD41*
HD42*
HD43*
HD44*
HD45*
HD46*
HD47*
HD48*
HD49*
HD50*
HD51*
HD52*
HD53*
HD54*
HD55*
HD56*
HD57*
HD58*
HD59*
HD60*
HD61*
HD62*
HD63*
Y1 HYRCOMP
U1 HYSCOMP
W1 HYSWING
AG2 HCLKIN
AG1 HCLKIN*
OMIT
U1200
945GM
NB
BGA
(1 OF 10)
HA3*
HA4*
HA5*
HA6*
HA7*
HA8*
HA9*
HA10*
HA11*
HA12*
HA13*
HA14*
HA15*
HA16*
HA17*
HA18*
HA19*
HA20*
HA21*
HA22*
HA23*
HA24*
HA25*
HA26*
HA27*
HA28*
HA29*
HA30*
HA31*
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
=PP1V05_S0_FSB_NB
IO
12 19 34 63
IO
R1210
HOST
HADS*
HADSTB0*
HADSTB1*
HAVREF
HBNR*
HBPRI*
HBREQ0*
HCPURST*
HDBSY*
HDEFER*
HDPWR*
HDRDY*
HDVREF
HDINV0*
HDINV1*
HDINV2*
HDINV3*
E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13
J7
W8
U3
AB10
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
HDSTBN0*
HDSTBN1*
HDSTBN2*
HDSTBN3*
K4
T7
Y5
AC4
79
7 5
HDSTBP0*
HDSTBP1*
HDSTBP2*
HDTSBP3*
K3
T6
AA5
AC5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
HHIT*
HHITM*
HLOCK*
D3
D4
B3
HREQ0*
HREQ1*
HREQ2*
HREQ3*
HREQ4*
D8
G8
B8
F8
A8
HRS0*
HRS1*
HRS2*
B4
E6
D6
79 7
HSLPCPU*
HTRDY*
E3
E7
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79
7 5
79 7
79 7
79 7
FSB_ADS_L
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
NB_FSB_VREF
FSB_BNR_L
FSB_BPRI_L
FSB_BREQ0_L
FSB_CPURST_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DPWR_L
FSB_DRDY_L
FSB_DINV_L<0>
FSB_DINV_L<1>
FSB_DINV_L<2>
FSB_DINV_L<3>
FSB_DSTBN_L<0>
FSB_DSTBN_L<1>
FSB_DSTBN_L<2>
FSB_DSTBN_L<3>
FSB_DSTBP_L<0>
FSB_DSTBP_L<1>
FSB_DSTBP_L<2>
FSB_DSTBP_L<3>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_SLPCPU_L
FSB_TRDY_L
100
1%
1/16W
MF-LF
2 402
IO
IO
IO
IO
OUT
IO
OUT
IO
C1211
1
1
R1211
200
0.1uF
10%
16V
X5R 2
402
1%
1/16W
MF-LF
2 402
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
1%
1/16W
MF-LF
2 402
NB CPU Interface
A
1
R1231
24.9
1%
1/16W
MF-LF
402 2
R1236
100
1%
1/16W
MF-LF
2 402
SYNC_DATE=(MASTER)
C1236

0.1uF
10%
2 16V
X5R
402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
12
OF
D
104
=PP1V5_S0_NB_PCIE
19 63
R1310
24.9
OMIT
1%
1/16W
MF-LF
2 402
U1200
19
19
OUT
OUT
OUT
OUT
19
IO
19
IO
19
19
19
IO
OUT
IN
19 IN
19
19
19
19
19
19
OUT
OUT
OUT
OUT
OUT
19
OUT
19
OUT
19
OUT
19
OUT
19
OUT
19
19
19
OUT
19
19
OUT
OUT
OUT
OUT
OUT
TV-Out Signal Usage:

19
Composite: DACA only

S-Video:
DACB & DACC only
Component: DACA, DACB & DACC
19
19
19
Unused DAC outputs must remain powered, but can omit

filtering components. Unused DAC outputs should
connect to GND through 75-ohm resistors.
19
19
19
OUT
OUT
OUT
OUT
OUT
OUT
OUT
LVDS_BKLTCTL
LVDS_BKLTEN
LVDS_CLKCTLA
LVDS_CLKCTLB
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_IBG
TP_LVDS_VBG
LVDS_VDDEN
LVDS_VREFH
LVDS_VREFL
LVDS_A_CLK_N
LVDS_A_CLK_P
LVDS_B_CLK_N
LVDS_B_CLK_P
D32 L_BKLTCTL
J30 L_BKLTEN
H30 L_CLKCTLA
H29 L_CLKCTLB
G26 L_DDC_CLK
(3 OF 10)
E26 LB_CLK
B37 LA_DATA0
B34 LA_DATA1
A36 LA_DATA2
LVDS_B_DATA_N<0>
LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>
G30 LB_DATA0*
D30 LB_DATA1*
F29 LB_DATA2*
EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
EXP_A_RXN8
EXP_A_RXN9
EXP_A_RXN10
EXP_A_RXN11
EXP_A_RXN12
EXP_A_RXN13
EXP_A_RXN14
EXP_A_RXN15
EXP_A_RXP0
EXP_A_RXP1
EXP_A_RXP2
EXP_A_RXP3
F30 LB_DATA0
D29 LB_DATA1
F28 LB_DATA2
A16 TV_DACA_OUT
C18 TV_DACB_OUT
A19 TV_DACC_OUT
J20 TV_IREF
B16 TV_IRTNA
B18 TV_IRTNB
B19 TV_IRTNC
TV-Out Disable
19
19
19
19
19
CRT Disable
19
Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core
rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.
OUT
OUT
OUT
OUT
OUT
OUT
19
IO
19
IO
19
19
19
OUT
OUT
OUT
CRT_BLUE
CRT_BLUE_L
CRT_GREEN
CRT_GREEN_L
CRT_RED
CRT_RED_L
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC_R
CRT_IREF
CRT_VSYNC_R
E23 CRT_BLUE
D23 CRT_BLUE*
C22 CRT_GREEN
B22 CRT_GREEN*
A21 CRT_RED
B21 CRT_RED*
EXP_A_RXP4
EXP_A_RXP5
EXP_A_RXP6
EXP_A_RXP7
EXP_A_RXP8
EXP_A_RXP9
EXP_A_RXP10
EXP_A_RXP11
EXP_A_RXP12
EXP_A_RXP13
EXP_A_RXP14
EXP_A_RXP15
EXP_A_TXN0
EXP_A_TXN1
EXP_A_TXN2
EXP_A_TXN3
EXP_A_TXN4
EXP_A_TXN5
EXP_A_TXN6
EXP_A_TXN7
EXP_A_TXN8
EXP_A_TXN9
VGA
Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and
VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.
EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2
A33 LA_CLK*
A32 LA_CLK
E27 LB_CLK*
LVDS_A_DATA_P<0>
LVDS_A_DATA_P<1>
LVDS_A_DATA_P<2>
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
EXP_A_COMPO
F32 L_VDDEN
C33 L_VREFH
C32 L_VREFL
C37 LA_DATA0*
B35 LA_DATA1*
A37 LA_DATA2*
TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
EXP_A_COMPI
BGA
G25 L_DDC_DATA
B38 L_IBG
C35 L_VBG
LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<2>
945GM
NB
PCI-EXPRESS GRAPHICS
19
LVDS
19
Can leave all signals NC if LVDS is not implemented

Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used
VCCD_LVDS must remain powered with proper decoupling.
Otherwise, tie VCCD_LVDS to GND also.
TV
LVDS Disable
EXP_A_TXN10
C26 CRT_DDC_CLK
C25 CRT_DDC_DATA
G23 HSYNC
EXP_A_TXN11
EXP_A_TXN12
J22 CRT_IREF
H23 CRT_VSYNC
EXP_A_TXN14
EXP_A_TXN15
EXP_A_TXN13
EXP_A_TXP0
EXP_A_TXP1
EXP_A_TXP2
EXP_A_TXP3
EXP_A_TXP4
EXP_A_TXP5
EXP_A_TXP6
EXP_A_TXP7
EXP_A_TXP8
EXP_A_TXP9
EXP_A_TXP10
EXP_A_TXP11
EXP_A_TXP12
EXP_A_TXP13
EXP_A_TXP14
EXP_A_TXP15
PEG_COMP
D40
D38
SDVO Alternate Function
F34
65
G38
H34
65
J38
65
L34
M38
65
N34
65
P38
R34
65
T38
65
V34
W38
65
Y34
AA38
65
AB34
65
AC38
65
D34
F38
65
G34
65
H38
J34
65
L38
65
M34
N38
65
P34
R38
65
T34
65
V38
W34
65
Y38
65
AA34
AB38
65
F36
65
G40
H36
65
J40
65
L36
M40
65
N36
65
P40
R36
65
T40
65
V36
W40
65
Y36
AA40
65
AB36
65
AC40
65
D36
F40
65
G36
65
H40
J36
65
L40
65
M36
N40
65
P36
R40
65
T36
65
V40
W36
65
Y40
65
AA36
AB40
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
PEG_D2R_N<0>
PEG_D2R_N<1>
PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<6>
PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>
PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>
PEG_D2R_P<9>
PEG_D2R_P<10>
PEG_D2R_P<11>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<14>
PEG_D2R_P<15>
PEG_R2D_C_N<0>
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
PEG_R2D_C_P<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>
IN
IN
IN
SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SDVOB_RED#
SDVOB_GREEN#
SDVOB_BLUE#
SDVOB_CLKN
SDVOC_RED#
SDVOC_GREEN#
SDVOC_BLUE#
SDVOC_CLKN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SDVOB_RED
SDVOB_GREEN
SDVOB_BLUE
SDVOB_CLKP
SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NB PEG / Video Interfaces

SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
13
OF
D
104
R14401
R1441
10K
TP_NB_XOR_FSB2_H7
TP_NB_TESTIN_L
NB_TV_DCONSEL0
NB_TV_DCONSEL1
19
19
19
34
IN
34
IN
34
IN
IN
6 IN
20
IN
IN
20
IN
IN
20
IN
IN
IN
6 IN
=PP3V3_S0_NB
10K
5%
1/16W
MF-LF
402 2
79 57 23
IN
IN
IN
IN
20
IN
IN
20
IN
20
IN
20
IN
23
OUT
NB_RST_IN_L
100
OUT
57 26
IN
5%
1/16W
MF-LF
402
19
19
IO
IO
22
OUT
33
OUT
A41 RSVD11
A35 RSVD12
A34 RSVD13
K16 CFG0
K18 CFG1
J18 CFG2
F18 CFG3
PM_BMBUSY_L
G28 PM_BM_BUSY*
F25 PM_EXTTS0*
H26 PM_EXTTS1*
E15 CFG4
F15 CFG5
E18 CFG6
D19 CFG7
D16 CFG8
G16 CFG9
E16 CFG10
D15 CFG11
G15 CFG12
K15 CFG13
C15 CFG14
H16 CFG15
G18 CFG16
H15 CFG17
J25 CFG18
K27 CFG19
J26 CFG20
PM_THRMTRIP_L
VR_PWRGOOD_DELAY
NB_RST_IN_L_R
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
G6 PW_THRMTRIP*
AH33 PWROK
AH34 RSTIN*
SDVO_CTRLCLK
SDVO_CTRLDATA
NB_SB_SYNC_L
CLK_NB_OE_L
28
AW7
AW40
29
SM_CK0*
SM_CK1*
AW35
28
AT1
28
SM_CK2*
AY7
AY40
29
SM_CKE0
SM_CKE1
AU20
30 28
AT20
30 28
SM_CKE2
BA29
AY29
30 29
AW13
30 28
AW12
AY21
30 28
AW21
30 29
SM_CK1
SM_CK2
SM_CK3
AG11 RSVD5
AF11 RSVD6
H7 RSVD7
NB_BSEL<0>
NB_BSEL<1>
NB_BSEL<2>
NB_CFG<3>
NB_CFG<4>
NB_CFG<5>
NB_CFG<6>
NB_CFG<7>
NB_CFG<8>
NB_CFG<9>
NB_CFG<10>
NB_CFG<11>
NB_CFG<12>
NB_CFG<13>
NB_CFG<14>
NB_CFG<15>
NB_CFG<16>
NB_CFG<17>
NB_CFG<18>
NB_CFG<19>
NB_CFG<20>
H28 SDVO_CTRLCLK
H27 SDVO_CTRLDATA
K28 ICH_SYNC*
H32 CLK_REQ*
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BGA
D28 RSVD14
D27 RSVD15
PM_EXTTS_L
PM_DPRSLPVR
R1430
26
IN
6 IN
R14201
48 47
TP_NB_XOR_LVDS_A35
TP_NB_XOR_LVDS_A34
TP_NB_XOR_LVDS_D28
TP_NB_XOR_LVDS_D27
AY35
AR1
SM_CK0
(2 OF 10)
J19 RSVD8
K30 RSVD9
J29 RSVD10
NC
19
945GM
NB
T32 RSVD1
R32 RSVD2
F3 RSVD3
F7 RSVD4
RSVD
NC
NC
NC
NC
NC
NC
SM_CK3*
DDR MUXING
(D_PLLMON1#)
(D_PLLMON1)
(H_EDRDY#)
(H_PCREQ#)
(H_PLLMON1#)
(H_PLLMON1)
(H_PROCHOT#)
(TESTIN#)
(TV_DCONSEL0)
(TV_DCONSEL1)
(VSS_MCHDETECT)
(LA_DATAN3)
(LA_DATAP3)
(LB_DATAN3)
(LB_DATAP3)
U1200
SM_CKE3
SM_CS0*
SM_CS1*
SM_CS2*
SM_CS3*
29
30 29
30 29
AF10
SM_ODT0
BA13
BA12
30 28
AY20
AU21
30 29
SM_ODT3
MEM_CLK_P<0>
MEM_CLK_P<1>
MEM_CLK_P<2>
MEM_CLK_P<3>
MEM_CLK_N<0>
MEM_CLK_N<1>
MEM_CLK_N<2>
MEM_CLK_N<3>
MEM_CKE<0>
MEM_CKE<1>
MEM_CKE<2>
MEM_CKE<3>
MEM_CS_L<0>
MEM_CS_L<1>
MEM_CS_L<2>
MEM_CS_L<3>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
NC
SMOCDCOMP1
=PP1V8_S3_MEM_NB
30 28
30 29
MEM_ODT<0>
MEM_ODT<1>
MEM_ODT<2>
MEM_ODT<3>
R1410
OUT
80.6
OUT
1%
1/16W
MF-LF
2 402
OUT
OUT
AT9
SMVREF0
AK1
32
SMVREF1
AK41
32
G_CLKIN*
AF33
AG33
34
A27
19
A26
C40
19
D41
19
AE35
AF39
22
D_REFCLKIN
D_REFSSCLKIN*
D_REFSSCLKIN
DMI_RXN1
DMI_RXN2
34
19
22
AG35
22
DMI_RXN3
AH39
22
DMI_RXP0
AC35
AE39
22
AF35
22
DMI_RXP3
AG39
22
DMI_TXN0
AE37
22 5
DMI_TXN1
DMI_TXN2
AF41
22 5
AG37
AH41
22
DMI_TXP0
DMI_TXP1
AC37
22 5
AE41
22 5
DMI_TXP2
AF37
AG41
22
DMI_TXN3
DMI_TXP3
MEM_RCOMP_L
MEM_RCOMP
AV9
SMRCOMP
G_CLKIN
D_REFCLKIN*
16 19 63
SMRCOMP*
DMI_RXP1
DMI_RXP2
BA41 NC3
BA40 NC4
BA39 NC5
29
AL20
DMI_RXN0
D1 NC0
C41 NC1
C1 NC2
28
SMOCDCOMP0
SM_ODT1
SM_ODT2
CFG
OMIT
5%
1/16W
MF-LF
2 402
CLK
5%
1/16W
MF-LF
402 2
PM
10K
63 20 19 14
=PP3V3_S0_NB
MISC
DMI
63 20 19 14
22
22
22
NB_CLK100M_GCLKIN_N
NB_CLK100M_GCLKIN_P
NB_CLK_DREFCLKIN_N
NB_CLK_DREFCLKIN_P
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFSSCLKIN_P
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
IN
C1415 1
IN
0.1uF
20%
10V
CERM 2
402
IN
IN
C1416
0.1uF
20%
10V
2 CERM
402
MEM_VREF_NB_0
MEM_VREF_NB_1
IN
IN
R1411
80.6
1%
1/16W
MF-LF
2 402
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BA3 NC6
BA2 NC7
BA1 NC8
B41 NC9
B2 NC10
AY41 NC11
NC
AY1 NC12
AW41 NC13
AW1 NC14
A40 NC15
A4 NC16
A39 NC17
A3 NC18
NB Misc Interfaces
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
14
OF
D
104
OMIT
IO
28
IO
28
IO
28
IO
28
IO
28
28
28
28
28
28
IO
IO
IO
IO
IO
28
IO
28
IO
28
IO
28
28
28
28
28
28
28
28
IO
IO
IO
IO
IO
IO
IO
IO
IO
28
IO
28
IO
28
IO
28
28
28
IO
IO
IO
28
IO
28
IO
28
28
28
28
28
28
28
28
28
28
28
IO
28
28
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
IO
28
28
IO
IO
AJ35 SA_DQ0
AJ34 SA_DQ1
AM31 SA_DQ2
AM33 SA_DQ3
AJ36 SA_DQ4
AK35 SA_DQ5
AJ32 SA_DQ6
BGA
AP24 SA_DQ29
AP20 SA_DQ30
AT21 SA_DQ31
AR12 SA_DQ32
AR14 SA_DQ33
AP13 SA_DQ34
AP12 SA_DQ35
AT13 SA_DQ36
AT12 SA_DQ37
AL14 SA_DQ38
AL12 SA_DQ39
SA_BS1
SA_BS2
AV14
30 28
BA20
30 28
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0*
SA_DQS1*
SA_DQS2*
SA_DQS3*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*
30 28
AM35
28
AL26
AN22
28
AM14
28
28
28
AL9
AR3
28
AH4
28
28
AK33
28
AT33
AN28
28
28
AM22
28
AN12
AN8
28
AP3
28
AG5
AK32
28
AU33
AN27
28
AM21
28
28
28
28
AM12
AL8
28
AN3
28
AH5
28
28
AY16
30 28
SA_MA1
AU14
AW16
30 28
BA16
BA17
30 28
AU16
30 28
AV17
AU17
30 28
AW17
30 28
AT16
AU13
30 28
AT17
30 28
AV20
AV12
30 28
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
AK7 SA_DQ43
AP9 SA_DQ44
AN9 SA_DQ45
AY13
AJ33
SA_MA0
SA_MA2
SA_MA3
AK9 SA_DQ40
AN7 SA_DQ41
AK8 SA_DQ42
AT5 SA_DQ46
AL5 SA_DQ47
AY2 SA_DQ48
AW2 SA_DQ49
AP1 SA_DQ50
30 28
SA_DM0
SA_DM1
AM36 SA_DQ13
AM34 SA_DQ14
AN33 SA_DQ15
AK26 SA_DQ16
AL27 SA_DQ17
AP23 SA_DQ24
AL22 SA_DQ25
AP21 SA_DQ26
AN20 SA_DQ27
AL23 SA_DQ28
AU12
SA_CAS*
AR31 SA_DQ10
AP31 SA_DQ11
AN38 SA_DQ12
AL28 SA_DQ21
AM24 SA_DQ22
AP26 SA_DQ23
SA_BS0
MEM_A_BS<0>
MEM_A_BS<1>
MEM_A_BS<2>
SA_MA13
SA_RAS*
AW14
SA_RCVENIN*
SA_RCVENOUT*
AK23
30 28
30 28
30 28
30 28
30 28
30 28
OUT
29
IO
OUT
29
IO
OUT
(4 OF 10)
AH31 SA_DQ7
AN35 SA_DQ8
AP33 SA_DQ9
AM26 SA_DQ18
AN24 SA_DQ19
AK28 SA_DQ20
U1200
945GM
NB
MEM_A_CAS_L
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MEM_A_RAS_L
OUT
29
IO
29
IO
29
IO
29
IO
29
29
29
29
29
29
IO
IO
IO
IO
IO
IO
29
IO
29
IO
29
IO
29
IO
29
29
29
29
29
29
29
29
29
IO
IO
IO
IO
IO
IO
IO
IO
IO
29
IO
29
IO
29
IO
29
IO
29
IO
29
IO
29
IO
29
IO
29
29
29
29
29
29
29
29
29
29
29
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
29
IO
29
IO
29
IO
29
IO
29
IO
29
IO
29
IO
AN2 SA_DQ51
AV2 SA_DQ52
AT3 SA_DQ53
29
IO
29
IO
29
IO
AN1 SA_DQ54
AL2 SA_DQ55
AG7 SA_DQ56
29
IO
29
IO
29
IO
AF9 SA_DQ57
AG4 SA_DQ58
AF6 SA_DQ59
AG9 SA_DQ60
AH6 SA_DQ61
29
IO
29
IO
29
IO
29
IO
29
IO
AF4 SA_DQ62
AF8 SA_DQ63
29
IO
29
IO
SA_WE*
AK24
AY14
NC
NC
30 28
MEM_A_WE_L
OUT
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
945GM
NB
AK39 SB_DQ0
AJ37 SB_DQ1
BGA
AP39 SB_DQ2
AR41 SB_DQ3
AJ38 SB_DQ4
AK38 SB_DQ5
AN41 SB_DQ6
SB_BS0
AT24
30 29
SB_BS1
SB_BS2
AV23
30 29
AY28
30 29
SB_CAS*
AR24
AK36
30 29
AR38
29
AT36
BA31
29
AL17
29
AH8
BA5
29
AN4
29
AM39
29
AT39
AU35
29
AR29
29
AR16
AR10
29
AR7
29
AN5
AM40
29
AU39
AT35
29
AP29
29
AP16
AT10
29
AT7
29
AP5
29
MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_BS<2>
OUT
OUT
OUT
(5 OF 10)
SB_DM0
SB_DM1
SB_DM2
AP41 SB_DQ7
AT40 SB_DQ8
AV41 SB_DQ9
SB_DM3
SB_DM4
SB_DM5
AU38 SB_DQ10
AV38 SB_DQ11
AP38 SB_DQ12
SB_DM6
SB_DM7
AR40 SB_DQ13
AW38 SB_DQ14
AY38 SB_DQ15
BA38 SB_DQ16
AV36 SB_DQ17
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
DDR SYSTEM MEMORY B
28
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
DDR SYSTEM MEMORY A
IO
OMIT
U1200
28
AR36 SB_DQ18
AP36 SB_DQ19
BA36 SB_DQ20
AU36 SB_DQ21
AP35 SB_DQ22
AP34 SB_DQ23
AY33 SB_DQ24
BA33 SB_DQ25
AT31 SB_DQ26
AU29 SB_DQ27
AU31 SB_DQ28
AW31 SB_DQ29
AV29 SB_DQ30
AW29 SB_DQ31
AM19 SB_DQ32
AL19 SB_DQ33
AP14 SB_DQ34
AN14 SB_DQ35
AN17 SB_DQ36
AM16 SB_DQ37
AP15 SB_DQ38
AL15 SB_DQ39
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0*
SB_DQS1*
SB_DQS2*
SB_DQS3*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*
29
29
29
29
29
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
SB_MA1
AW24
AY24
30 29
AR28
AT27
30 29
AT28
30 29
AU27
AV28
30 29
AV27
30 29
AW27
AV24
30 29
BA27
30 29
30 29
SB_MA13
AY27
AR23
30 29
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
SB_RAS*
AU23
30 29
MEM_B_RAS_L
OUT
SB_RCVENIN*
SB_RCVENOUT*
AK16
30 29
MEM_B_WE_L
OUT
SB_MA2
SB_MA3
SB_MA4
SB_MA10
SB_MA11
SB_MA12
SB_WE*
AK18
AR27
30 29
30 29
30 29
30 29
IO
30 29
SB_MA9
AK10 SB_DQ46
AJ8 SB_DQ47
BA10 SB_DQ48
AW10 SB_DQ49
BA4 SB_DQ50
29
OUT
AY23
SB_MA7
SB_MA8
AN10 SB_DQ43
AK13 SB_DQ44
AH11 SB_DQ45
29
OUT
SB_MA0
SB_MA5
SB_MA6
AJ11 SB_DQ40
AH10 SB_DQ41
AJ9 SB_DQ42
29
MEM_B_CAS_L
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
NC
AW4 SB_DQ51
AY10 SB_DQ52
AY9 SB_DQ53
AW5 SB_DQ54
AY5 SB_DQ55
AV4 SB_DQ56
AR5 SB_DQ57
AK4 SB_DQ58
AK3 SB_DQ59
AT4 SB_DQ60
AK5 SB_DQ61
AJ5 SB_DQ62
AJ3 SB_DQ63
NB DDR2 Interfaces
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
15
OF
D
104
NCTF balls are Not Critical To Function

=PPVCORE_S0_NB
AD27
AC27
VCC_NCTF0
VCC_NCTF1
AB27
VCC_NCTF2
VCC_NCTF3
AA27
Y27
W27
V27
U27
T27
R27
AD26
R26
0.47uF
20%
6.3V
CERM-X5R 2
402
C1615
63 19 14
20%
2 6.3V
CERM-X5R
402
C1613
Layout Note:
Place near pin BA23
0.47uF
20%
6.3V
2 CERM-X5R
402
C1620 1
10uF
20%
6.3V
X5R 2
603
VCC_109 M16
VCC_110 L16
VCC_106 N17
VCC_107 M17
VCC_108 N16
AV1 VCC_SM106
AJ1 VCC_SM107
VCC_103 M18
VCC_104 L18
VCC_105 P17
AL6 VCC_SM103
AK6 VCC_SM104
AJ6 VCC_SM105
V23
U23
T23
C1621
10uF
C1610
0.47uF
20%
6.3V
2 CERM-X5R
402
20%
6.3V
2 X5R
603
C1612 1
0.47uF
20%
6.3V
CERM-X5R 2
402
0.47uF
Layout Note:
Place near pin BA15
U21
T21
R21
Layout Note:
Place in cavity
VCC_NCTF41
VCC_NCTF42
AD18
AC18
VCC_NCTF52
VCC_NCTF53
VCCAUX_NCTF40 W16
VCCAUX_NCTF41 V16
VCCAUX_NCTF42 U16
VCC_NCTF59
VCCAUX_NCTF45 AG15
VCCAUX_NCTF46 AF15
VCCAUX_NCTF47 AE15
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCCAUX_NCTF48 AD15
VCCAUX_NCTF49 AC15
VCCAUX_NCTF50 AB15
VCC_NCTF65
VCC_NCTF68
VCC_NCTF69
VCCAUX_NCTF43 T16
VCCAUX_NCTF44 R16
VCC_NCTF60
VCC_NCTF61
Y18
T18
VCCAUX_NCTF37 AB16
VCCAUX_NCTF38 AA16
VCCAUX_NCTF39 Y16
VCC_NCTF54
VCC_NCTF66
VCC_NCTF67
U18
VCCAUX_NCTF34 AE16
VCCAUX_NCTF35 AD16
VCCAUX_NCTF36 AC16
VCC_NCTF51
AB18
AA18
W18
V18
VCCAUX_NCTF32 AG16
VCCAUX_NCTF33 AF16
VCC_NCTF49
VCC_NCTF50
VCC_NCTF57
VCC_NCTF58
T19
VCCAUX_NCTF29 V17
VCCAUX_NCTF30 T17
VCCAUX_NCTF31 R17
VCC_NCTF48
U20
V19
U19
VCCAUX_NCTF26 AB17
VCCAUX_NCTF27 AA17
VCCAUX_NCTF28 W17
VCC_NCTF43
VCC_NCTF55
VCC_NCTF56
AD19
VCCAUX_NCTF23 AF17
VCCAUX_NCTF24 AE17
VCCAUX_NCTF25 AD17
VCC_NCTF40
AD20
V20
T20
R20
VCCAUX_NCTF21 R18
VCCAUX_NCTF22 AG17
VCC_NCTF38
VCC_NCTF39
VCC_NCTF46
VCC_NCTF47
VCCAUX_NCTF18 R19
VCCAUX_NCTF19 AG18
VCCAUX_NCTF20 AF18
VCC_NCTF37
V22
AD21
V21
VCCAUX_NCTF15 AF20
VCCAUX_NCTF16 AG19
VCCAUX_NCTF17 AF19
VCC_NCTF32
VCC_NCTF44
VCC_NCTF45
R22
20%
6.3V
2 CERM-X5R
402
VCCAUX_NCTF12 AG21
VCCAUX_NCTF13 AF21
VCCAUX_NCTF14 AG20
VCC_NCTF30
VCC_NCTF31
R23
AD22
U22
T22
C1611
VCCAUX_NCTF10 AG22
VCCAUX_NCTF11 AF22
VCC_NCTF29
VCC_NCTF35
VCC_NCTF36
R24
AD23
VCCAUX_NCTF7 AF24
VCCAUX_NCTF8 AG23
VCCAUX_NCTF9 AF23
VCC_NCTF27
VCC_NCTF28
W24
T24
VCCAUX_NCTF4 AG25
VCCAUX_NCTF5 AF25
VCCAUX_NCTF6 AG24
VCC_NCTF26
VCC_NCTF33
VCC_NCTF34
17 19 63
VCCAUX_NCTF2 AG26
VCCAUX_NCTF3 AF26
VCC_NCTF21
AA24
Y24
V24
U24
NB_VCCSM_LF2
NB_VCCSM_LF1
0.47uF
VCC_98 Y19
VCC_99 N19
VCC_100 M19
VCC_101 L19
VCC_102 N18
AY6 VCC_SM96
AW6 VCC_SM97
AV6 VCC_SM98
AT6 VCC_SM99
AR8 VCC_SM93
AP8 VCC_SM94
BA6 VCC_SM95
AW8 VCC_SM90
AV8 VCC_SM91
AT8 VCC_SM92
AK11 VCC_SM87
BA8 VCC_SM88
AY8 VCC_SM89
AJ12 VCC_SM84
AH12 VCC_SM85
AG12 VCC_SM86
AJ13 VCC_SM81
AH13 VCC_SM82
AK12 VCC_SM83
AR15 VCC_SM78
AJ15 VCC_SM79
AJ14 VCC_SM80
AW15 VCC_SM74
AV15 VCC_SM75
AU15 VCC_SM76
AT15 VCC_SM77
AH16 VCC_SM71
BA15 VCC_SM72
AY15 VCC_SM73
AJ17 VCC_SM68
AH17 VCC_SM69
AJ16 VCC_SM70
AK19 VCC_SM65
AJ19 VCC_SM66
AJ18 VCC_SM67
AT19 VCC_SM62
AR19 VCC_SM63
AP19 VCC_SM64
AW19 VCC_SM59
AV19 VCC_SM60
AU19 VCC_SM61
=PP1V8_S3_MEM_NB
AR6 VCC_SM100
AP6 VCC_SM101
AN6 VCC_SM102
VCC_95 L20
VCC_96 AB19
VCC_97 AA19
VCC_92 P20
VCC_93 N20
VCC_94 M20
VCC_90 Y20
VCC_91 W20
VCC_87 L21
VCC_88 AC20
VCC_89 AB20
VCC_84 W21
VCC_85 N21
VCC_86 M21
VCC_81 L22
VCC_82 AC21
VCC_83 AA21
VCC_79 N22
VCC_80 M22
VCC_76 Y22
VCC_77 W22
VCC_78 P22
VCC_73 L23
VCC_74 AC22
VCC_75 AB22
VCC_70 P23
VCC_71 N23
VCC_72 M23
VCC_68 AA23
VCC_69 Y23
VCC_65 N24
VCC_66 M24
VCC_67 AB23
VCC_62 M25
VCC_63 L25
VCC_64 P24
VCC_59 N26
VCC_60 L26
VCC_61 N25
VCC_57 L27
VCC_58 P26
AK20 VCC_SM56
BA19 VCC_SM57
AY19 VCC_SM58
AP22 VCC_SM52
AK22 VCC_SM53
AJ22 VCC_SM54
AK21 VCC_SM55
AU22 VCC_SM49
AT22 VCC_SM50
AR22 VCC_SM51
AY22 VCC_SM46
AW22 VCC_SM47
AV22 VCC_SM48
BA23 VCC_SM43
AJ23 VCC_SM44
BA22 VCC_SM45
AH25 VCC_SM40
AJ24 VCC_SM41
AH24 VCC_SM42
AJ26 VCC_SM37
AH26 VCC_SM38
AJ25 VCC_SM39
AU26 VCC_SM34
AT26 VCC_SM35
AR26 VCC_SM36
BA26 VCC_SM30
AY26 VCC_SM31
AW26 VCC_SM32
AV26 VCC_SM33
AH28 VCC_SM27
AJ27 VCC_SM28
AH27 VCC_SM29
AJ29 VCC_SM24
AH29 VCC_SM25
AJ28 VCC_SM26
AM29 VCC_SM21
AL29 VCC_SM22
AK29 VCC_SM23
AP30 VCC_SM18
AN30 VCC_SM19
AM30 VCC_SM20
AU30 VCC_SM15
AT30 VCC_SM16
AR30 VCC_SM17
AY30 VCC_SM12
AW30 VCC_SM13
AV30 VCC_SM14
AU34 VCC_SM8
AT34 VCC_SM9
AR34 VCC_SM10
BA30 VCC_SM11
NB_VCCSM_LF4
NB_VCCSM_LF5
C1614 1
VCC_54 P27
VCC_55 N27
VCC_56 M27
VCC_51 N28
VCC_52 M28
VCC_53 L28
VCC_48 T28
VCC_49 R28
VCC_50 P28
VCC_46 V28
VCC_47 U28
VCC_43 AB28
VCC_44 AA28
VCC_45 Y28
VCC_40 P29
VCC_41 M29
VCC_42 L29
VCC_37 V29
VCC_38 U29
VCC_39 R29
VCC_35 Y29
VCC_36 W29
VCC_32 M30
VCC_33 L30
VCC_34 AA29
VCC_29 R30
VCC_30 P30
VCC_31 N30
VCC_26 V30
VCC_27 U30
VCC_28 T30
VCC_24 Y30
VCC_25 W30
VCC_21 N31
VCC_22 M31
VCC_23 AA30
VCC_18 T31
VCC_19 R31
VCC_20 P31
VCC_15 AA31
VCC_16 W31
VCC_17 V31
VCC_12 M32
VCC_13 L32
VCC_14 J32
VCC_10 P32
VCC_11 N32
VCC_7 Y32
VCC_8 W32
VCC_9 V32
VCC_4 L33
VCC_5 J33
VCC_6 AA32
BGA
(6 OF 10)
AY34 VCC_SM5
AW34 VCC_SM6
AV34 VCC_SM7
AM41 VCC_SM2
AU40 VCC_SM3
BA34 VCC_SM4
945GM
NB
VCC_0 AA33
VCC_1 W33
VCC_2 P33
VCC_3 N33
U1200
AU41 VCC_SM0
AT41 VCC_SM1
OMIT
AC24
AB24
VSS_NCTF8 AE19
VSS_NCTF9 AE18
VSS_NCTF10 AC17
=PP1V5_S0_NB_VCCAUX
VCC_NCTF19
VCC_NCTF20
VCC_NCTF24
VCC_NCTF25
AD24
VSS_NCTF5 AE22
VSS_NCTF6 AE21
VSS_NCTF7 AE20
VCCAUX_NCTF0 AG27
VCCAUX_NCTF1 AF27
VCC_NCTF18
Y25
T25
R25
VSS_NCTF3 AE24
VSS_NCTF4 AE23
VSS_NCTF11 Y17
VSS_NCTF12 U17
VCC_NCTF16
VCC_NCTF17
VCC_NCTF22
VCC_NCTF23
U25
VSS_NCTF0 AE27
VSS_NCTF1 AE26
VSS_NCTF2 AE25
VCC_NCTF15
AB25
AA25
W25
V25
1.8V Max Current

Speed
1 Channel
2 Channel
400MTs
1300mA
2400mA
533MTs
1500mA
2800mA
667MTs
1700mA
3200mA
VCC
16 19 63
VCC_NCTF10
VCC_NCTF13
VCC_NCTF14
AD25
AC25
BGA
(7 OF 10)
VCC_NCTF8
VCC_NCTF9
AA26
U26
T26
945GM
NB
VCC_NCTF7
VCC_NCTF11
VCC_NCTF12
V26
=PPVCORE_S0_NB
1.05V or 1.5V
VCC_NCTF5
VCC_NCTF6
AC26
AB26
Y26
W26
1.05V, Internal Graphics: 3500mA Max

1.05V, External Graphics: 1500mA Max
1.5V, Internal Graphics: 5500mA Max
VCC_NCTF4
U1200
NCTF
63 19 16
These connections can break without

impacting part performance.
OMIT
VCCAUX_NCTF51 AA15
VCCAUX_NCTF52 Y15
VCCAUX_NCTF53 W15
VCC_NCTF70
VCCAUX_NCTF54 V15
VCCAUX_NCTF55 U15
VCC_NCTF71
VCC_NCTF72
VCCAUX_NCTF56 T15
VCCAUX_NCTF57 R15
NB Power 1
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
16
OF
D
104
70mA Max VCCA_CRTDAC/VCCSYNC

19
19
OMIT
=PP2V5_S0_NB_VCCSYNC
H22 VCCSYNC
=PP2V5_S0_NB_VCC_TXLVDS
60mA Max
C30 VCC_TXLVDS0
B30 VCC_TXLVDS1
U1200
945GM
NB
BGA
A30 VCC_TXLVDS2
PP1V5_S0_NB_VCC3G
1500mA Max VCC3G/3GPLL
AJ41 VCC3G0
AB41 VCC3G1
Y41 VCC3G2
V41 VCC3G3
R41 VCC3G4
N41 VCC3G5
L41 VCC3G6
19
PP1V5_S0_NB_VCCA_3GPLL
=PP2V5_S0_NB_VCCA_3GBG
GND_NB_VSSA_3GBG
19
PP2V5_S0_NB_VCCA_CRTDAC
19
GND_NB_VSSA_CRTDAC
19
63 19
F21 VCCA_CRTDAC0
E21 VCCA_CRTDAC1
G21 VSSA_CRTDAC
Max
See VCCSYNC
PP1V5_S0_NB_VCCA_DPLLA
PP1V5_S0_NB_VCCA_DPLLB
PP1V5_S0_NB_VCCA_HPLL
B26 VCCA_DPLLA
C39 VCCA_DPLLB
=PP2V5_S0_NB_VCCA_LVDS
GND_NB_VSSA_LVDS
A38 VCCA_LVDS
B39 VSSA_LVDS
10mA Max
19
19
PP1V5_S0_NB_VCCA_MPLL
AF2 VCCA_MPLL
45mA Max
19
PP3V3_S0_NB_VCCA_TVBG
GND_NB_VSSA_TVBG
H20 VCCA_TVBG
G20 VSSA_TVBG
19
PP3V3_S0_NB_VCCA_TVDACC
19
PP3V3_S0_NB_VCCA_TVDACB
E20 VCCA_TVDACC0
F20 VCCA_TVDACC1
C20 VCCA_TVDACB0
19
19
19
19
19
AC33 VCCA_3GPLL
G41 VCCA_3GBG 2mA
H41 VSSA_3GBG
POWER
(8 OF 10)
19
AF1 VCCA_HPLL
50mA Max
50mA Max
45mA Max
PP3V3_S0_NB_VCCA_TVDACA
63 19
=PP1V5_S0_NB_VCCD_HMPLL
AH1 VCCD_HMPLL0
AH2 VCCD_HMPLL1
=PP1V5_S0_NB_VCCD_LVDS
20mA Max
A28 VCCD_LVDS0
B28 VCCD_LVDS1
C28 VCCD_LVDS2
PP1V5_S0_NB_VCCD_TVDAC
D21 VCCD_TVDAC
=PP3V3_S0_NB_VCC_HV
40mA Max
A23 VCC_HV0
B23 VCC_HV1
B25 VCC_HV2
PP1V5_S0_NB_VCCD_QTVDAC
H19 VCCD_QTVDAC
19
63 19
19
63 19 16
=PP1V5_S0_NB_VCCAUX
1900mA Max
AK31 VCCAUX0
AF31 VCCAUX1
AE31 VCCAUX2
AC31 VCCAUX3
AL30 VCCAUX4
AK30 VCCAUX5
AJ30 VCCAUX6
AH30 VCCAUX7
AG30 VCCAUX8
AF30 VCCAUX9
AE30 VCCAUX10
AD30 VCCAUX11
AC30 VCCAUX12
VTT0 AC14
VTT1 AB14
VTT2 W14
19 63
VTT6 P14
VTT7 N14
VTT8 M14
VTT9 L14
VTT10 AD13
VTT11 AC13
VTT12 AB13
VTT13 AA13
VTT14 Y13
VTT15 W13
VTT16 V13
VTT17 U13
VTT18 T13
VTT19 R13
VTT20 N13
VTT21 M13
VTT22 L13
VTT23 AB12
VTT24 AA12
VTT25 Y12
120mA Max
150mA Max
VTT28 U12
VTT29 T12
VTT30 R12
VTT31 P12
VTT32 N12
VTT33 M12
VTT34 L12
VTT35 R11
VTT36 P11
VTT37 N11
VTT38 M11
VTT39 R10
VTT40 P10
VTT41 N10
24mA Max
VTT42 M10
VTT43 P9
VTT44 N9
VTT45 M9
VTT46 R8
VTT47 P8
VTT48 N8
VTT49 M8
VTT50 P7
VTT51 N7
VTT52 M7
VTT53 R6
VTT54 P6
VTT55 M6
NB_VTTLF_CAP3
VTT56 A6
VTT57 R5
VTT58 P5
C1713
AD29 VCCAUX16
AC29 VCCAUX17
AG28 VCCAUX18
VTT64 R3
VTT65 P3
VTT66 N3
AF28 VCCAUX19
AE28 VCCAUX20
AH22 VCCAUX21
VTT67 M3
VTT68 R2
VTT69 P2
AJ21 VCCAUX22
AH21 VCCAUX23
AJ20 VCCAUX24
VTT70 M2
VTT71 D2
0.47uF
VTT59 N5
VTT60 M5
VTT61 P4
VTT62 N4
VTT63 M4
P16 VCCAUX28
AH15 VCCAUX29
P15 VCCAUX30
AH14 VCCAUX31
VTT3 V14
VTT4 T14
VTT5 R14
AG29 VCCAUX13
AF29 VCCAUX14
AE29 VCCAUX15
AH20 VCCAUX25
AH19 VCCAUX26
P19 VCCAUX27
=PP1V05_S0_NB_VTT
800mA Max
VTT26 W12
VTT27 V12
D20 VCCA_TVDACB1
E19 VCCA_TVDACA0
F19 VCCA_TVDACA1
19
19
20%
6.3V
CERM-X5R 2
402
VTT72 AB1
VTT73 R1
VTT74 P1
NB_VTTLF_CAP2
NB_VTTLF_CAP1
C1711
0.47uF
VTT75 N1
VTT76 M1
20%
6.3V
CERM-X5R 2
402
C1712
0.22uF
20%
2 6.3V
X5R
402
AG14 VCCAUX32
AF14 VCCAUX33
AE14 VCCAUX34
Y14 VCCAUX35
AF13 VCCAUX36
AE13 VCCAUX37
AF12 VCCAUX38
NB Power 2
AE12 VCCAUX39
AD12 VCCAUX40
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
17
OF
D
104
OMIT
AC41
AA41
W41
T41
VSS_0
VSS_1
VSS_2
VSS_3
P41
M41
VSS_4
VSS_5
J41
VSS_6
VSS_7
F41
AV40
U1200
945GM
NB
BGA
(9 OF 10)
VSS_106 AE33
VSS_107 AB33
VSS_108 Y33
AJ40 VSS_12
AH40 VSS_13
AG40 VSS_14
VSS_109 V33
VSS_110 T33
VSS_111 R33
AF40 VSS_15
AE40 VSS_16
B40 VSS_17
VSS_112 M33
VSS_113 H33
VSS_114 G33
AY39 VSS_18
AW39 VSS_19
AV39 VSS_20
VSS_115 F33
VSS_116 D33
AC39 VSS_24
AB39 VSS_25
AA39 VSS_26
Y39 VSS_27
W39 VSS_28
V39 VSS_29
T39 VSS_30
H39 VSS_37
G39 VSS_38
F39 VSS_39
VSS_134 E30
VSS_135 AT29
VSS_136 AN29
D39 VSS_40
AT38 VSS_41
AM38 VSS_42
VSS_137 AB29
VSS_138 T29
M37 VSS_59
L37 VSS_60
J37 VSS_61
VSS_156 AP27
VSS_157 AM27
VSS_158 AK27
H37 VSS_62
G37 VSS_63
F37 VSS_64
VSS_159 J27
VSS_160 G27
D37 VSS_65
AY36 VSS_66
AW36 VSS_67
AN36 VSS_68
AH36 VSS_69
AG36 VSS_70
AF36 VSS_71
AE36 VSS_72
AC36 VSS_73
C36 VSS_74
B36 VSS_75
BA35 VSS_76
AV35 VSS_77
AR35 VSS_78
AH35 VSS_79
AB35 VSS_80
AA35 VSS_81
Y35 VSS_82
VSS_167 F26
VSS_168 D26
VSS_169 AK25
VSS_170 P25
VSS_171 K25
VSS_172 H25
VSS_173 E25
VSS_174 D25
W35 VSS_83
V35 VSS_84
T35 VSS_85
VSS_300 BA7
VSS_301 AV7
VSS_302 AP7
VSS_303 AL7
VSS_304 AJ7
VSS_311 AG6
VSS_312 AD6
VSS_313 AB6
VSS_314 Y6
VSS_315 U6
VSS_316 N6
VSS_317 K6
VSS_318 H6
VSS_319 B6
VSS_320 AV5
VSS_321 AF5
VSS_322 AD5
VSS_323 AY4
VSS_324 AR4
VSS_325 AP4
VSS_326 AL4
C16 VSS_237
AN15 VSS_238
AM15 VSS_239
AK15 VSS_240
N15 VSS_241
VSS_330 R4
VSS_331 J4
VSS_332 F4
VSS_333 C4
VSS_334 AY3
VSS_335 AW3
VSS_336 AV3
VSS_337 AL3
A15 VSS_245
BA14 VSS_246
AT14 VSS_247
VSS_338 AH3
VSS_339 AG3
VSS_340 AF3
AK14 VSS_248
AD14 VSS_249
AA14 VSS_250
VSS_341 AD3
VSS_342 AC3
VSS_343 AA3
U14 VSS_251
K14 VSS_252
H14 VSS_253
VSS_344 G3
VSS_345 AT2
VSS_346 AR2
E14 VSS_254
AV13 VSS_255
AR13 VSS_256
VSS_347 AP2
VSS_348 AK2
B13 VSS_264
AY12 VSS_265
AC12 VSS_266
K12 VSS_267
R35 VSS_86
P35 VSS_87
N35 VSS_88
VSS_297 U8
VSS_298 K8
VSS_299 C8
VSS_327 AJ4
VSS_328 Y4
VSS_329 U4
AG13 VSS_260
P13 VSS_261
F13 VSS_262
D13 VSS_263
VSS_178 AL24
VSS_179 AW23
VSS_294 AG8
VSS_295 AD8
VSS_296 AA8
AL16 VSS_234
J16 VSS_235
F16 VSS_236
AN13 VSS_257
AM13 VSS_258
AL13 VSS_259
VSS_175 A25
VSS_176 BA24
VSS_177 AU24
VSS_286 AR9
VSS_287 AH9
VSS_288 AB9
VSS_308 R7
VSS_309 G7
VSS_310 D7
M15 VSS_242
L15 VSS_243
B15 VSS_244
VSS_283 U10
VSS_284 BA9
VSS_285 AW9
A20 VSS_215
AN19 VSS_216
AC19 VSS_217
W19 VSS_218
K19 VSS_219
AK17 VSS_231
AV16 VSS_232
AN16 VSS_233
VSS_164 AN26
VSS_165 M26
VSS_166 K26
VSS
VSS_305 AH7
VSS_306 AF7
VSS_307 AC7
A18 VSS_226
AY17 VSS_227
AR17 VSS_228
AP17 VSS_229
AM17 VSS_230
VSS_161 F27
VSS_162 C27
VSS_163 B27
VSS_281 AC10
VSS_282 W10
AA20 VSS_212
K20 VSS_213
B20 VSS_214
P18 VSS_223
H18 VSS_224
D18 VSS_225
VSS_148 AU28
VSS_149 AP28
VSS_153 W28
VSS_154 J28
VSS_155 E28
VSS_278 AL10
VSS_279 AJ10
VSS_280 AG10
VSS_292 E9
VSS_293 A9
G19 VSS_220
C19 VSS_221
AH18 VSS_222
VSS_145 A29
VSS_146 BA28
VSS_147 AW28
R37 VSS_56
P37 VSS_57
N37 VSS_58
(10 OF 10)
VSS_275 B11
VSS_276 AV10
VSS_277 AP10
AR21 VSS_199
AN21 VSS_200
AL21 VSS_201
AW20 VSS_209
AR20 VSS_210
AM20 VSS_211
VSS_142 E29
VSS_143 C29
VSS_144 B29
VSS_150 AM28
VSS_151 AD28
VSS_152 AC28
BGA
VSS_273 J11
VSS_274 D11
VSS_289 Y9
VSS_290 R9
VSS_291 G9
K21 VSS_205
J21 VSS_206
H21 VSS_207
C21 VSS_208
VSS_139 N29
VSS_140 K29
VSS_141 G29
W37 VSS_53
V37 VSS_54
T37 VSS_55
945GM
NB
A22 VSS_196
BA21 VSS_197
AV21 VSS_198
AB21 VSS_202
Y21 VSS_203
P21 VSS_204
VSS_126 AY31
VSS_127 AV31
VSS_131 AB31
VSS_132 Y31
VSS_133 AB30
AB37 VSS_50
AA37 VSS_51
Y37 VSS_52
F22 VSS_193
E22 VSS_194
D22 VSS_195
VSS_123 AB32
VSS_124 G32
VSS_125 B32
M39 VSS_34
L39 VSS_35
J39 VSS_36
AE38 VSS_46
C38 VSS_47
AK37 VSS_48
AH37 VSS_49
AA22 VSS_190
K22 VSS_191
G22 VSS_192
VSS_120 AF32
VSS_121 AE32
VSS_122 AC32
VSS_128 AN31
VSS_129 AJ31
VSS_130 AG31
U1200
J23 VSS_187
F23 VSS_188
C23 VSS_189
VSS_117 B33
VSS_118 AH32
VSS_119 AG32
R39 VSS_31
P39 VSS_32
N39 VSS_33
AH38 VSS_43
AG38 VSS_44
AF38 VSS_45
AH23 VSS_183
AC23 VSS_184
W23 VSS_185
K23 VSS_186
VSS_101 AC34
VSS_102 C34
VSS_103 AW33
VSS_9
AN40 VSS_10
AK40 VSS_11
AR39 VSS_21
AN39 VSS_22
AJ39 VSS_23
AT23 VSS_180
AN23 VSS_181
AM23 VSS_182
VSS_99 AF34
VSS_100 AE34
VSS_8
VSS
OMIT
VSS_97 AK34
VSS_98 AG34
VSS_104 AV33
VSS_105 AR33
AP40
VSS_349 AJ2
VSS_350 AD2
VSS_351 AB2
VSS_352 Y2
VSS_353 U2
VSS_354 T2
VSS_355 N2
VSS_356 J2
VSS_357 H2
VSS_358 F2
VSS_359 C2
NB Grounds
VSS_360 AL1
H12 VSS_268
E12 VSS_269
AD11 VSS_270
M35 VSS_89
L35 VSS_90
J35 VSS_91
AA11 VSS_271
Y11 VSS_272
H35 VSS_92
G35 VSS_93
F35 VSS_94

D35 VSS_95
AN34 VSS_96

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
SYNC_DATE=(MASTER)
18
OF
D
104
7
63 19
Power Interface
(MCH LVDS DATA/CLK TX 2.5V PWR)

CRT_RED
CRT_GREEN
CRT_BLUE
CRT_RED_L
CRT_GREEN_L
CRT_BLUE_L
CRT_IREF
These are the power signals that leave the NB "block"

IN
IN
IN
IN
3674mA Max
IN
IN
IN
IN
IN
40mA Max?
19 63
=PP1V8_S3_MEM_NB
IN
132mA Max
17 19 63
IN
IN
3200mA Max
12 34 63
IN
IN
IN
IN
1500mA
10mA
800mA
?mA
16 19 63
=PP1V5_S0_NB
=PP1V5_S0_NB_3G
=PP1V5_S0_NB_3GPLL
=PP1V5_S0_NB_PCIE
=PP1V5_S0_NB_PLL
=PP1V5_S0_NB_TVDAC
=PP1V5_S0_NB_VCCAUX
IN
IN
=PPVCORE_S0_NB
=PP1V05_S0_FSB_NB
=PP1V05_S0_NB_VTT
=PP1V05_S0_NB_CRT
=PP3V3_S0_NB
=PP3V3_S0_NB_VCC_HV
Max
Max?
Max
Max
19 63
TP_LVDS_BKLTCTL
13
TP_LVDS_BKLTEN
TP_LVDS_CLKCTLA
13
16 17 19 63
?mA
100mA
24mA
150mA
1900mA
TP_LVDS_CLKCTLB
13
TP_LVDS_DDC_CLK
13
TP_LVDS_DDC_DATA
NC_LVDS_IBG
14 16 63
3200mA Max
19 63
17 63
TP_CRT_DDC_DATA
17 19
17 19 63
17 19 63
13
TP_LVDS_VREFL
=PP1V5_S0_NB_TVDAC
MAKE_BASE=TRUE
TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
13
=PP2V5_S0_NB_VCCA_LVDS
17
LVDS_IBG
13
LVDS_VDDEN
13
GND_NB_VSSA_LVDS
17
LVDS_VREFH
13
LVDS_VREFL
13
MAKE_BASE=TRUE
13
MAKE_BASE=TRUE
MAKE_BASE=TRUE
13
MAKE_BASE=TRUE
13
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
LVDS_B_CLK_P
13
LVDS_B_CLK_N
13
LVDS_B_DATA_P<2..0>
13
LVDS_B_DATA_N<2..0>
13
PP1V5_S0_NB_VCCD_TVDAC
TP_NB_XOR_LVDS_A34
14
14
TP_NB_XOR_LVDS_D27
14
(MCH TV OUT CHANNEL A 3.3V PWR)
TP_NB_XOR_LVDS_D28
14
PP3V3_S0_NB_VCCA_TVDACA
SDVO_CTRLCLK
14
(MCH TV OUT CHANNEL B 3.3V PWR)
SDVO_CTRLDATA
14
PP3V3_S0_NB_VCCA_TVDACB
PP1V5_S0_NB_VCCD_QTVDAC
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_SDVO_CTRLDATA
MAKE_BASE=TRUE
C1900
C1902
10uF
470uF
20%
2.5V
3 2 TANT
D2T
C1903
10uF
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
C1904
1uF
C1905
0.22uF
C1906
0.22uF
20%
2 6.3V
X5R
402
10%
2 6.3V
CERM
402
20%
2 6.3V
X5R
402
17
17
NO_TEST=TRUE
CRITICAL
1
17
(MCH TVDAC DIGITAL QUIET 1.5V PWR)
NO_TEST=TRUE
TP_SDVO_CTRLCLK
GMCH CORE PWR 1.05V BYPASS
(MCH TVDAC DEDICATED PWR 1.5V)
=PP1V5_S0_NB_TVDAC
63 19
17 19
TP_NB_XOR_LVDS_A35
NO_TEST=TRUE
NC_NB_XOR_LVDS_D28
MAKE_BASE=TRUE
(MCH H/V SYNC 2.5V PWR)
13
NO_TEST=TRUE
NC_NB_XOR_LVDS_D27
MAKE_BASE=TRUE
13
LVDS_A_DATA_N<2..0>
NO_TEST=TRUE
NC_NB_XOR_LVDS_A35
17
LVDS_A_DATA_P<2..0>
NO_TEST=TRUE
NC_NB_XOR_LVDS_A34
17
GND_NB_VSSA_CRTDAC
13
NO_TEST=TRUE
NC_LVDS_B_CLKN
13
PP2V5_S0_NB_VCCA_CRTDAC
13
NO_TEST=TRUE
NC_LVDS_B_CLKP
(MCH CRTDAC ANALOG 2.5V PWR)
=PPVCORE_S0_NB
LVDS_A_CLK_N
NO_TEST=TRUE
NC_LVDS_A_DATAN<2..0>
13
17
NO_TEST=TRUE
LVDS_A_CLK_P
NO_TEST=TRUE
NC_LVDS_A_DATAP<2..0>
13
NC_GND_NB_VSSA_LVDS
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_B_DATAN<2..0>
LVDS_DDC_DATA
63 19 16
NC_LVDS_A_CLKN
13
MAKE_BASE=TRUE
=PPVCORE_S0_NB
1500mA Max
(MCH LVDS ANALOG 2.5V PWR)
=PP1V5_S0_NB_VCCD_LVDS
MAKE_BASE=TRUE
NC_LVDS_B_DATAP<2..0>
63 19 16
13
NO_TEST=TRUE
NC_LVDS_A_CLKP
?mA Max
40mA Max
14 20 63
13
LVDS_DDC_CLK
NO_TEST=TRUE
NC_LVDS_VREFH
MAKE_BASE=TRUE
CRT_DDC_DATA
70mA Max
60mA Max
2mA Max
17 19
13
MAKE_BASE=TRUE
63 19
13
LVDS_CLKCTLB
MAKE_BASE=TRUE
CRT_DDC_CLK
MAKE_BASE=TRUE
17 19
LVDS_CLKCTLA
MAKE_BASE=TRUE
13
(MCH LVDS DIGITAL 1.5V PWR)
MAKE_BASE=TRUE
TP_LVDS_VDDEN
TP_CRT_DDC_CLK
13
MAKE_BASE=TRUE
13
MAKE_BASE=TRUE
Max
Max
Max
Max
Max
LVDS_BKLTEN
MAKE_BASE=TRUE
13
19 63
19 63
13
MAKE_BASE=TRUE
13
1500mA Max
13 63
LVDS_BKLTCTL
MAKE_BASE=TRUE
13
CRT_HSYNC_R
CRT_VSYNC_R
?mA Max
63
=PP1V05_S0_NB_CRT
Rail Totals:
2310mA Max?
17
C1907
(MCH TV OUT CHANNEL C 3.3V PWR)
0.22uF
PP3V3_S0_NB_VCCA_TVDACC
20%
2 6.3V
X5R
402
17
(MCH TV DAC BAND GAP 3.3V PWR)

PP3V3_S0_NB_VCCA_TVBG
17
GND_NB_VSSA_TVBG
17
(MCH DISPLAY A PLL 1.5V PWR)
63 19 17
MCH VTT BYPASS

(MCH FSB 1.05V PWR)
(SHARE C0940 470UF)
=PP1V05_S0_NB_VTT
800mA Max
1
C1965
4.7uF
20%
2 6.3V
CERM
603
C1966
2.2uF
63 19 17
C1967
C1914 1
10uF
20%
2 6.3V
X5R
402
Layout Note:
Place in cavity
20%
6.3V 2
X5R
603
PP1V5_S0_NB_VCCA_DPLLA
17
MAKE_BASE=TRUE
MCH VCCA_3GBG BYPASS

(MCH PCIE/DMI BAND GAP 2.5V PWR)
=PP3V3_S0_NB_VCC_HV
40mA Max
0.22uF
20%
2 6.3V
CERM1
603
TP_NB_VCCA_DPLLA
MCH VCC_HV BYPASS

(MCH HV BUFFER 3.3V PWR)
63 19 17
2mA Max
C1915
0.1uF
GMCH VCCAUX FILTER

(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)
63 19 17 16
C1918 1
20%
10V
CERM 2
402
20%
10V
CERM 2
402
0.1uF
PP1V5_S0_NB_VCCA_DPLLB
17
NB_CLK_DREFCLKIN_P
14
NB_CLK_DREFCLKIN_N
14
NB_CLK_DREFSSCLKIN_P
14
NB_CLK_DREFSSCLKIN_N
14
MAKE_BASE=TRUE
C1916 1
20%
2 10V
CERM
402
(MCH DISPLAY B PLL 1.5V PWR)

TP_NB_VCCA_DPLLB
=PP1V5_S0_NB_VCCAUX
1900mA Max
0.1uF
Layout Note:
Place on the edge
B
GMCH VCC3G FILTER
(PCI-E/DMI ANALOG 1.5V PWR)
L1970
GMCH VCCA_HPLL FILTER
(HOST PLL 1.5V PWR)
PP1V5_S0_NB_VCCA_HPLL
L1934
63 19
=PP1V5_S0_NB_PLL
100mA Max
FERR-120-OHM-0.2A
1
VOLTAGE=1.5V
2
0603
1
22UF
Layout Note:
Place L and C
close to MCH
C1935
20%
2 10V
CERM
402
1500mA Max
GMCH VCCA_MPLL FILTER

(MCH MEMORY PLL 1.5V PWR)
PP1V5_S0_NB_VCCA_MPLL 17
L1936
FERR-120-OHM-0.2A
0603
63 19
45mA Max
C1936 1
22UF
C1937
0.1uF
20%
10V
2 CERM
402
20%
6.3V
CERM 2
805
20%
2 6.3V
X5R
603
20%
2 2.5V
POLY
SMB2
17
C1972
10uF
20%
2 6.3V
X5R
603
Layout Note:
10uF caps should
be close to MCH
on opposite side.
1500mA Max
GMCH VCCA_3GPLL FILTER

(3GIO PLL 1.5V PWR)
VOLTAGE=1.5V
R1975
1
PP1V5_S0_NB_VCCA_3GPLL
0.51 2
1%
1/16W
MF-LF
402
Layout Note:
3GPLL 10uF cap should
be placed in cavity
C1971
10uF
220UF
1.0UH-220MA-0.12-OHM
=PP1V5_S0_NB_3GPLL
1
2
PP1V5_S0_NB_3GPLL_F
0805
C1970
L1975
VOLTAGE=1.5V
PP1V5_S0_NB_VCC3G
VOLTAGE=1.5V
2
1210
17
0.1uF
20%
6.3V 2
CERM
805
91nH
=PP1V5_S0_NB_3G
45mA Max
C1934 1
63 19
VOLTAGE=1.5V
C1975 1
10uF
20%
6.3V 2
X5R
603
17
C1976
0.1uF
20%
2 10V
CERM
402
GND_NB_VSSA_3GBG
NB (GM) Decoupling
17
Layout Note: Route to caps, then GND
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
19
OF
D
104
Internal pull-ups
NB_CFG<13:12>
NB_CFG<3>
RESERVED
NB_CFG<4>
RESERVED
14
NB_CFG<5>
Internal pull-up
00
01
10
11
=
=
=
=
Partial Clock Gating Disable

XOR Mode Enabled
All-Z Mode Enabled
Normal Operation
NB_CFG<14>
RESERVED
NB_CFG<15>
RESERVED
NBCFG_DMI_X2
1
R2075
NB_CFG<5>
High = DMIx4
DMI x2 Select
Low
= DMIx2
2.2K
5%
1/16W
MF-LF
2 402
PROBABLY NOT NEEDED

14
NB_CFG<16>
Internal pull-up
NBCFG_DYN_ODT_DISABLE
NB_CFG<6>
RESERVED
14
NB_CFG<7>
Internal pull-up
R2085
NB_CFG<16>
High = Enabled
FSB Dynamic
ODT
Low
= Disabled
2.2K
5%
1/16W
MF-LF
2 402
NO STUFF
1
R2077
NB_CFG<7>
High = Mobile CPU
CPU Strap
Low
= RESERVED
2.2K
5%
1/16W
MF-LF
2 402
NB_CFG<17>
RESERVED
=PP3V3_S0_NB
NBCFG_VCC_1V5
14 19 20 63
NB_CFG<18>
NB_CFG<8>
RESERVED
VCC Select
R2058
Low
14
B
14
NB_CFG<9>
Internal pull-up
= 1.05V
High = Normal
Low
= Reversed
B
=PP3V3_S0_NB 14 19 20
NBCFG_DMI_REVERSE
NBCFG_PEG_REVERSE
63
R2079
NB_CFG<9>
5%
1/16W
MF-LF
2 402
NB_CFG<18>
Internal pull-down
PCIE Graphics
Lane Reversal
2.2K
High = 1.5V
2.2K
5%
1/16W
MF-LF
2 402
R2059
NB_CFG<19>
High = Reversed
DMI Lane
Reversal
Low
14
= Normal
2.2K
5%
1/16W
MF-LF
2 402
NB_CFG<19>
Internal pull-down
945 External Design Spec says reserved
=PP3V3_S0_NB 14 19 20 63
NBCFG_SDVO_AND_PCIE
1
NB_CFG<10>
RESERVED
NB_CFG<20>
High = Both active
PCIe Backward
Interop. Mode
Low
14
= Only SDVO
or PCIe x1
R2060
2.2K
5%
1/16W
MF-LF
2 402
NB_CFG<20>
Internal pull-down
PROBABLY NOT NEEDED

NB Config Straps
NB_CFG<11>
RESERVED
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
20
OF
D
104
PP3V3_S5_SB_RTC
R2105 NOTE:
332K
402MF-LF
=PP3V3_S0_SB_GPIO 21
1/16W 1%
R2194
10K
5%
1/16W
MF-LF
2402
OMIT
U2100
26 IN
26 IN
AB1
AB2
SB_RTC_RST_L
AA3
Y5
SB_SM_INTRUDER_L
W4
SB_INTVRMEN
ICH7-M
SB
BGA
RTCX1
RTCX2
LAD0
LAD1
LAD2
LAD3
(1 OF 6)
RTCRST*
INTRUDER*
INTVRMEN
LPC
OUT
SB_RTC_X1
SB_RTC_X2
RTC
26
IN
LDRQ0*
LDRQ1*/GPIO23
W1 EE_CS
NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN TP_SB_XOR_W1
LAN_RST#=L
79 45 5
OUT
79 45 5
OUT
79 45 5
OUT
79 45 5
79 45 5
IN
OUT
ACZ_BITCLK
ACZ_SYNC
R2195 1
R2198 1
R2197 1
ACZ_RST_L
ACZ_SDATAIN<0>
ACZ_SDATAOUTR2196 1
1/16W
MF-LF
402
2
2
39
39
39
79
79
U1
SB_ACZ_BITCLK
SB_ACZ_SYNC R6
(WEAK INT PD)
LAN_RSTSYNC
36
IN
IN
36
OUT
36
OUT
76 IN
76
76
76
34 5
IN
34 5
IN
IN
OUT
OUT
SATA_C_D2R_NAF7
SATA_C_D2R_PAE7
AG6
SATA_C_R2D_C_N
AH6
SATA_C_R2D_C_P
TP1/DPRSTP*
TP2/DPSLP*
ACZ_BIT_CLK
ACZ_SYNC
FERR*
GPIO49/CPUPWRGD
CPU
LAN_TXD0
LAN_TXD1
LAN_TXD2
79
AF18
TP_SB_SATALED_L
SATA_A_D2R_NAF3
SATA_A_D2R_PAE3
AG2
SATA_A_R2D_C_N
AH2
SATA_A_R2D_C_P
CPUSPL*
LAN_RXD0
LAN_RXD1 (WEAK INT PU)
LAN_RXD2
SB_ACZ_RST_LR5 ACZ_RST*
T2 ACZ_SDIN0
20K PD
T3 ACZ_SDIN1
TP_SB_ACZ_SDIN1
20K PD
T1 ACZ_SDIN2
TP_SB_ACZ_SDIN2
20K PD
T4 ACZ_SDOUT
2 3979 SB_ACZ_SDATAOUT
2
36
IGNNE*
INIT3_3V*
INIT*
INTR
RCIN*
NMI
SMI*
STPCLK*
THRMTRIP*
SATALED*
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
SATA_0RXN
SATA_0RXP
SATA_0TXN
SATA_0TXP
SATA_2RXN
SATA_2RXP
SATA_2TXN
SATA_2TXP
36
IN
36
IN
AH10
SATA_RBIAS_N
AG10
SATA_RBIAS_P
AF15
OUT IDE_PDIOR_L
AH15
36
OUT IDE_PDIOW_L
AF16
36
IDE_PDDACK_L
OUT
AH16
36
IDE_IRQ14
IN
AG16
36
IN IDE_PDIORDY
IDE_PDDREQ AE15
NOTE: DDREQ HAS INTERNAL 11.5K INPD
AA6
AB5
AC4
Y6 56
AC3
AA5
AB3
56
49 47 5
56
49 47 5
56
49 47 5
49 47 5
LPC_AD<0>
IO
LPC_AD<1>
IO
LPC_AD<2>
IO
LPC_AD<3>
IO
NOTE: LAD<0-3> HAVE INTERNAL 20K PU
TP_SB_DRQ0_L
NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU
TP_SB_GPIO23
IO
NOSTUFF
LPC_FRAME_L
56
49
47 5
1
2
SB_A20GATE
NOTE: PULLED UP PER INTEL
CPU_A20M_L
5%
OUT
79 7
AG27
TP_CPU_CPUSLP_L
AF24
AH25
57 7
79
=PP1V05_S0_SB_CPU_IO 21
23 63
1/16W
MF-LF
402
CPU_DPRSTP_L
OUT
7 CPU_DPSLP_L
OUT
R2199
10K
AG22
AG21
AF22
AF25
79 7
BOM CONSOLIDATION
1/16W 1%
79 7
CPU_FERR_L
IN
CPU_PWRGD
OUT
CPU_IGNNE_L
OUT
FWH_INIT_L
OUT
7 CPU_INIT_L
OUT
79 7 CPU_INTR
OUT
49 48 5
79
AG23
CPU_RCIN_L
AH24
AF23
AH22
R2110=56 IN CV.
R2110 NOTE:
CHANGED TO 54.9 FOR
54.9
MF-LF402
5%
1/16W
MF-LF
2402
AG26
AG24
24 25 63
R2101
2.2K
OUT
AE22
AH28
LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE
CPU_NMI
NOTE: RISING-EDGE TRIGGERED AT CPU
OUT
CPU_SMI_L
OUT
79 7
79 7
79 7
=PP1V05_S0_SB_CPU_IO 21
NOSTUFF
NOTE: KEYBOARD CONTROLLER RESET CPU
R2100
0
1
2
MF-LF402
1/16W 5%
47
SMC_RCIN_L
IN
NOTE: R2108=56 IN CV.

CHANGED TO 54.9 2FOR
BOM CONSOLIDATION
R2108 LAYOUT
NOTE: R2108 TO BE
< 2 IN OF R2107 W/O STUB
54.9
MF-LF402
R2107 1
CPU_STPCLK_L
OUT
24.92
1
CPU_THERMTRIP_R
AF26
24 25 63
1/16W 1%
48 14 7
PM_THRMTRIP_L
IN
MF-LF402
1/16W 1%
AF1 SATA_CLKN
SB_CLK100M_SATA_N
AE1 SATA_CLKP
SB_CLK100M_SATA_P
36
LAN_CLK
IDE
A20GATE
A20M*
(INT PU)
LAN
NOTE:
U3
TP_SB_XOR_U3
POR IS SMC WILL PUT LAN INTF
U5
TP_SB_XOR_U5
INTO RESET STATE TO SAVE PWR.
6
V4
INTEL CONFIRMS OK TO LEAVE PINS ASTP_SB_XOR_V4
NC
T5
6 TP_SB_XOR_T5
U7
TP_SB_XOR_U7
V6
TP_SB_XOR_V6
V7
5%
TP_SB_XOR_V7
LFRAME*
EE_SHCLK
EE_DOUT
(INT PU)
EE_DIN
AC-97/
AZALIA
Y1
TP_SB_XOR_Y1
Y2
TP_SB_XOR_Y2
W3
TP_SB_XOR_W3
V3
TP_SB_XOR_V3
SATA
23 63
ENABLE INTERNAL 1.05V SUSPEND REG
26
26 25 24
SATARBIASN
SATARBIASP
(HSTROBE)
(STOP)
DIOR*
DIOW*
DDACK*
IDEIRQ
IORDY (DSTROBE)
DDREQ
DA0
DA1
DA2
DCS1*
DCS3*
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AH17
AE17
AF17
AE16
AD16
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
IDE_PDD<0>
IO
IDE_PDD<1>
IO
IDE_PDD<2>
IO
IDE_PDD<3>
IO
IDE_PDD<4>
IO
IDE_PDD<5>
IO
IDE_PDD<6>
IO
IDE_PDD<7>
IO
IDE_PDD<8>
IO
IDE_PDD<9>
IO
IDE_PDD<10>
IO
IDE_PDD<11>
IO
IDE_PDD<12>
IO
IDE_PDD<13>
IO
IDE_PDD<14>
IO
IDE_PDD<15>
IO
36
36
36
36
36
LAYOUT NOTE: R2107 TO BE

< 2 IN OF SB
NOTE: DD<7> HAS INTERNAL 11.5K PD
IDE_PDA<0>
OUT
IDE_PDA<1>
OUT
IDE_PDA<2>
OUT
IDE_PDCS1_L
OUT
IDE_PDCS3_L
OUT
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES RS
AC 07
SB: 1 OF 4
INTEL HIGH DEFINITION AUDIO
SYNC_MASTER=M38
ACZ_BIT_CLK INTERNAL 20K PD ENABLED WHEN
INTERNAL 20K PD ONLY ENABLED IN S3COLD

- LSO BIT IN AC97 GLOBAL CONTROL REG = 1; OR
NONE
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
ACZ_RST#
ACZ_SDIN[0-2]
INTERNAL 20K PD
ACZ_SDOUT
ACZ_SYNC

INTERNAL 20K PD
INTERNAL 20K PD ENABLED DURING RESET AND

INTERNAL
WHEN 20K PD ENABLED WHEN
- LSO BIT IN AC97 GLOBAL CONTROL REG -= LSO
1; OR
BIT IN AC97 GLOBAL CONTROL REG = 1; OR
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE- DISABLED
BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

SIZE
INTERNAL 20K PD
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
21
OF
D
104
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
37
IN
37
IN
37
37
USB_A_OC_L
USB_B_OC_L
6 USB_C_OC_L
6 USB_D_OC_L
6 USB_E_OC_L
OUT
OUT
22 6
46
IN
22 6
22
22
46 IN
46
46
SB_GPIO29
22 6 SB_GPIO30
22 SB_GPIO31
OUT
OUT
46
IN
46
IN
46
OUT
46
OUT
PCIE_A_D2R_N F26
PCIE_A_D2R_P F25
E28
PCIE_A_R2D_C_N
E27
PCIE_A_R2D_C_P
PCIE_B_D2R_N H26
PCIE_B_D2R_P H25
G28
PCIE_B_R2D_C_N
G27
PCIE_B_R2D_C_P
ICH7-M
SB
PERN1
PERP1
PETN1
PETP1
BGA
(3 OF 6)
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
PCIE_C_D2R_N K26
PCIE_C_D2R_P K25
J28
PCIE_C_R2D_C_N
J27
PCIE_C_R2D_C_P
PERN3
PERP3
PETN3
PETP3
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
PCIE_D_D2R_N M26
PCIE_D_D2R_P M25
L28
PCIE_D_R2D_C_N
L27
PCIE_D_R2D_C_P
PERN4
PERP4
PETN4
PETP4
22
46
63
=PP3V3_S5_SB_IO
2
R2205
NOSTUFF
52 47
IO
52 47
IO
47
IO
52 47
IO
52 47
IO
R2207
10K
MF-LF
1/16W
402 5%
OUT
46
IN
46
IN
46
R2206
10K
MF-LF
1/16W
402 5%
OUT
46
46
46
10K
MF-LF
1/16W
402 5%
46
46
IN
46
46
OUT
OUT
IN
IN
OUT
OUT
PCIE_E_D2R_N P26
PCIE_E_D2R_P P25
N28
PCIE_E_R2D_C_N
N27
PCIE_E_R2D_C_P
PCIE_F_D2R_N T25
PCIE_F_D2R_P T24
R28
PCIE_F_R2D_C_N
R27
PCIE_F_R2D_C_P
SPI_SCLK
SPI_CE_L
SPI_ARB
R2
P6
P1
SPI_SI
SPI_SO
P5
P2
22 6
IN
22 6
22 6
22 6
22 6
USB_A_OC_L
USB_B_OC_L
USB_C_OC_L
USB_D_OC_L
USB_E_OC_L
22 SB_GPIO29
22 6 SB_GPIO30
22 SB_GPIO31
D3
C4
D5
D4
E5
C3
A2
B3
PERN5
PERP5
PETN5
PETP5
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
PERN6
PERP6
PETN6
PETP6
SPI_CLK (INT PD)
SPI_CS*
SPI_ARB (INT PD)
SPI
46 IN
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
PERN2
PERP2
PETN2
PETP2
DMI
SPI_MOSI
SPI_MISO
USB
U2100
1
1
R2223
R2222
R2226
10K
10K
10K
R2225
R2200
R2250
R2255
R2251
10K
10K
10K
10K
10K
OMIT
USB_G_OC_PU
USB_C_OC_PUUSB_D_OC_PUUSB_E_OC_PU
22
=PP3V3_S5_SB_USB
PCI-EXP
63
OC0*
OC1*
OC2*
OC3*
OC4*
OC5*/GPIO29
OC6*/GPIO30
OC7*/GPIO31
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBRBIAS*
USBRBIAS
V26
V25
U28
U27
14 5
14 5
14
14
Y26
Y25
W28
W27
14 5
14 5
14
14
AB26
AB25
AA28
AA27
14
14
14
14
AD25
AD24
AC28
AC27
14
14
14
14
AE28
AE27
D2
D1
DMI_N2S_N<1>
IN
DMI_N2S_P<1>
IN
DMI_S2N_N<1>
OUT
DMI_S2N_P<1>
OUT
DMI_N2S_N<2>
IN
DMI_N2S_P<2>
IN
DMI_S2N_N<2>
OUT
DMI_S2N_P<2>
OUT
DMI_N2S_N<3>
IN
DMI_N2S_P<3>
IN
DMI_S2N_N<3>
OUT
DMI_S2N_P<3>
OUT
34
34
SB_CLK100M_DMI_N
IN
SB_CLK100M_DMI_P
IN
2
1/16WMF-LF 1% 402
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
USB_A_NIO
USB_A_PIO
USB_B_NIO
USB_B_PIO
USB_C_NIO
USB_C_PIO
USB_D_NIO
USB_D_PIO
USB_E_NIO
USB_E_PIO
USB_F_NIO
USB_F_PIO
USB_G_NIO
USB_G_PIO
USB_H_NIO
USB_H_PIO
OMIT
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40
IO
40 26
IO
26
IO
26
IO
26
IO
40 26
IO
PCI_AD<0>E18
PCI_AD<1>C18
PCI_AD<2>A16
PCI_AD<3>F18
PCI_AD<4>E16
PCI_AD<5>A18
PCI_AD<6>E17
PCI_AD<7>A17
PCI_AD<8>A15
PCI_AD<9>C14
E14
PCI_AD<10>
D14
PCI_AD<11>
B12
PCI_AD<12>
C13
PCI_AD<13>
G15
PCI_AD<14>
G13
PCI_AD<15>
E12
PCI_AD<16>
C11
PCI_AD<17>
D11
PCI_AD<18>
A11
PCI_AD<19>
A10
PCI_AD<20>
F11
PCI_AD<21>
F10
PCI_AD<22>
PCI_AD<23>E9
PCI_AD<24>D9
PCI_AD<25>B9
PCI_AD<26>A8
PCI_AD<27>A6
PCI_AD<28>C7
PCI_AD<29>B6
PCI_AD<30>E6
PCI_AD<31>D6
F16
PCI_FRAME_L
A3
INT_PIRQA_L
B4
INT_PIRQB_L
C5
INT_PIRQC_L
B5
INT_PIRQD_L
AE5
TP_SB_XOR_AE5
AD5
TP_SB_XOR_AD5
AG4
TP_SB_XOR_AG4
AH4
TP_SB_XOR_AH4
AD9
TP_SB_XOR_AD9
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
U2100
ICH7-M
SB
BGA
(2 OF 6)
=PP3V3_S0_SB 25
D7
REQ0*
E7
GNT0*
C16
REQ1*
D16
GNT1*
C17
REQ2*
D17
GNT2*
40 26 E13
REQ3*
40 F13
GNT3*
A13
REQ4*/GPIO22
A14
GNT4*/GPIO48
C8
GPIO1/REQ5*
D8
GPIO17/GNT5*
26 PCI_REQ0_L
IN
TP_PCI_GNT0_L
OUT
26 PCI_REQ1_L
IN
TP_PCI_GNT1_L
OUT
26 PCI_REQ2_L
IN
TP_PCI_GNT2_L
OUT
PCI_REQ3_L IN
PCI_GNT3_L OUT
EXTERNAL 0
AIRPORT (MINI-PCIE)
EXTERNAL 1
NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD
CAMERA
EXTERNAL 2
CF/SD
BT
IR
R2204
USB_RBIAS_PN122.62
63
1
R2298
R2299
10K
10K
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
SB_CRT_TVOUT_MUX
IO NOTE: FWH_WP_L NOT USED
TP_PCI_GNT4_L
OUT
40
PCI_PME_FW_L
IN
(INT
PLTRST*
PCIRST*
20K PU)
PME*
BOOT_LPC_SPI_L
OUT
49 47 5
BOM NOTE FOR PD ON PCI_GNT3_L:
IRDY*
PAR
PCICLK
DEVSEL*
PERR*
PLOCK*
SERR*
STOP*
TRDY*
B15 PCI_C_BE_L<0>
IO
PCI_C_BE_L<1>
IO
PCI_C_BE_L<2>
IO
PCI_C_BE_L<3>
IO
A7 40 26 PCI_IRDY_L
IO
E10
40 PCI_PAR
IO
A9 34 PCI_CLK_SB IN
40
A12 26
PCI_DEVSEL_L
IO
C9 40 26 PCI_PERR_L
IO
E11 26 PCI_LOCK_L
IO
B10 40 26 PCI_SERR_L
IO
F15 40 26 PCI_STOP_L
IO
F14 40 26 PCI_TRDY_L
IO
C26
26 PLT_RST_L
OUT
B18
40 PCI_RST_L
OUT
B19 TP_PCI_PME_L
R2211
1K
5%
NO STUFF - DEFAULT
STUFF - A16 SWAP OVERRIDE
1/16W
MF-LF
2402
(STRAPPED TO TOP-BLOCK SWAP MODE

IE SB INVERTS A16 FOR ALL CYCLES
TARGETING FWH BIOS SPACE)
SB BOOT BIOS SELECT

GNT5#
STRAP R2211
GNT4#
R2210
LPC (DEFAULT)11
UNSTUFFUNSTUFF
PCI
10
UNSTUFF STUFF
SPI
01
STUFF UNSTUFF
NOTE:
GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
SB: 2 OF 4
FRAME*
PIRQA*
PIRQB*
PIRQC*
PIRQD*
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
INT I/F GPIO2/PIRQE* G8

GPIO3/PIRQF*
GPIO4/PIRQG*
GPIO5/PIRQH*
MISC
NOTE:
TO
RSVD5
RSVD6
CHANGE SYMBOL
RSVD7
RSVD[1-9]
RSVD8
MCH_SYNC*
F7
F8
G7
VOLTAGE=0V
LAYOUT NOTE:
PLACE R2204 < 1/2 IN FROM SB
C/BE0* 40
C12
C/BE1* 40
D12
C/BE2* 40
C15
C/BE3* 40
PCI
NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L

26
26
26
36
SB_GPIO2
IO
SB_GPIO3
IO
SB_GPIO4
IO
ODD_PWR_EN_L
IO
AE9 TP_SB_XOR_AE9
AG8 TP_SB_XOR_AG8
AH8 TP_SB_XOR_AH8
F21
TP_SB_RSVD9
(AKA TP3, INTERNAL 20K PU)
AH20 14 NB_SB_SYNC_L
IN

SIZE
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE

APPLE COMPUTER INC.
25
LAYOUT NOTE:
PLACE R2203 < 1/2 IN FROM SB
DMI_IRCOMP_R1
1%
1/16W
MF-LF
402
NOTE:
GNT[0-3]# HAVE INT 20K PU
ENABLED ONLY WHEN PCIRST#=0
AND PWROK=H
PP1V5_S0_SB_VCC1_5_B 24
R2203
24.9
C25
D25
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
DMI_N2S_N<0>
IN
DMI_N2S_P<0>
IN
DMI_S2N_N<0>
OUT
DMI_S2N_P<0>
OUT
22
OF
D
104
NOTE FOR R2323 (DEF=NOSTUFF)

STRAPPING @ PWROK RISING:
SB WILL DISABLE TCO TIMER
SYSTEM REBOOT FEATURE
23 63
=PP3V3_S5_SB 23
25 63
8 7 6 5
1
1 NOSTUFF
1 NOSTUFF
1 NO_REBOOT_MODE
RP2300
10K
R2318 R2395 R2396 R2397 R2327 R2326 R2323

10K
D
63 25 23
1/16W
2402
MF-LF
5%
=PP3V3_S5_SB
1
8.2K
1/16W
2402
MF-LF
5%
10K
1/16W
2402
MF-LF
5%
8.2K
1/16W
2402
MF-LF
5%
10K
1/16W
2402
MF-LF
5%
10K
1/16W
2MF-LF
402
5%
1/16W
2402
MF-LF
5%
R2398 R2320 R2317 R2316

1K
1/16W
2402
MF-LF
5%
10K
1/16W
2402
MF-LF
5%
10K
1/16W
2402
MF-LF
5%
27
IO
IO
NOT USED
PM_RI_L
SB_SPKR
56 49 48 47 5
33
OUT
33
OUT
OUT
47 26 5
IN
14
IN
A28
A19
PM_SUS_STAT_L A27
A22
PM_SYSRST_L
PM_BMBUSY_L AB18
B23
SMB_ALERT_L
A21
SB_GPIO26
B21
BIOS_REC
E23
23 FWH_MFG_MODE
AG18
23
56 49 47 40 5
IO
PM_CLKRUN_L
AC19
TP_AZ_DOCK_EN_L
RESERVED FOR MOBILE
U2
TP_AZ_DOCK_RST_L
AZALIA DOCKING INTF
C
45 37 5
56 49 47 5
IN
IO
47 IN
F20
AH21
AF20
PCIE_WAKE_L
INT_SERIRQ
PM_THRM_L
26
IN
AD22
VR_PWRGD_CK410
IO
47
IN
47
IN
RI*
SPKR (INT WEAK PD)
SUS_STAT*
SYS_RST*
SMC_RUNTIME_SCI_L
SMC_EXTSMI_L
AC21
TP_SB_GPIO6
AC18
E21
GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP
GPIO37/SATA3GP
GPIO26
CLK14
CLK48
SUSCLK
SLP_S3*
SLP_S4*
SLP_S5*
GPIO0/BM_BUSY*
PWROK
GPIO16/DPRSLPVR
TP0/BATLOW*
(INT 20K PU)

PWRBTN*
GPIO27
GPIO28
LAN_RST*
GPIO32/CLKRUN*
RSMRST*
GPIO33/AZ_DOCK_EN*
GPIO34/AZ_DOCK_RST*
WAKE*
SERIRQ
THRM*
VRMPWRGD
GPIO6
GPIO7
GPIO8
GPIO
11 26 63
R2319
R2343
10K
8.2K
SATA GPIO
OF 6)
GPIO11/SMBALERT*
NOTE: RESERVED FOR FUTURE
AC20 GPIO18/STPPCI*
AF21 GPIO20/STPCPU*
PM_STPPCI_L
PM_STPCPU_L
ICH7-M
SB
BGA
(4
C22 SMBCLK
B22 SMBDATA
A26 LINKALERT*
SMB_LINK_ALERT_L
B25 SMLINK0
SMLINK<0>
A25 SMLINK1
SMLINK<1>
SMB_CLK
SMB_DATA
10K
1/16W
2402
MF-LF
5%
U2100
1 2 3 4
27
=PP3V3_S5_SB_PM
OMIT
5%
1/16W
SM-LF
1K
CLKS
SMB
SYS GPIO
PWR MNGT
GPIO9
GPIO10
DEF=GPI
GPIO12
GPIO13
DEF=GPI
GPIO14
GPIO15
GPIO24
GPIO25
ODGPIO35
GPIO38
DEF=GPI
GPIO39
AF19SB_GPIO21
1001
AH18SB_GPIO19
1001
AH19
AE19SB_GPIO37
1001
AC1
B2
34
34
C20
B24
D23
F22
62 47 39
48 47
AA4
SATA_C_DET_L
IN
SB_CLK14P3M_TIMER
IN
SB_CLK48M_USBCTLR
IN
PM_SLP_S3_L
OUT
PM_SLP_S4_L
OUT
PM_SLP_S5_L
OUT
26
PM_SB_PWROK
IN
57 14
PM_DPRSLPVR
OUT
C21 NOTE:
C23
C19
36
5%
21/16W
MF-LF
402
SUS_CLK_SB
OUT
62 47 41
AC22 79
1/16W
2402
MF-LF
5%
R2302
R2303
2 R2305
2
2
DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN
47
47
47
PM_BATLOW_L
IN
47
PM_RSMRST_L
IN
PM_PWRBTN_L
IN
PM_LAN_ENABLE
IN NOTE:
SMC WILL DRIVE 0-1-0 TO KEEP LAN INTF

IN RESET STATE TO SAVE PWR
Y4
R2399
100K
1
2
E20
48 47 SMS_INT_L
IN
A20
47 SMC_SB_NMI
IN
F19
23 PATA_PWR_EN_L
OUT
E19
R4
36 IDE_RESET_L
OUT
E22
SV_SET_UP 5 23 49
R3
CRB_SV_DET 23
D20 TP_SB_GPIO25_DO_NOT_USE
AD21
33 SB_CLK100M_SATA_OE_L
OUT
AD20 TP_SB_GPIO38
IO
AE20
23 SATA_C_PWR_EN_L
OUT
5% 1/16W
402MF-LF
47
SMC_WAKE_SCI_L
IN
NOTE FOR GPIO25:

- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS
- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)
=PP3V3_S5_SB 23
63 25 23
25 63
=PP3V3_S5_SB
R2390
10K
NOTE:
SV_SET_UP IS LINDACARD DETECT
HI = PRESENT
LO = NOT PRESENT
1 NOSTUFF1
R2306
R2308
10K
10K
1/16W
2402
MF-LF
5%
1/16W
2402
MF-LF
5%
23
SV_SET_UP 5 23
CRB_SV_DET 23
5%
1/16W
MF-LF
2402
PATA_PWR_EN_L
49
23 63
R2388
10K
1
1
2402
MF-LF
5%
2402
MF-LF
5%
5%
1/16W
MF-LF
2402
NOSTUFF
LAYOUT NOTE:
R2307
R2309
10K
0
PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE
1/16W
1/16W
63 25 23
23
SATA_C_PWR_EN_L
=PP3V3_S5_SB
1
SB: 3 OF 4
R2313
R2310
10K
10K
1/16W
2402
MF-LF
5%
1/16W
402
2MF-LF
5%
SYNC_MASTER=M38

FWH_MFG_MODE 23
BIOS_REC 23

1 NOSTUFF 1 NOSTUFF
R2314
R2311
0
10K
1/16W
2402
MF-LF
5%
SIZE
1/16W
2402
MF-LF
5%
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
23
OF
D
104
OMIT
OMIT
A4
A23
N24
P24
R18
U14
V27
AA24
AB27
AD11
B1
D10
F4
G18
J1
L24
M17
N14
N17
N18
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P27
P28
R1
R11
R12
R13
R14
R15
R16
R17
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB28
AC2
AC5
AC9
AC11
AD1
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
U2100
ICH7-M
SB
BGA
(6 OF 6)
VSS
AD3
AD4
AD7
AD8
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N15
N16
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
25
25 22
G10
PP5V_S0_SB_V5REF
AD17
V5REF
U2100
F6 V5REF_SUS
25 PP5V_S5_SB_V5REF_SUS
AA22
PP1V5_S0_SB_VCC1_5_B
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22 VCCA3GP
H23 VCC1_5_B
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
ICH7-M
SB
BGA
(5 OF 6)
CORE
VCC1_05
VCC PAUX
VCCLAN_3_3
VCC3_3/VCCHDA
VCCSUS3_3/VCCSUSHDA
V_CPU_IO
IDE
VCC3_3
PCI
VCC3_3
VCCRTC
VCCSUS3_3
B27 VCC3_3
=PP3V3_S0_SB_VCC3_3
AG28 VCCDMIPLL
25 PP1V5_S0_SB_VCCDMIPLL
AB7
=PP1V5_S0_SB_VCC1_5_A_ARX
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
63 25
63 25 24
63 25
63 25
63
ARX
VCC1_5_A
USB
VCCSUS3_3
AD2 VCCSATAPLL
=PP1V5_S0_SB_VCCSATAPLL
AH11 VCC3_3
=PP3V3_S0_SB_VCC3_3
AB10
=PP1V5_S0_SB_VCC1_5_A_ATX
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
E3
24 =PP3V3_S5_SB_VCCSUS3_3
C1
25 =PP1V5_S0_SB_VCCUSBPLL
V5
V1
W2
W7
VCC1_5_A
VCC1_5_A
ATX
VCC1_5_A
VCC1_5_A
=PPVCORE_S0_SB
25 63
NOTE FOR VCCLAN_3_3:

S3 IF INTERNAL LAN IS USED
S0 OR S3 IF NOT
=PP3V3_S0_SB_VCCLAN3_3
25 63
NOTE:
=PP3V3_S0_SB_3V3_1V5_VCCHDAVCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA
DEPENDING ON VIO OF AZALIA INTERFACE
CODEC ICS CONSIDERED SO FAR ARE 3.3V
AE23 =PP1V05_S0_SB_CPU_IO 21 25 63
AE26
AH26
U6
R7
AA7
=PP3V3_S0_SB_VCC3_3_IDE
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
W5
P7
63 25 24
63 25
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
25 63
=PP3V3_S0_SB_VCC3_3_PCI
PP3V3_S5_SB_RTC
25 63
21 25 26
=PP3V3_S5_SB_VCCSUS3_3
24 25 63
A24
C24
D19
D22
G19
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
=PP3V3_S5_SB_VCCSUS3_3_USB
25 63
AB17
AC17
T7
F17
G17
=PP1V5_S0_SB_VCC1_5_A
25 63
AB8
AC8
K7
VCCSAUS1_5
VCCSUS3_3
C28
CHANGE SYMBOL TO 1.05

G20
VCCUSBPLL
AA2
VOLTAGE GENERATED INTERNALLY
Y7 VCCLAN1_5
USB CORE
SO NO CONNECT HERE
CHANGE SYMBOL TO 1.05
VCC1_5_A
A1
H6
H7
J6
J7
VOLTAGE GENERATED INTERNALLY

SO NO CONNECT HERE
SB: 4 OF 4
SYNC_MASTER=M38
=PP1V5_S0_SB_VCC1_5_A_USB_CORE

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
24
OF
D
104
8
63 22
63
ICH VCC1_5_A/ARX BYPASS

(ICH LOGIC&IO[ARX] 1.5V PWR)
63 24 =PP1V5_S0_SB_VCC1_5_A_ARX
=PP3V3_S0_SB
=PP5V_S0_SB
2
R2502
100
1/16W
5
NC
MF-LF
1 402
5%
1
1
D2502
BAT54DW
SOT-363
ICH V5REF BYPASS

(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)
PP5V_S0_SB_V5REF 24
D
1
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
C2503
0.1UF
10%
2 16V
X5R
402
PLACEMENT NOTE:
PLACE C2503 < 2.54MM OF PIN AD17 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
C2511
0.1UF
10%
2 16V
X5R
402
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN AG5
C2517
0.1UF
10%
2 16V
X5R
402
R2501
2
NC
10
1/16W
MF-LF
402
5%
D2502
C2504
0.1UF
10%
2 16V
X5R
402
C2513
0.1UF
10%
2 16V
X5R
402
VOLTAGE=5V
63 24
ICH VCC_PAUX/VCCLAN3_3 BYPASS

(ICH LAN I/F BUFFER 3.3V PWR)
=PP3V3_S0_SB_VCCLAN3_3 24 63
C2519
63 24
C2514
1UF
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AG9
ICH VCC1_5A BYPASS

(ICH LOGIC&IO 1.5V PWR)
63 24
63
ICH V_CPU_IO BYPASS

(ICH CPU I/O 1.05V PWR)
=PP1V05_S0_SB_CPU_IO
24 21
ICH VCCA3GP(VCC1_5_B BYPASS

(ICH IO,LOGIC 1.5V PWR)
PLACEMENT NOTE:
PLACE NEAR PINS AE23, AE26 & AH26 OF SB
100-OHM-EMI
SM-3
PP1V5_S0_SB_VCC1_5_B
1 C2505
1 C2506
1 C2507
C2500
220UF 0.1UF 0.1UF 0.1UF
20%
2.5V
2 POLY
SMB2
10%
2 16V
X5R
402
10%
2 16V
X5R
402
ICH VCCSUS3_3 BYPASS

(ICH SUSPEND 3.3V PWR)
63 25 24
10%
2 16V
X5R
402
PLACEMENT NOTE:
PLACE C2500 & C2505-07 < 2.54MM OF SB
NEAR PINS D28, T28, AD28
NOTE:
PLACE C2520 NEAR PIN E3 OF SB
C2509
0.1UF
10%
2 16V
X5R
402
63 24
20%
2 6.3V
CERM
603
0
63 24
ICH VCCUSBPLL BYPASS

(ICH USB PLL 1.5V PWR)
ICH VCC3_3 BYPASS
(ICH IO BUFFER 3.3V PWR)
=PP3V3_S0_SB_VCC3_3
10%
2 16V
X5R
402
ICH USB CORE/VCC1_5_A BYPASS

(ICH USB CORE 1.5V PWR)
63 24
1 C2522
1 C2524
C2523
0.1UF 0.1UF 4.7UF
10%
2 16V
X5R
402
C2520
0.1UF PLACEMENT
10%
16V
2 X5R
402
C2510
22 24
VOLTAGE=1.5V
PLACEMENT NOTE:
0.1UF
PLACE CAPS NEAR PINS 10%
2 16V
X5R
AB8 AND AC8 OF SB
402
C25331 C2532
PLACEMENT NOTE:
0.1UF 0.1UF
10%
PLACE CAPS NEAR PINS 10%
2 16V
2 16V
X5R
X5R
K3 ... N7 OF SB
402
402
ICH VCC3_3/VCCHDA BYPASS

(ICH INTEL HDA CORE 3.3V PWR)
63 24 =PP3V3_S0_SB_3V3_1V5_VCCHDA
ICH VCC1_5_A/ATX BYPASS

(ICH LOGIC&IO[ATX] 1.5V PWR)
=PP1V5_S0_SB
C2521
10%
2 6.3V
CERM
402
L2500
ICH USB/VCCSUS3_3 BYPASS

(ICH SUSPEND USB 3.3V PWR)
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AH11
402
PLACEMENT NOTE:
1
PLACE < 2.54MM OF SB ON SECONDARY
OR
0.1UF
10%
3.56MM ON PRIMARY NEAR PIN U6
16V
63 25 24
402
2 X5R
402
63 25
C2531 C2534
PLACEMENT NOTE:
PLACE C2504 < 2.54MM OF PIN F6 OF SB
1
1
PLACEMENT NOTE:
0.1UF
0.1UF
PLACE CAPS NEAR PINS
10%
10%
16V
A24 ... G19 AND P7 OF 2SB
2 16V
X5R
X5R
PLACEMENT NOTE:
0.1UF
10%
PLACE CAP UNDER SB NEAR PINS V1,
2 16V
X5R
V5, W2, OR W7
402
(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)

PP5V_S5_SB_V5REF_SUS 24
1
63 25
BAT54DW
FOR 270UF
2 2.5V
POLY
CASE-C2
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AD2
ICH VCC3_3 BYPASS

(ICH IO BUFFER 3.3V PWR)
24 =PP3V3_S0_SB_VCC3_3
SOT-363
3 ICH V5REF_SUS BYPASS
330UF
20%
10%
2 6.3V
CERM
402
63 25 24
=PP3V3_S5_SB
=PP5V_S5_SB
2
63
1 C2502
1
C2518
C2516 PLACEHOLDER
0.1UF 1UF
10%
2 16V
X5R
402
0
63 23
1
ICH VCCSUS3_3 BYPASS
(ICH SUSPEND 3.3V PWR)
ICH CORE/VCC1_05 BYPASS

PLACEMENT NOTE:
(ICH CORE 1.05V PWR)
PLACE CAPS AT EDGE OF SB
=PPVCORE_S0_SB 24 63
ICH VCCSATAPLL BYPASS

(ICH SATA PLL 1.5V PWR)
24 =PP1V5_S0_SB_VCCSATAPLL
63
C2525
1
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY 0.1UF
OR
10%
3.56MM ON PRIMARY NEAR PINS A1 ...
J7
2 16V
X5R
NOTE:
PLACE C2520 NEAR PIN C1 OF SB
402
16V
2 X5R
402
C2515
0.1UF PLACEMENT
10%
2 16V
X5R
402
PLACEMENT NOTE:
PLACE C2509 NEAR PIN B27 OF SB
C2512
PLACEMENT NOTE:
1
3.56MM ON PRIMARY NEAR PINS AA7 ... 0.1UF
AG19
10%
=PP1V5_S0_SB_VCCUSBPLL
1
ICH IDE/VCC3_3 BYPASS

(ICH IDE I/O 3.3V PWR)
ICH PCI/VCC3_3 BYPASS

(ICH PCI I/O 3.3V PWR)
63 24
C2526 C2527 C2528
1
1
1
PLACEMENT NOTE:
0.1UF
0.1UF
0.1UF
DISTRIBUTE IN PCI SECTION OF SB
10%
10%
10%
16V
16V
16V
NEAR PINS A5 ... G16
2 X5R
2 X5R
2 X5R
402
402
402
63 25
=PP1V5_S0_SB
R2500
1
1
2
1/10W 5%
MF-LF603
L2507
ICH VCCDMIPLL BYPASS

(ICH DMI PLL 1.5V PWR)
PP1V5_S0_SB_VCCDMIPLL
0.28-OHM
1
PP1V5_S0_SB_VCCDMIPLL_F
VOLTAGE=1.5V
SB: 4 OF 4
24
VOLTAGE=1.5V
1206
1
1 C2508
C2501
0.01UF 10UF
10%
2 16V
CERM
402
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON
SECONDARY SIDE OR 3.56MM ON PRIMARY
26 24 21
ICH VCCRTC BYPASS

(ICH RTC 3.3V PWR)
PP3V3_S5_SB_RTC
1
20%
2 6.3V
X5R
603
C25301 C2529
0.1UF
PLACEMENT NOTE:
0.1UF
10%
PLACE CAPS NEAR PIN W5 OF SB
16V
2 X5R
402

10%
2 16V
X5R
402

SIZE
0
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE

25
OF
D
104
RTC Battery Connector

63
SYM_1
VOLTAGE=3.3V
1K
5%
1/16W
MF-LF
402
NC
518S0226
PPVBATT_G3C_RTC_R
10%
2 6.3V
CERM
402
C2610
1UF
R2607
PPVBATT_G3C_RTC
SOT-363
=PP3V42_G3H_SB_RTC
1
NC
21 24 25
BAT54DW
F-RT-SM
PP3V3_S5_SB_RTC
MAKE_BASE=TRUE
VOLTAGE=3.3V
D2600
J2600
88460-0201
3
=PP3V3_S0_SB_PCI
63
PP3V3_G3C_SB_RTC_D
CRITICAL
40 22
IO
40 22
IO
40 22
IO
40 22
IO
40 22
IO
40 22
IO
40 22
IO
VOLTAGE=3.3V
NC 2
5 NC
NC
R2600
NC
NOTE: R2607 and D2600 form the doublefault protection for RTC battery.
20K
22
21
5%
1/16W
MF-LF
402
SB_RTC_RST_L
OUT
IN
22
IN
22
IN
40 22
IN
C2605
1UF
10%
2 6.3V
CERM
402
R2606
1M
5%
1/16W
MF-LF
2 402
21
SB_SM_INTRUDER_L
OUT
IO
22
22
IO
22
IO
22
IO
40 22
IO
22
IO
22
IO
22
IO
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_SERR_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_LOCK_L
PCI_REQ0_L
PCI_REQ1_L
PCI_REQ2_L
PCI_REQ3_L
INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
SB_GPIO2
SB_GPIO3
SB_GPIO4
R2623
R2624
R2625
R2626
R2627
R2628
R2630
R2629
R2632
R2631
R2633
R2634
R2637
R2636
R2638
R2639
R2640
R2642
R2641
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
1
1
1
1
2
2
2
2
8.2K
8.2K
8.2K
8.2K
1
1
1
1
1
1
1
2
2
2
2
2
2
2
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
Platform Reset Connections

SB RTC Crystal Circuit
5%
1/16W
MF-LF
402
R26091
10M
CRITICAL
Y2600
5%
1/16W
MF-LF
402 2
21
SM-2
NC
NC
32.768K
R2696
IN
XDP_DBRESET_L
1K
5%
50V
CERM
402
IN
PLT_RST_L
MAKE_BASE=TRUE
100K
5%
1/16W
MF-LF
402 2
LIO_PLT_RESET_L 5 45
LIO represents X loads (2?)
5%
1/16W
MF-LF
402
OUT
R26981
This part is never stuffed,

it provides a set of pads
on the board to short or
to solder a reset button.
12pF
PM_SYSRST_L
MAKE_BASE=TRUE
OMIT
5%
1/16W
MF-LF
402
C2609
22
47
23 5
R2685
10K
5%
1/16W
MF-LF
402 2
ITP
5%
50V
CERM
402
SB_RTC_X2
Unbuffered
R26971
12pF
SB_RTC_X1_R
3
2 4
SB_RTC_X1
=PP3V3_S5_SB_PM
C2608
R2610
21
63 23 11
NB_RST_IN_L
100-ohm on NB page
R2687
Silk: "SYS RST"
PEG_RESET_L
14
65
5%
1/16W
MF-LF
402
63
=PP3V3_S0_RSTBUF
Buffered
5
1
MC74VHC1G08
SC70
PLT_RST_BUF_L
U2680 4
R2681
1
C2680
0.1UF
20%
10V
2 CERM
402
R2684
5%
1/16W
MF-LF
402
R2680
100K
5%
1/16W
MF-LF
2 402
R2683
1
1
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
63 26
=PP3V3_S0_SB_PM
63 26
C2611
MC74VHC1G00
=PP3V3_S0_SB_PM
R2611
20%
10V
CERM 2
402
56
ENET_RST_L
37
1.8K
5%
1/16W
MF-LF
2 402
U2603 2
MC74VHC1G08
57
VR_PWRGD_CK410_L
IN
OUT
23
PM_SB_PWROK
5
1
SC70
4
U2601 2
R26121
VR_PWRGOOD_DELAY
IN
62 47
ALL_SYS_PWRGD
IN
R2622
5%
1/16W
MF-LF
402 2
CK410_PD_VTT_PWRGD_L
57
14
10K
OUT
TPM_LRESET_L
R2682
MAKE_BASE=TRUE
33
47
Initial resistor values are based on CRB,

but may change after characterization.
0.1UF
SC70-5
4
VR_PWRGD_CK410
SMC_LRESET_L
5%
1/16W
MF-LF
402
C2607 1
20%
10V
CERM 2
402
23
0.1UF
OUT
100
DEBUG_RST_L
5 49
Linda Card represents 3 loads
10K
5%
1/16W
MF-LF
2 402
1G00 used as small & cheap inverter
SB Misc
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
26
OF
D
104
ICH7-M SMBus Connections

63
63
R27001
ICH7-M
4.7K
U2100
(MASTER)
23
SMB_CLK
23
SMB_DATA
SMC "0" SMBus Connections
=PP3V3_S0_SMBUS_SB
5%
1/16W
MF-LF
402 2
SMBUS_SB_SCL
R2701
4.7K
5%
1/16W
MF-LF
2 402
Clock Chip
SMC
CY28445-5: U3301
(Write: 0xD2 Read: 0xD3)
U5800
(MASTER)
4.7K
5%
1/16W
MF-LF
402 2
33
47
SMB_0_S0_CLK
SMB_CK410_DATA
33
47
SMB_0_S0_DATA
63
R2751
4.7K
5%
1/16W
MF-LF
2 402
Right-Side Temp
SMC
ADT7461: U6150
(Write: 0x98 Read: 0x99)
U5800
(MASTER)
SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
=PP3V3_S0_SMBUS_SMC_B_S0
R27601
R2761
4.7K
5%
1/16W
MF-LF
402 2
=SMBUS_RSTHMSNS_SCL
50
47
SMB_B_S0_CLK
=SMBUS_RSTHMSNS_SDA
50
47
SMB_B_S0_DATA
CPU Temp
ADT7461: U1001
5%
1/16W
MF-LF
2 402
SMBUS_SMC_B_S0_SCL
SMB_THRM_CLK
10
SMB_THRM_DATA
10
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
4.7K
MAKE_BASE=TRUE
SMBUS_SB_SDA
SMC "B" SMBus Connections
=PP3V3_S0_SMBUS_SMC_0_S0
R27501
SMB_CK410_CLK
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
SO-DIMM "A"
GPU Temp
J2800
(Write: 0xA0 Read: 0xA1)
MAX6695: U6100
Left I/O Board
Left I/O SMBus Connections:
J5400
(See Table)
LIO - TMP105
=I2C_SODIMMA_SCL
28
=SMBUS_GPUTHMSNS_SCL
50
=SMBUS_LIO_SMC_SCL
5 45
=I2C_SODIMMA_SDA
28
=SMBUS_GPUTHMSNS_SDA
50
=SMBUS_LIO_SMC_SDA
5 45
SO-DIMM "B"
Ambient Thermal
J2900
(Write: 0xA4 Read: 0xA5)
TMP105: J4930
=I2C_SODIMMB_SCL
29
=SMBUS_ATS_SCL
5 43
=I2C_SODIMMB_SDA
29
=SMBUS_ATS_SDA
5 43
SMC "Battery A" SMBus Connections

63
=PP3V42_G3H_SMBUS_SMC_BSA
R27801
SMC
Trackpad I2C Connections:
Trackpad
SMC "A" SMBus Connections
J4900
(See Table)
U1 - Trackpad Controller
U2 - Keyboard Controller
=I2C_TRACKPAD_SCL
43
=I2C_TRACKPAD_SDA
43
63
R27701
Left I/O SMBus Connections:
Left I/O Board

J5500
(See Table)
M35 - TMP105
4.7K
U5800
(MASTER)
47
SMB_A_S3_CLK
47
SMB_A_S3_DATA
5%
1/16W
MF-LF
402 2
R2781
4.7K
Battery
J8250
5%
1/16W
MF-LF
2 402
SMBUS_SMC_BSA_SCL
=SMBUS_BATT_SCL
5 64
=SMBUS_BATT_SDA
5 64
MAKE_BASE=TRUE
47
=PP3V3_S3_SMBUS_SMC_A_S3
SMC
5%
1/16W
MF-LF
402 2
SMB_BSA_CLK
NOTE: SMC RMT bus remains powered and may be active in S3 state
4.7K
U5800
(MASTER)
SMB_BSA_DATA
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
R2771
4.7K
SMC "Battery B" SMBus Connections
5%
1/16W
MF-LF
2 402
SMBUS_SMC_A_S3_SCL
63
=PP3V3_S0_SMBUS_SMC_BSB
MAKE_BASE=TRUE
ExpressCard Slot
=SMBUS_LIO_SB_SCL
5 45
(Address determined by ARP)
=SMBUS_LIO_SB_SDA
5 45
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
R27901
SMC
Top-Case
Top-Case SMBus Connections:
J4900
(See Table)
Left Temp - TMP105
100K
U5800
(MASTER)
47
SMB_BSB_CLK
47
SMB_BSB_DATA
Right Temp - TMP105
=SMBUS_TOPCASE_SCL
43
=SMBUS_TOPCASE_SDA
43
5%
1/16W
MF-LF
402 2
R2791
100K
5%
1/16W
MF-LF
2 402
SMBUS_SMC_BSB_SCL
MAKE_BASE=TRUE
SMBUS_SMC_BSB_SDA
MAKE_BASE=TRUE
Left ALS - TSL2561

M1 SMBus Connections
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
27
OF
D
104
Page Notes
32 29
Power aliases required by this page:

- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)
2.2uF
20%
6.3V
CERM1 2
603
C2800
15
0.1uF
15
20%
2 10V
CERM
402
15
15
BOM options provided by this page:

(NONE)
1A
3A
5A
7A
9A
11A
13A
15A
17A
19A
21A
23A
25A
27A
29A
31A
33A
35A
37A
39A
MEM_VREF
C2801
Signal aliases required by this page:

- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
203
201
=PP1V8_S3_MEM
15
15
NOTE: This page does not supply VREF.

The reference voltage must be provided
by another page.
15
15
15
15
15
15
15
15
15
15
15
15
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DQ<20>
MEM_A_DQ<16>
15
MEM_A_DQ<28>
MEM_A_DQ<25>
15
MEM_A_DM<3>
15
NC
15
"Lower" (surface-mount) slot
15
30 14
MEM_A_DQ<27>
MEM_A_DQ<30>
MEM_CKE<0>
NC
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 14
30 14
15
15
15
15
15
15
15
15
15
15
15
15
15
MEM_A_BS<2>
MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
MEM_A_A<10>
MEM_A_BS<0>
MEM_A_WE_L
MEM_A_CAS_L
MEM_CS_L<1>
MEM_ODT<1>
MEM_A_DQ<35>
MEM_A_DQ<39>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQ<37>
MEM_A_DQ<33>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DM<7>
MEM_A_DQ<58>
MEM_A_DQ<61>
MEM_A_DQ<43>
MEM_A_DQ<45>
NC
15
15
15
15
15
15
15
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DQ<41>
MEM_A_DQ<46>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DM<6>
MEM_A_DQ<53>
15 MEM_A_DQ<48>
=PPSPD_S0_MEM
27 =I2C_SODIMMA_SDA
27 =I2C_SODIMMA_SCL
15
63 29
41A
43A
45A
47A
49A
51A
53A
55A
57A
59A
61A
63A
65A
67A
69A
71A
73A
75A
77A
79A
81A
83A
85A
87A
89A
91A
93A
95A
97A
99A
101A
103A
105A
107A
109A
111A
113A
115A
117A
119A
121A
123A
125A
127A
129A
131A
133A
135A
137A
139A
141A
143A
145A
147A
149A
151A
153A
155A
157A
159A
161A
163A
165A
167A
169A
171A
173A
175A
177A
179A
181A
183A
185A
187A
189A
191A
193A
195A
197A
199A
VREF
VSS1
CRITICAL VSS0
DQ0
J2800
DQ1
VSS4
F-RT-SM
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8
DQ9
VSS10
DQ4
DQ5
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1
VSS11
DQS1*
DQS1
CK0
CK0*
VSS12
VSS13
DQ10
DQ11
DQ14
DQ15
VSS14
VSS15
KEY
VSS16
DQ16
VSS17
DQ20
DQ17
DQ21
VSS18
DQS2*
VSS19
NC0
DQS2
DM2
VSS21
DQ18
VSS22
DQ22
DQ19
VSS23
DQ23
VSS24
DQ24
DQ28
DQ25
VSS25
DQ29
VSS26
DM3
DQS3*
NC1
VSS27
DQS3
VSS28
DQ30
DQ26
DQ27
VSS29
CKE0
VDD0
DQ31
VSS30
NC/CKE1
VDD1
NC2
NC/A15
BA2
VDD2
NC/A14
VDD3
A12
A11
A9
A8
A7
A6
VDD4
VDD5
A5
A3
A4
A2
A1
VDD6
A0
VDD7
A10/AP
BA1
BA0
WE*
RAS*
S0*
VDD8
VDD9
CAS*
NC/S1*
ODT0
NC/A13
VDD10
VDD11
NC/ODT1
VSS31
NC3
VSS32
DQ32
DQ33
DQ36
DQ37
VSS33
VSS34
DQS4*
DQS4
DM4
VSS35
VSS36
DQ38
DQ39
VSS37
DQ34
DQ35
VSS38
DQ44
DQ45
VSS39
DQ40
DQ41
VSS40
DM5
DQS5*
DQS5
VSS41
VSS42
DQ42
DQ43
DQ46
DQ47
VSS43
VSS44
DQ48
DQ49
DQ52
DQ53
VSS45
VSS46
NC_TEST
VSS47
CK1
CK1*
DQS6*
DQS6
VSS48
DM6
VSS49
VSS50
DQ50
DQ51
DQ54
DQ55
VSS51
VSS52
DQ56
DQ57
DQ60
DQ61
VSS53
VSS54
DM7
VSS55
DQS7*
DQS7
DQ58
DQ59
VSS56
DQ62
VSS57
DQ63
VSS58
SA0
SDA
SCL
VDDSPD
516S0382
=PP1V8_S3_MEM
NC
SA1
202
204
2A
4A
6A
8A
10A
12A
14A
16A
18A
20A
22A
24A
26A
28A
30A
32A
34A
36A
38A
40A
42A
44A
46A
48A
50A
52A
54A
56A
58A
60A
62A
64A
66A
68A
70A
72A
74A
76A
78A
80A
82A
84A
86A
88A
90A
92A
94A
96A
98A
100A
102A
104A
106A
108A
110A
112A
114A
116A
118A
120A
122A
124A
126A
128A
130A
132A
134A
136A
138A
140A
142A
144A
146A
148A
150A
152A
154A
156A
158A
160A
162A
164A
166A
168A
170A
172A
174A
176A
178A
180A
182A
184A
186A
188A
190A
192A
194A
196A
198A
200A
5
63 29 28
DDR2-SODIMM-DUAL
MEM_A_DQ<8>
MEM_A_DQ<12>
MEM_A_DM<1>
MEM_A_DQ<15>
MEM_A_DQ<9>
15
15
15
15
15
MEM_A_DQ<2>
MEM_A_DQ<3>
15
MEM_A_DM<0>
15
MEM_CLK_P<0>
MEM_CLK_N<0>
MEM_A_DQ<1>
MEM_A_DQ<0>
MEM_A_DQ<23>
MEM_A_DQ<22>
DIMM_OVERTEMP_L
MEM_A_DM<2>
MEM_A_DQ<21>
MEM_A_DQ<17>
MEM_A_DQ<29>
MEM_A_DQ<24>
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MEM_A_DQ<26>
MEM_A_DQ<31>
MEM_CKE<1>
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
15
14
14
15
15
15
15
29 48
15
15
15
15
15
15
15
15
15
14 30
6
6
DDR2 Bypass Caps
15 30
15 30
(For return current)
15 30
63 29 28
MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<0>
28 29 63
=PP1V8_S3_MEM
15 30
15 30
15 30
C2808
10UF
MEM_A_BS<1>
MEM_A_RAS_L
MEM_CS_L<0>
14 30
MEM_ODT<0>
MEM_A_A<13>
15 30
15 30
15 30
14 30
C2810
20%
2 10V
CERM
402
NC
MEM_A_DM<4>
MEM_A_DQ<32>
MEM_A_DQ<36>
MEM_A_DQ<57>
MEM_A_DQ<63>
MEM_A_DQ<56>
MEM_A_DQ<62>
MEM_A_DQ<40>
MEM_A_DQ<42>
C2811
0.1uF
C2812
0.1uF
20%
2 10V
CERM
402
C2814
0.1uF
15
20%
2 10V
CERM
402
15
0.1uF
C2815
0.1uF
20%
2 10V
CERM
402
C2816
0.1uF
20%
2 10V
CERM
402
C2817
0.1uF
20%
2 10V
CERM
402
15
15
15
C2818
20%
2 10V
CERM
402
15
15
C2819
0.1uF
20%
2 10V
CERM
402
C2820
0.1uF
20%
2 10V
CERM
402
C2821
0.1uF
20%
2 10V
CERM
402
15
15
15
15
MEM_A_DM<5>
15
14
DDR2 SO-DIMM Connector A
15
15
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
C2813
20%
2 10V
CERM
402
15
14
MEM_A_DQ<54>
MEM_A_DQ<55>
15
MEM_CLK_P<1>
MEM_CLK_N<1>
MEM_A_DQ<47>
MEM_A_DQ<44>
20%
2 10V
CERM
402
0.1uF
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
C2809
20%
2 6.3V
X5R
603
0.1uF
MEM_A_DQ<38>
MEM_A_DQ<34>
10UF
20%
2 6.3V
X5R
603
15
SYNC_DATE=(MASTER)
15

15
15
MEM_A_DQ<52>
MEM_A_DQ<49>
15
15
SIZE
APPLE COMPUTER INC.
ADDR=0xA0(WR)/0xA1(RD)
DRAWING NUMBER
SCALE
NC
SHT
NONE
REV.
051-7099
28
OF
D
104
Page Notes
32 28
MEM_VREF
C2901
1B
2.2uF
20%
6.3V
CERM1 2
603

- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
C2900
15
0.1uF
15
20%
2 10V
CERM
402
MEM_B_DQ<15>
MEM_B_DQ<14>
5B
7B
9B
15
15
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
11B
13B
15B

(NONE)
15
15
MEM_B_DQ<10>
MEM_B_DQ<13>
17B
19B
21B
NOTE: This page does not supply VREF.

The reference voltage must be provided
by another page.
15
15
MEM_B_DQ<7>
MEM_B_DQ<2>
23B
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
29B
25B
27B
15
15
31B
33B
15
15
MEM_B_DQ<1>
MEM_B_DQ<4>
35B
37B
39B
41B
15
15
MEM_B_DQ<21>
MEM_B_DQ<19>
43B
45B
47B
15
15
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
49B
51B
53B
15
15
MEM_B_DQ<20>
MEM_B_DQ<23>
55B
57B
59B
15
15
MEM_B_DQ<29>
MEM_B_DQ<24>
61B
63B
65B
15
MEM_B_DM<3>
67B
NC
69B
71B
15
"Upper" (thru-hole) slot
15
MEM_B_DQ<27>
MEM_B_DQ<25>
73B
75B
77B
30 14
MEM_CKE<2>
79B
81B
NC
30 15
MEM_B_BS<2>
83B
85B
87B
30 15
30 15
30 15
MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>
89B
91B
93B
95B
30 15
30 15
30 15
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
97B
99B
101B
103B
30 15
30 15
30 15
MEM_B_A<10>
MEM_B_BS<0>
MEM_B_WE_L
105B
107B
109B
111B
30 15
30 14
MEM_B_CAS_L
MEM_CS_L<3>
113B
115B
117B
30 14
MEM_ODT<3>
119B
121B
15
15
MEM_B_DQ<36>
MEM_B_DQ<33>
123B
125B
127B
15
15
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
129B
131B
133B
15
15
MEM_B_DQ<34>
MEM_B_DQ<35>
135B
137B
139B
15
15
MEM_B_DQ<40>
MEM_B_DQ<41>
141B
143B
145B
15
MEM_B_DM<5>
147B
149B
15
15
MEM_B_DQ<42>
MEM_B_DQ<43>
151B
153B
155B
15
15
MEM_B_DQ<62>
MEM_B_DQ<59>
157B
159B
161B
NC
163B
165B
15
15
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
167B
169B
171B
15
15
MEM_B_DQ<60>
MEM_B_DQ<61>
173B
175B
177B
15
15
MEM_B_DQ<54>
MEM_B_DQ<51>
179B
181B
183B
15
MEM_B_DM<6>
185B
187B
MEM_B_DQ<52>
15 MEM_B_DQ<49>
=PPSPD_S0_MEM
27 =I2C_SODIMMB_SDA
27 =I2C_SODIMMB_SCL
189B
15
63 29 28
191B
193B
195B
197B
199B
VREF
VSS1
CRITICAL VSS0
DQ0
J2900
DQ1
VSS4
F-RT-TH1
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8
DQ9
DQ4
DQ5
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1
VSS10
VSS11
DQS1*
DQS1
CK0
CK0*
VSS12
VSS13
DQ10
DQ11
DQ14
DQ15
VSS14
VSS15
KEY
VSS16
DQ16
DQ17
VSS18
DQS2*
DQS2
VSS17
DQ20
DQ21
VSS19
NC0
DM2
VSS21
DQ18
VSS22
DQ22
DQ19
VSS23
DQ23
VSS24
DQ24
DQ28
DQ25
VSS25
DQ29
VSS26
DM3
DQS3*
NC1
VSS27
DQS3
VSS28
DQ26
DQ27
VSS29
CKE0
VDD0
DQ30
DQ31
VSS30
NC/CKE1
VDD1
NC2
NC/A15
BA2
VDD2
NC/A14
VDD3
A12
A11
A9
A8
VDD4
A7
A6
VDD5
A5
A3
A1
VDD6
A10/AP
BA0
WE*
VDD8
CAS*
NC/S1*
A4
A2
A0
VDD7
BA1
RAS*
S0*
VDD9
ODT0
NC/A13
VDD10
VDD11
NC/ODT1
VSS31
NC3
VSS32
DQ32
DQ33
VSS33
DQ36
DQ37
VSS34
DQS4*
DQS4
DM4
VSS35
VSS36
DQ38
DQ34
DQ35
VSS38
DQ40
DQ41
DQ39
VSS37
DQ44
DQ45
VSS39
VSS40
DM5
DQS5*
DQS5
VSS41
VSS42
DQ42
DQ43
VSS43
DQ48
DQ49
VSS45
NC_TEST
VSS47
DQ46
DQ47
VSS44
DQ52
DQ53
VSS46
CK1
CK1*
DQS6*
DQS6
VSS48
DM6
VSS49
VSS50
DQ50
DQ51
VSS51
DQ56
DQ57
DQ54
DQ55
VSS52
DQ60
DQ61
VSS53
VSS54
DM7
VSS55
DQS7*
DQS7
DQ58
DQ59
VSS57
SDA
SCL
VDDSPD
516-0140
=PP1V8_S3_MEM
201NC
3B

- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)
=PP1V8_S3_MEM
VSS56
DQ62
DQ63
VSS58
SA0
SA1
5
63 29 28
DDR2-SODIMM-DUAL
28 29 63
2B
MEM_B_DQ<9>
MEM_B_DQ<11>
4B
6B
15
15
8B
MEM_B_DM<1>
10B
15
12B
MEM_B_DQ<12>
MEM_B_DQ<8>
14B
16B
15
15
18B
MEM_B_DQ<3>
MEM_B_DQ<6>
20B
22B
15
15
24B
MEM_B_DM<0>
26B
15
28B
MEM_CLK_P<3>
MEM_CLK_N<3>
30B
32B
14
14
34B
MEM_B_DQ<0>
MEM_B_DQ<5>
36B
38B
15
15
40B
42B
MEM_B_DQ<22>
MEM_B_DQ<18>
44B
46B
15
15
48B
DIMM_OVERTEMP_L
MEM_B_DM<2>
50B
52B
28 48
15
54B
MEM_B_DQ<17>
MEM_B_DQ<16>
56B
58B
15
15
60B
MEM_B_DQ<26>
MEM_B_DQ<28>
62B
64B
15
15
66B
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
68B
70B
15
15
72B
MEM_B_DQ<31>
MEM_B_DQ<30>
74B
76B
15
15
78B
MEM_CKE<3>
80B
14 30
82B
MEM_B_A<15>
MEM_B_A<14>
84B
86B
6
6
DDR2 Bypass Caps
88B
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>
90B
92B
94B
15 30
15 30
(For return current)
15 30
96B
63 29 28
MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>
98B
100B
102B
=PP1V8_S3_MEM
15 30
15 30
15 30
C2908
10UF
104B
MEM_B_BS<1>
MEM_B_RAS_L
MEM_CS_L<2>
106B
108B
110B
15 30
15 30
C2909
10UF
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
14 30
112B
MEM_ODT<2>
MEM_B_A<13>
114B
116B
14 30
15 30
120B
C2910
0.1uF
118B
20%
2 10V
CERM
402
NC
122B
MEM_B_DQ<32>
MEM_B_DQ<37>
124B
126B
MEM_B_DM<4>
MEM_B_DQ<38>
MEM_B_DQ<39>
136B
0.1uF
20%
2 10V
CERM
402
C2912
0.1uF
20%
2 10V
CERM
402
C2913
0.1uF
20%
2 10V
CERM
402
15
C2914
0.1uF
15
20%
2 10V
CERM
402
132B
134B
C2911
15
128B
130B
15
C2915
0.1uF
20%
2 10V
CERM
402
C2916
0.1uF
20%
2 10V
CERM
402
C2917
0.1uF
20%
2 10V
CERM
402
15
138B
MEM_B_DQ<44>
MEM_B_DQ<45>
140B
142B
15
15
C2918
0.1uF
144B
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
146B
148B
20%
2 10V
CERM
402
15
15
C2919
0.1uF
20%
2 10V
CERM
402
C2920
0.1uF
20%
2 10V
CERM
402
C2921
0.1uF
20%
2 10V
CERM
402
150B
MEM_B_DQ<46>
MEM_B_DQ<47>
152B
154B
15
15
156B
MEM_B_DQ<58>
MEM_B_DQ<63>
158B
160B
15
15
162B
164B
166B
MEM_CLK_P<2>
MEM_CLK_N<2>
14
MEM_B_DM<7>
15
14
168B
170B
172B
MEM_B_DQ<56>
MEM_B_DQ<57>
174B
176B
DDR2 SO-DIMM Connector B
15
15
178B
MEM_B_DQ<55>
MEM_B_DQ<50>
180B
182B
15
15
184B
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
186B
188B
15
=PPSPD_S0_MEM

28 29 63
15
190B
MEM_B_DQ<53>
15
MEM_B_DQ<48>
15
Resistor prevents pwr-gnd short
192B
194B
196B
198B
R2900
10K
5%
1/16W
MF-LF
2 402
SIZE
APPLE COMPUTER INC.
SODIMM_A_SA1
200B
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
ADDR=0xA4(WR)/0xA5(RD)
202 NC
SYNC_DATE=(MASTER)
29
OF
D
104
One cap for each side of every RPAK, one cap for every two discrete resistors
Ensure CS_L and ODT resistors are close to SO-DIMM connector
63
29 28 14
IN
MEM_CS_L<3..0>
R3000
R3001
R3002
R3003
56
56
56
56
RP3032
RP3032
RP3058
RP3058
56
56
56
56
1
2
4
3
R3010
R3011
R3012
R3013
56
56
56
56
RP3034
RP3010
RP3034
RP3034
RP3034
RP3030
RP3032
RP3030
RP3032
RP3030
RP3036
RP3030
RP3005
RP3036
56
56
56
56
56
56
56
56
56
56
56
56
56
56
3
1
2
4
1
2
3
1
4
4
3
3
3
2
1
2
3
29 28 14
IN
MEM_CKE<3..0>
0
1
2
3
29 28 14
IN
MEM_ODT<3..0>
0
1
2
3
28 15
IN
MEM_A_A<13..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
=PP0V9_S0_MEM_TERM
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
8
7 5%
5 5%
6 5%
5%
1/16W
1/16W
1/16W
1/16W
SM-LF
SM-LF
SM-LF
SM-LF
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
6
8
7
5
8
7
6
8
5
5
6
6
6
7
402
402
402
402
C3000
0.1uF
20%
10V
2 CERM
402
C3005
20%
2 10V
CERM
402
402
402
402
402
C3010
IN
MEM_A_BS<2..0>
0
1
2
28 15
IN
28 15
IN
28 15
IN
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
29 15
IN
MEM_B_A<13..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
RP3036
RP3036
RP3005
56
56
56
1
4
4
RP3010
RP3010
RP3010
56
56
56
3
4
2
RP3005
RP3050
RP3050
RP3052
RP3054
RP3052
RP3054
RP3054
RP3058
RP3058
RP3050
RP3056
RP3056
RP3052
56
56
56
56
56
56
56
56
56
56
56
56
56
56
2
3
4
3
2
1
3
4
1
2
2
3
2
4
8
5 5%
5 5%
5%
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
6
5 5%
7 5%
5%
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
7
6
5
6
7
8
6
5
8
7
7
6
7
5
C3030
0.1uF
20%
2 10V
CERM
402
C3032
0.1uF
20%
10V
2 CERM
402
C3034
0.1uF
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
C3036
0.1uF
20%
10V
2 CERM
402
C3038
0.1uF
20%
10V
2 CERM
402
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
C3050
IN
MEM_B_BS<2..0>
0
1
2
29 15
IN
29 15
IN
29 15
IN
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
RP3056
RP3005
RP3056
56
56
56
4
1
1
RP3050
RP3054
RP3052
56
56
56
1
1
2
5
8 5%
8 5%
5%
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
8
8 5%
7 5%
5%
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
20%
10V
2 CERM
402
C3052
0.1uF
C3054
0.1uF
C3056
0.1uF
20%
2 10V
CERM
402
C3011
0.1uF
20%
2 10V
CERM
402
C3031
0.1uF
20%
2 10V
CERM
402
C3033
0.1uF
20%
10V
2 CERM
402
C3035
0.1uF
20%
10V
2 CERM
402
C3037
0.1uF
20%
10V
2 CERM
402
C3039
0.1uF
20%
10V
2 CERM
402
C3051
0.1uF
20%
10V
2 CERM
402
0.1uF
20%
2 10V
CERM
402
C3007
20%
2 10V
CERM
402
0.1uF
20%
2 10V
CERM
402
29 15
0.1uF
0.1uF
20%
2 10V
CERM
402
C3002
20%
10V
2 CERM
402
0.1uF
20%
10V
2 CERM
402
28 15
C3053
0.1uF
20%
2 10V
CERM
402
C3055
0.1uF
20%
10V
2 CERM
402
C3057
0.1uF
20%
2 10V
CERM
402
Memory Active Termination

1
C3058
0.1uF
20%
10V
2 CERM
402
C3059
SYNC_DATE=(MASTER)
0.1uF
20%
10V
2 CERM
402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
30
OF
D
104
Page Notes
- =PP5V_S0_MEMVTT
- =PP1V8_S0_MEMVTT
- =PP0V9_S0_MEMVTT_LDO
(NONE)
(NONE)
DDR2 Vtt Regulator

C
63
=PP5V_S0_MEMVTT
63
=PP1V8_S0_MEMVTT
R3104
2
220
5%
1/16W
MF-LF
402
If power inputs are not S0,

MEMVTT_EN can be used to
disable MEMVTT in sleep.
PP1V8_S0_MEMVTT_VDDQ
VOLTAGE=1.8V
R3100
1K
5%
1/16W
MF-LF
2 402
C3104 1
2.2uF
20%
6.3V
CERM1 2
603
5
VDDQ
C3101
BD3533FVM
MSOP-8
2 EN
10uF
20%
6.3V 2
X5R
603
6
VCC
10%
2 6.3V
CERM
402
U3100
7 VTT_IN
MEMVTT_EN
C3100
1uF
MEMVTT_EN_PU
1
Okay to turn off 5V and

leave 1.8V powered in S3.
MEMVTT_VREF
VTTS 3
VTT 8
C3103
0.1uF
VREF 4
CRITICAL
1
10uF
20%
2 6.3V
X5R
603
GND
10%
2 16V
X5R
402
C3102
=PP0V9_S0_MEMVTT_LDO
63
C3105
150UF
20%
6.3V
POLY
SMC-LF
Memory Vtt Supply

SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
31
OF
D
104
63
=PP3V3_S3_MEMVREF
MEMVREF_S3
C3200 1
R32021
0.1UF
100K
20%
10V
CERM 2
402
63
5%
1/16W
MF-LF
402 2
=PP1V8_S3_MEMVREF
CRITICAL
R32051
U3200
10K
1%
1/16W
MF-LF
402 2
V+
MEMVREF_UNBUF
R32061
10K
1%
1/16W
MF-LF
402 2
VOLTAGE=0.9V
MAX4236EUTT
SOT23-6-LF
1
MEMVREF_OUT
5
V-
28 29
14
14
MEMVREF_S0
C3205 1
R3203
220pF
5%
25V
CERM 2
402
MEM_VREF
MEM_VREF_NB_0
MEM_VREF_NB_1
VOLTAGE=0.9V
MAKE_BASE=TRUE
MEMVREF_SHDN_L
62
=MEMVREF_EN
IN
5%
1/16W
MF-LF
402
DDR2 VRef
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
32
OF
D
104
R3302
2.2
PP3V3_S0_CK410_VDD48
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
20%
2 6.3V
X5R
603
402
33 34 63
0402
5%
10%
L3302
FERR-120-OHM-1.5A
1
2
=PP3V3_S0_CK410
1/16W
1 C3309
MF-LF
C3308
402
0.1UF 10UF
2 16V
X5R
C3310
1UF
10%
2 6.3V
CERM
402
D
L3301
FERR-120-OHM-1.5A
PP3V3_S0_CK410_VDD_CPU_SRC
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C3312
C3311
10UF 0.1UF
C3307
0.1UF
10%
10%
2 16V
X5R
2 16V
X5R
402
402
Y3301
VDD48
14.31818
1
2
5X3.2-SM
1 C3390
C3389
18pF
18pF
5%
50V
2 CERM
402
U3301
5%
50V
2 CERM
402
QFN
38
39
CK410_XTAL_IN
CK410_XTAL_OUT
=PP3V3_S0_CK410
34
R3301
10K
CK410_PCIF0_CLK
CK410_FSB_TEST_MODE
8
34
IO
OUT
51
50
57
(FW PCI 33MHZ)OUT CK410_PCI1_CLK
58
(TPM LPC 33MHZ)
OUT CK410_PCI2_CLK
CK410_PCI3_CLK
63
(SMC LPC 33MHZ)
OUT
CK410_PCI4_CLK
64
(NO USED)
OUT
5%
1/16W
MF-LF
2402
34
IN
34
CK410_PCI5_FCTSEL1
65
(INT PD)
(PORT80 LPC 33MHZ)
CK410_PCIF1_CLK
(ICH7M PCI 33MHZ)
OUT
(PULL UP PIN 68 TO ENABLE ITP HOST CLK)

SMB_CK410_CLK
(ICH SM BUS) IN SMB_CK410_DATA
27
IO
CK410_IREF
68
1
47
48
40
CY284455
OMIT
PCI_STP*
CPU_STP*
CRITICAL
VDDA
VSSA
CPUC1
CPUT1
41
42
CPUC2_ITP/SRCC_10
36
37
XOUT
CPUT2_ITP/SRCT_10
SRCC_0/LCD100MC
PCI1
PCI2
PCI3
SRCT_0/LCD100MT
(INT PU)
CLKREQ_1*
SRCC_2
SRCT_2
16
15
SRCC_3
19
18
59
SRCT_1
PCIF0/ITP_SEL
PCIF1
SCLK
SDATA
(INT
IREF
SRCT_3
PU)
CLKREQ_3*
SRCT_4
R3300
475
1%
1/16W
MF-LF
2402
(INT PU)
CLKREQ_4*
VSS48
46
VSS_CPU
62
66
VSS_PCI0
52
VSS_REF
31
VSS_SRC
69
SRCC_5
SRCT_5
(INT PU)
CLKREQ_5*
VSS_PCI1
34
34
SRCC_8
32
33
34
SRCT_8
(INT PU)
CLKREQ_8*
DOT96C/27MHZ_SPREAD
DOT96T/27MHZ_NON-SPREAD
7
6
(INT PD)
VTT_PWRGD*/PD 2
FSA/48M 4
REF0/FSC 54
(INT PD)
REF1/FCTSEL0 53
IN
OUT
34
OUT
34
OUT
OUT
OUT
34
OUT
34
OUT
34
OUT
34
OUT
34
IN
34
34
OUT
CK410_SRC3_N
CK410_SRC3_P
(FOR PCI-E CARD)
CK410_SRC_CLKREQ3_L
CK410_SRC4_N
CK410_SRC4_P
(ICH SATA 100 MHZ)
34
OUT
34
OUT
IN
34
OUT
34
23
OUT
SB_CLK100M_SATA_OE_L
(FROM ICH7 GPIO35)
(SIGNAL NAME WILL BE CHANGED
PROTO
POST
TO REMOVE 100M FROM SIGNAL NAME)
IN
34
CK410_SRC5_N
CK410_SRC5_P
14
CLK_NB_OE_L
34
34
OUT
IN
(GMCH G_CLKIN 100 MHZ )

(FROM GMCH CLK_REQ*)
OUT
34
OUT
IN
34
OUT
34
OUT
34
OUT
34
OUT
34
34
OUT
CK410_SRC6_N
CK410_SRC6_P
(WIRELESS PCI-E 100 MHZ )
CK410_SRC_CLKREQ6_L
CK410_SRC7_N
(NOT USED )
CK410_SRC7_P
CK410_SRC8_N
(GIGA LAN PCI-E 100 MHZ )
CK410_SRC8_P
CK410_SRC_CLKREQ8_L
CK410_DOT96_27M_N
(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)
CK410_DOT96_27M_P
CK410_PD_VTT_PWRGD_L (FROM CPU VCORE PWR GOOD)
CK410_USB48_FSA
USB 48MHZ)
CK410_CLK14P3M_TIMER (ICH7M
(ICH7M,SIO,LPC REF. 14.318MHZ)
CK410_REF1_FCTSEL0
34
34
GPIO?
OUT
34
SRCC_6 27
SRCT_6 26
CLKREQ_6* 25
(INT PU)
THRML_PAD
23
OUT
24
23
60
30
29
IN
34
22
21
20
SRCC_7
SRCT_7
23
34
11
10
14
13
9
SRCC_1
PCI4
PCI5/FCTSEL1
C
PM_STPPCI_L
(FROM ICH7 GPIO18 STPPCI* )
PM_STPCPU_L
(FROM ICH7 GPIO20 STPCPU* )
CK410_CPU0_N
CK410_CPU0_P
(CPU HOST 133/167MHZ)
CK410_CPU1_N
CK410_CPU1_P
(GMCH HOST 133/167MHZ)
CK410_CPU2_ITP_SRC10_N
CK410_CPU2_ITP_SRC10_P
(ITP HOST 133/167MHZ)
CK410_LVDS_N
CK410_LVDS_P
(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)
CK410_SRC1_N
(GPU PCI-E 100 MHZ )
CK410_SRC1_P
CK410_SRC_CLKREQ1_L
NEED TO DECIDE THE CLKREQ CONNECTION,TO
CK410_SRC2_N
CK410_SRC2_P
(ICH7M DMI 100 MHZ )
56 (INT PU)
55 (INT PU)
CPUT0
XIN
FSB
(EACH POWER PIN PLACED ONE 0.1UF)

(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)
44
45
CPUC0
SRCC_4
5%
1/16W
MF-LF
402
1
CRITICAL
63 34 33
20%
2 6.3V
X5R
603
402
1 1
PP3V3_S0_CK410_VDD_REF
VOLTAGE=3.3V
20%
2 6.3V
X5R
603
10%
2 16V
X5R
402
R3303
5%
1/16W
MF-LF
402
1 C3306
1 C3317
C3305
0.1UF 0.1UF 10UF
10%
PP3V3_S0_CK410_VDDA
VOLTAGE=3.3V
NEED TO CHECK CAP VALUE
2 16V
X5R
10%
2 16V
X5R
402
12
17
28
35
10%
2 16V
X5R
402
VDD_SRC2
VDD_SRC3
R3304
2.2
10%
2 16V
X5R
402
VDD_SRC1
20%
2 6.3V
X5R
603
VDD_SRC0
10%
2 6.3V
CERM
402
VOLTAGE=3.3V
1 C3315
1 C3301
1 C3302
1 C3303
1 C3304
C3316
10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
49
VDD_REF
C3314
1UF
61
67
PP3V3_S0_CK410_VDD_PCI
VOLTAGE=3.3V
0402
43
VDD_PCI0
VDD_PCI1
=PP3V3_S0_CK410
VDD_CPU
63 34 33
IN
OUT
OUT
26
IN
34
OUT
34
OUT
34
IO
CLOCKS
SYNC_MASTER=M42
FCTSEL1FCTSEL0PIN 6 PIN 7 PIN 10

PIN 11
0
0
DOT96T DOT96C 100MT_SST100MC_SST* FOR INT. GRAPHIC SYSTEM
0
1
DOT96T DOT96C SRCT0
SRCC0
27M NON 27M
1
0
SPREAD SPREAD SRCT0
SRCC0
* FOR EXT. GRAPHIC SYSTEM
1
1
OFF LOWTBD
SRCT0
SRCC0

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
33
OF
D
104
R3463
33
33
CK410_PCIF0_CLK
IN
PCI_CLK_PORT80_LPC
5%
1/16W
MF-LF
402
CK410_PCIF1_CLK
IN
33
33
R3432
33
CK410_PCI1_CLK
IN
33
CK410_PCI3_CLK
IN
CK410_PCI4_CLK
IN
33
PCI_CLK_FW
(TO ICH7M PCI 33MHZ)
22
OUT
33
33 IN
PCI_CLK_TPM
5%
1/16W
MF-LF
402
(TO TPM PCI 33MHZ)
56
OUT
33
5%
1/16W
MF-LF
402
(TO SMC PCI 33MHZ)
47
OUT
33
33
TP_CK410_PCI4_CLK
CK410_USB48_FSA
33
SB_CLK48M_USBCTLR
23
5%
1/16W
MF-LF
402
1
(TO ICH7M USB 48MHZ)
OUT
=PP1V05_S0_FSB_NB
NOSTUFF
CK410_CPU1_P
33
5%
1/16W
MF-LF
2 402
IN
CK410_CPU1_N
1K
2 14
33
NB_BSEL<0>
5%
1/16W
MF-LF
402
R3401
OUT
IN
IN
CK410_CPU2_ITP_SRC10_P
IN
IN
IN
IN
IN
IN
CPU_BSEL<0>
IN
33
5%
1/16W
MF-LF
402
R3469
1K
CK410_SRC6_P
33
CK410_SRC5_P
R3470
5%
1/16W
MF-LF
2 402
CK410_SRC2_P
1K
2 14
5%
1/16W
MF-LF
402
NB_BSEL<1>
OUT
(TO MCH FS_B)
R3451
1
IN
CK410_SRC8_N
IN
CK410_SRC4_P
NOSTUFF
1K
CPU_BSEL<1>
IN
IN
CK410_SRC3_P
33
IN
CK410_SRC3_N
(FROM CPU FS_B)
IN
CK410_DOT96_27M_P
CK410_27M_NONSPREAD
IN
CK410_DOT96_27M_N
CK410_27M_SPREAD
MAKE_BASE=TRUE
5%
1/16W
MF-LF
2 402
33
R3473
33
IN
IN
CK410_SRC1_P
CK410_SRC1_N
1K
R3474
IN
33
CK410_CLK14P3M_TIMER
1K
5%
1/16W
MF-LF
402
1K
2 14
NB_BSEL<2>
5%
1/16W
MF-LF
402
CPU_BSEL_R<2>
1
33
NOSTUFF
R3454
1K
33
33
5%
1/16W
MF-LF
402
33
33
121
33
33
5%
1/16W
MF-LF
402
NB_CLK100M_GCLKIN_P
33
34 14
NB_CLK100M_GCLKIN_N
63 33
(TO MCH FS_C)
OUT
R3453
1
33
IN
CK410_SRC7_P
33
IN
CK410_SRC7_N
IN
CK410_LVDS_P
IN
CK410_LVDS_N
33
CPU_BSEL<2>
IN
(FROM CPU FS_C)
5%
1/16W
MF-LF
402
SB_CLK14P3M_TIMER
10K
5%
1/16W
MF-LF
2 402
A
33
IO
CK410_PCI5_FCTSEL1
CK410_REF1_FCTSEL0
1
R3466
10K
5%
1/16W
MF-LF
2 402
79 34 11
49.9 2
CPU_XDP_CLK_N
R3440
1
OUT
45 34 5
PCIE_CLK100M_MINI_N
1%
1/16W
MF-LF
402
OUT
34 14
NB_CLK100M_GCLKIN_P
34 14
NB_CLK100M_GCLKIN_N
45 34 5
22 34
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R3406
1
SB_CLK100M_DMI_P
1%
1/16W
MF-LF
402
34 22
SB_CLK100M_DMI_N
OUT
34 37
37 34
ENET_CLK100M_PCIE_P
37 34
ENET_CLK100M_PCIE_N
34 37
SB_CLK100M_SATA_P
OUT
5 21 34
34 21 5
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
R3407
1
OUT
5 21 34
34 21 5
OUT
5 34 45
45 34 5
R3438
1
45 34 5
49.9 2
OUT
5 34 45
49.9 2
1%
1/16W
MF-LF
402
49.9 2
R3496
1
69 34
OUT
GPU_CLK27M
69 34
GPU_CLK27MSS_IN
69 34
OUT
71.5 2
1%
1/16W
MF-LF
402
(GPU 27MHz Spread / Non-Spread)

GPU_CLK27MSS_IN
R3402
1
65 34
OUT
PEG_CLK100M_GPU_P
49.9 2
1
PEG_CLK100M_GPU_N
1%
1/16W
MF-LF
402
(GPU PCI-E Graphics 100MHz)

65 34
PEG_CLK100M_GPU_N
65 34
OUT
33
71.5 2
1%
1/16W
MF-LF
402
R3490
PEG_CLK100M_GPU_P
49.9 2
1%
1/16W
MF-LF
402
R3405
GPU_CLK27M
R3482
1%
1/16W
MF-LF
402
(ExpressCard Slot)
49.9 2
1%
1/16W
MF-LF
402
R3495
1
49.9 2
1%
1/16W
MF-LF
402
49.9 2
1%
1/16W
MF-LF
402
SB_CLK100M_SATA_N
49.9 2
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
(ICH7M SATA 100MHZ)
49.9 2
1%
1/16W
MF-LF
402
49.9 2
34 22
22 34
49.9 2
R3437
49.9 2
1
OUT
ITP
1%
1/16W
MF-LF
402
R3481
R3491
1
49.9 2
1%
1/16W
MF-LF
402
TP_CK410_SRC7P
MAKE_BASE=TRUE
TP_CK410_SRC7N
MAKE_BASE=TRUE
TP_CK410_LVDSP
MAKE_BASE=TRUE
TP_CK410_LVDSN
MAKE_BASE=TRUE
33
CK410_SRC_CLKREQ3_L
33
CK410_SRC_CLKREQ6_L
EXCARD_CLKREQ_L
5 45
MAKE_BASE=TRUE
MINI_CLKREQ_L
5 45
MAKE_BASE=TRUE
R3485
OUT
23
(ICH7M 14.318MHZ)
33
NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY

FS_C FS_B FS_A CPU
0
0
0
266M
# 0
0
1
133M
# 0
1
0
166M
0
1
1
200M
1
0
0
100M
1
0
1
333M
1
1
0
400M
RESERVED
1
1
1
# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED
R3467
IO
49.9 2
CK410_SRC_CLKREQ1_L
GPU CLK OE*
1K
5%
1/16W
MF-LF
402
CK410_SRC_CLKREQ8_L
Yukon CLK OE*
R3486
1K
5%
1/16W
MF-LF
402
=PP3V3_S0_CK410
1
33
11 34 79
33
5%
1/16W
MF-LF
402
PCIE_CLK100M_MINI_P
OUT
R3476
33
1%
1/16W
MF-LF
402
CPU_XDP_CLK_P
(Yukon PCI-E 100MHZ)

ENET_CLK100M_PCIE_N
5%
1/16W
MF-LF
2 402
ITP
R3439
65 34
FSB_CLK_NB_N
1%
1/16W
MF-LF
402
R3403
34 12
49.9 2
1
OUT
ENET_CLK100M_PCIE_P
R3494
33
FSB_CLK_NB_P
79 34 11
11 34 79
OUT
SB_CLK100M_DMI_N
1%
1/16W
MF-LF
402
34 12
(ICH7M DMI 100MHZ)
R3419
1
12 34
OUT
SB_CLK100M_DMI_P
69 34
121
12 34
49.9 2
1%
1/16W
MF-LF
402
R3431
5%
1/16W
MF-LF
402
49.9 2
1
(GMCH G_CLKIN 100MHZ)
R3499
1
R3400
R3408
5%
1/16W
MF-LF
402
R3493
1
34 14
R3478
1%
1/16W
MF-LF
402
33
PCIE_CLK100M_MINI_N
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
45 34 5
R3426
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
OUT
PCIE_CLK100M_MINI_P
R3428
33
1%
1/16W
MF-LF
402
(WIRELESS PCI-E MINI 100MHZ)
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
FSB_CLK_CPU_N
R3436
R3423
1
OUT
CPU_XDP_CLK_N
5%
1/16W
MF-LF
402
7 34
49.9 2
5%
1/16W
MF-LF
402
R3475
MAKE_BASE=TRUE
33
33
5%
1/16W
MF-LF
402
CK410_SRC4_N
33
33
5%
1/16W
MF-LF
402
R3452
5%
1/16W
MF-LF
2 402
34 7
(ITP HOST 133/167MHZ)
45 34 5
33
FSB_CLK_CPU_P
R3441
R3435
R3418
CPU_BSEL_R<1>
=PP1V05_S0_FSB_NB
CK410_SRC2_N
IN
R3472
5%
1/16W
MF-LF
402
63 34 19 12
OUT
CPU_XDP_CLK_P
5%
1/16W
MF-LF
402
R3498
NEED TO CHECK THE BSEL PULLS
1K
OUT
33
5%
1/16W
MF-LF
402
CK410_SRC5_N
1K
33
OUT
FSB_CLK_NB_N
ITP
34 7
(GMCH HOST 133/167MHZ)
R3416
R3477
33
CK410_SRC6_N
CK410_SRC8_P
=PP1V05_S0_FSB_NB
R3471
R3465
(FROM CPU FS_A)
33 IN
CK410_FSB_TEST_MODE
5%
1/16W
MF-LF
402
OUT
FSB_CLK_NB_P
ITP
33
7 34
R3404
R3412
33
FSB_CLK_CPU_N
5%
1/16W
MF-LF
402
OUT
(CPU HOST 133/167MHZ)
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CK410_CPU2_ITP_SRC10_N
R3450
5%
1/16W
MF-LF
2 402
33
(TO MCH FS_A)

33
CPU_BSEL_R<0>
5%
1/16W
MF-LF
402
63 34 19 12
33
33
R3427
R3468
12 19 34 63
1K
2.2K 2
R3414
R3422
33
R3480
R3442
FSB_CLK_CPU_P
R3434
R3417
33
33
5%
1/16W
MF-LF
402
CK410_CPU0_N
MAKE_BASE=TRUE
IN
R3415
PCI_CLK_SMC
33
33
IN
CK410_CPU0_P
R3411
(TO FIREWIRE PCI 33MHZ)
40
OUT
33
IN
R3430
R3433
33
PCI_CLK_SB
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CK410_PCI2_CLK
IN
33
33
R3429
33
R3413
(PORT80 LPC 33MHZ)
5 49
OUT
Clock Termination
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
34
OF
D
104
TPM Crystal Circuit

C3720
R3721
15pF
5%
1/16W
MF-LF
402
R37201
10M
CRITICAL
Y3720
5%
1/16W
MF-LF
402 2
56
TPM_XTALO_R
2 4
TPM_XTALO
NO STUFF
32.768K
SM-2
NC
NC
56
5%
50V
CERM
402
C3721
15pF
1
TPM_XTALI
5%
50V
CERM
402
SMC G3Hot Oscillator

L3750
63
=PP3V42_G3H_SMC_CLK
FERR-EMI-100-OHM
1
PP3V42_G3H_SMC_CLK_F
2
SM
VOLTAGE=3.425V
1
C3750
C3751
4.7uF
0.1uF
20%
2 6.3V
CERM
603
20%
10V
CERM 2
402
12 CRITICAL
VDD
U3750
32.768KHZ-9-3.6V
NC
NC
NC
NC
SG-3040LC-SM
OUT
VIO
2
3
NC0
NC4
NC1
NC2
NC5
NC6
NC3
NC7
7
8
9
10
11
R3750
SMC_CLK32K_SUSCLK_R
22
5%
1/16W
MF-LF
402
NC
NC
NC
NC
SMC_CLK32K_SUSCLK
SMC_SUS_CLK
47
MAKE_BASE=TRUE
GND
6
Mobile Clocking
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
37
OF
D
104
IDE (ODD) Connector

63
=PP3V3_S0_IDE
63
=PP5V_S0_IDE
CRITICAL
Q3820
B3
FDZ293P
BGA
D
B1
B2
VOLTAGE=5V
NO STUFF
R38011
A2
PP5V_S0_IDE_ODD
C2
C1
A3
C3
4.7K
R38201
5%
1/16W
MF-LF
402 2
A1
10K
5%
1/16W
MF-LF
402 2
ODD_PWR_EN_L_RC
10K
5%
1/16W
MF-LF
402 2
IN
22
23
IN
21
IO
21
ODD_PWR_EN_L
IO
21
IO
21
(UATA_CS0*)
IO
21
IO
21
IO
21
IO
21
(UATA_HSTROBE)
(UATA_DSTROBE)
IO
21
21
21
OUT
IN
OUT
21
IN
21
IN
33K
CRITICAL
5%
1/16W
MF-LF
402 2
20%
6.3V
X5R
402
R38211
R3810
4.7K
0.22uF
1
R38021
C3821
5%
1/16W
MF-LF
2 402
J3800
M-ST-SM1-LF
1
50
2
49
3
48
47
4
46
5
6
45
7
44
43
8
42
9
10
41
11
40
12
39
13
38
14
37
15
36
16
35
17
34
18
33
19
32
20
31
21
30
22
29
23
28
24
27
25
26
IDE_RESET_L
IDE_PDD<7>
IDE_PDD<6>
IDE_PDD<5>
IDE_PDD<4>
IDE_PDD<3>
IDE_PDD<2>
IDE_PDD<1>
IDE_PDD<0>
IDE_PDDREQ
IDE_PDIOR_L
IDE_PDIORDY
IDE_PDA<2>
IDE_PDCS1_L
NC
R38111
15K
5%
1/16W
MF-LF
402 2
21
21
21
21
21
21
21
21
21
21
21
21
21
21
47
IDE_PDD<8>
IDE_PDD<9>
IDE_PDD<10>
IDE_PDD<11>
IDE_PDD<12>
IDE_PDD<13>
IDE_PDD<14>
IDE_PDD<15>
IDE_PDIOW_L
IDE_PDDACK_L
IDE_IRQ14
IDE_PDA<1>
IDE_PDA<0>
IDE_PDCS3_L
IO
IO
IO
IO
IO
IO
IO
IO
IN
(UATA_STOP)
IN
OUT
IN
IN
IN
(UATA_CS1*)
Indicates disk presence

SMC_ODD_DETECT OUT
R3803
6.2K
5%
1/16W
MF-LF
2 402
516S0335
Counters 10K pull-up to 5V in

ODD to keep SB GPIO <= 3.3V
23
SATA_C_DET_L
1
R3850
100
5%
1/16W
MF-LF
2 402
21
SATA_A_R2D_C_P
TP_SATA_A_R2DP
21
SATA_A_R2D_C_N
TP_SATA_A_R2DN
21
SATA_A_D2R_P
TP_SATA_A_D2RP
21
SATA_A_D2R_N
TP_SATA_A_D2RN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PATA Connector
MAKE_BASE=TRUE
SYNC_DATE=(MASTER)

21
21
SATA_RBIAS_P
SATA_RBIAS_N
SATA_RBIAS
MAKE_BASE=TRUE

R3860
Placement note
Place within 12.7mm
from ball of SB
24.9
1%
1/16W
MF-LF
2 402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
38
OF
D
104
PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6.

SCHEME MATCHES DOC MVL100258-01 MIN_LINE_WIDTH=0.4MM
VOLTAGE=2.5V
38 PP2V5_S3_ENET_AVDD
L4100
FERR-120-OHM-1.5A
1
=PP2V5_S3_ENET
63
0402
1
C4100
1UF
C4101
0.1UF
0.1UF
2 16V
X5R
2 16V
X5R
C4103
0.1UF
2 16V
X5R
402
402
10%
10%
10%
10%
2 6.3V
CERM
402
C4102
C4104
0.1UF
10%
2 16V
X5R
402
C4105
402
0.001UF
10%
C4106
0.001UF
0.1UF
10%
16V
402
10%
2 50V
CERM
2 50V
CERM
402
C4107
2 X5R
402
PLACE C4107 NEAR U4101 AVDD
63 37
=PP3V3_S3_ENET
=PP1V2_S3_ENET
37
63
=PP3V3_S3_ENET
37
63
C4110 10%
16V
12
=ENET_VMAIN_AVLBL47
NC 11
NC 9
NC 24
NC 25
U4101
SWITCH_VAUX
88E8053
4.87K2
R4102
OUT
ENET_CTRL254
ENET_CTRL123
ENET_RSET 16
NO PULL-UP NEEDED
OUT
NC
NC
NC
NC
59
60
62
63
29
46
HSDACP
HSDACN
64
VDD25
AVDDL0
AVDDL4 32
AVDDL3 28
AVDDL2 22
AVDDL1 19
AVDD
57
AVDDL6 52
AVDDL5 51
23
VDDO_TTL1
VDDO_TTL0
61
VDDO_TTL4 45
VDDO_TTL3 40
VDDO_TTL2
8
7
2
VDD0
CRITICAL
VMAIN_AVLBL
SWITCH_VCC
22
1
10%
16V
X5R
PCIE_A_D2R_P
PCIE_A_D2R_N
C4111
OUT
OUT
X5R
C4112 10%
0.1UF
0.1UF
16V
1
2
PCIE_A_R2D_P
PCIE_A_R2D_C_P
IN
PCIE_A_R2D_N 1 2
PCIE_A_R2D_C_N
IN
PLACE
C4113
AND
C4112
WITHIN
ENET_CLK100M_PCIE_P
IN
C4113 12 MIL OF U2100 E27 AND E28
ENET_CLK100M_PCIE_N
0.1UF
IN
402
X5R
PCIE_WAKE_L
OUT
16V
10%
ENET_RST_L
IN
22
22
34
34
WAKE* 6
PERST* 5
CTRL25
22
402
REFCLKP 55
REFCLKN 56
PCI EXPRESS
402
RX_P 54
RX_N 53
ANALOG
X5R
402
1
PCIE_A_D2R_C_P
PCIE_A_D2R_C_N
TX_P 49
TX_N 50
OMIT
VAUX_AVLBL
QFN
1%
1/16W
MF-LF
402
OPTIONAL EXTERNAL LDO
VDD2
VDD1
58
VDD7 48
VDD6 44
ENET_LOM_DIS_L
10 LOM_DISABLE*
62
VDD5 39
VDD4 33
VDD3 13
0.1UF
5%
1/16W
MF-LF
402
4.7K 2
R4101
PLACE C4110 AND C4111 WITHIN

12 MIL OF U4101 PIN 49 AND 50
45 23 5
26
CTRL12
MDIP0 17
MDIN0 18
RSET
38
MDIP1 20
MDIN1 21
LED_ACT*
LED_LINK10/100*
38
38
MEDIA
LED
LED_LINK1000*
LINK*
TSTPT
38
TEST
TESTMODE
MDIP2 26
MDIN2 27
38
MDIP3 30
MDIN3 31
38
TWSI
VPD_CLK 38
VPD_DATA 41
TEST
PU_VDDO_TTL0 42
PU_VDDO_TTL1 43
SPI_DI 35
SPI_DO 34
SPI
SPI_CLK 37
SPI_CS 36
XTALI 15
XTALO 14
MAIN CLK
38
38
ENET_VPD_CLK
ENET_VPD_DATA
ENET_PU_VDD_TTL0
ENET_PU_VDD_TTL1
ENET_MDI_P<0>
IO
ENET_MDI_N<0>
IO
ENET_MDI_P<1>
IO
ENET_MDI_N<1>
IO
ENET_MDI_P<2>
IO
ENET_MDI_N<2>
IO
ENET_MDI_P<3>
IO
ENET_MDI_N<3>
IO
37
37
37
37
ASF IS UNAVAILABLE ON 8053
NC
NC
INTERNAL PULL-UP
NC
NC
R4106
49.9
CRITICAL
ENET_XTALI
3
1
ENET_XTALO
1. KEEP ENET_XTALI AND ENET_XTALO

TRACE LENGTH <12MIL
1%
1/16W
MF-LF
2 402
R4105
1%
1/16W
MF-LF
2 402
R4104
49.9
R4103
49.9
49.9
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
R4120
49.9
1%
1/16W
MF-LF
2 402
R4119
R4118
49.9
49.9
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
R4117
49.9
1%
1/16W
MF-LF
2 402
65
THRML_PAD
4
2. DO NOT ROUTE UNDER CRYSTAL
Y4101
ENET_MDI0
ENET_MDI1
ENET_MDI2
ENET_MDI3
SM-3.2X2.5MM
25.0000M
1
C4150
27pF
5%
2 50V
CERM
402
C4151
27pF
C4116
0.001UF
5%
2 50V
CERM
402
C4115
0.001UF
10%
2 50V
CERM
402
C4117
0.001UF
10%
2 50V
CERM
402
C4118
0.001UF
10%
2 50V
CERM
402
10%
2 50V
CERM
402
B
PLACE RESISTORS CLOSE TO U4101
=PP3V3_S3_ENET
37 63
63 37
37
0.1UF
10%
402
OMIT
CRITICAL
8
3
2
1
PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101

SCHEME MATCHES DOC MVL100258-01
63 37
PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101

SCHEME MATCHES DOC MVL100258-01
=PP1V2_S3_ENET
63 37
VCC
E2
NC1 U4102 SDA
NC0
M24C08SCL
WC* SO8
=PP3V3_S3_ENET
5
6
5%
1/16W
MF-LF
402
C4140
2 16V
X5R
4.7K 2
ENET_PU_VDD_TTL0
ENET_PU_VDD_TTL1
5%
1/16W
MF-LF
2 402
R4123
37
PLACE C4140 NEAR U4102 VCC
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
R4131
4.7K2
4.7K
=PP3V3_S3_ENET
R4130
R4122
ENET_VPD_DATA
ENET_VPD_CLK
37
37
VSS
4
C4126
0.1UF
10%
2 16V
X5R
402
C4127
0.1UF
10%
16V
2 X5R
402
C4128
0.1UF
10%
16V
2 X5R
402
C4129
0.1UF
10%
16V
2 X5R
402
C4130
0.1UF
10%
16V
2 X5R
402
C4131
0.001UF
10%
2 50V
CERM
402
C4132
0.001UF
10%
2 50V
CERM
C4133
0.001UF
10%
2 50V
CERM
402
402
C4134
0.001UF
C4135
0.1UF
10%
10%
50V
2 CERM
2 16V
X5R
402
402
C4136
0.1UF
10%
2 16V
X5R
402
C4137
0.1UF
10%
16V
2 X5R
402
C4138
0.001UF
10%
2 50V
CERM
402
C4139
ETHERNET CONTROLLER
0.001UF
10%
50V
402
2 CERM
SYNC_MASTER=M42

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
41
OF
D
104
8
ELECTRICAL_CONSTRAINT_SET
PROVIDED
BY
ETHERNET
PHY
NET_TYPE
SPACING
PHYSICAL
ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENET_100D
ENET_100D
ENET_100D
ENET_100D
ENET_100D
ENET_100D
ENET_100D
ENET_100D
ENETCONN_P<0>
ENETCONN_N<0>
ENETCONN_P<1>
ENETCONN_N<1>
ENETCONN_P<2>
ENETCONN_N<2>
ENETCONN_P<3>
ENETCONN_N<3>
38
38
38
38
38
38
38
38
Page Notes
- =PP2V5_ENET
- =GND_CHASSIS_ENET
(NONE)
(NONE)
37
IN
PP2V5_S3_ENET_AVDD
Place one cap at each pin of transformer

1
C4200
1uF
C4201
1uF
10%
2 6.3V
CERM
402
C4202
1uF
10%
2 6.3V
CERM
402
C4203
1uF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
1000BT-824-00275
CRITICAL
37
IO
ENET_MDI_P<0>
T4200
XFR-SM
16
38
14
ENETCONN_P<0>
ENET_CTAP0
37
IO
ENET_MDI_N<0>
ENET_MDI_P<1>
2
4
5
7
NC1
NC2
LINE
SIDE
37
IO
CHIP
SIDE
CRITICAL
NC4
NC3
15
13
12
10
11
38
J4200
ENETCONN_N<0>
JM36113-P2054-7F
F-RT-TH-RJ45
11
38
ENETCONN_P<1>
ENET_CTAP1
1
2
37
IO
ENET_MDI_N<1>
Transformers should be
mirrored on opposite
sides of the board
ENETCONN_N<1>
3
4
SYM_VER2
37
37
IO
IO
IO
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>
T4201
XFR-SM
16
14
2
4
5
7
15
13
12
10
NC1
NC2
LINE
SIDE
37
IO
1000BT-824-00275
CRITICAL
CHIP
SIDE
37
38
NC4
NC3
11
38
ENETCONN_P<2>
ENET_CTAP2
10
38
ENETCONN_N<2>
38
ENETCONN_P<3>
12
514-0277
Short shielded RJ-45
NO STUFF
ENET_CTAP3
38
R4210
ENETCONN_N<3>
5%
1/16W
MF-LF
402
SYM_VER2
R42001 R42011
75
5%
1/16W
MF-LF
402 2
75
5%
1/16W
MF-LF
402 2
R4202
75
5%
1/16W
MF-LF
2 402
Place close to connector
R4203
75
5%
1/16W
MF-LF
2 402
C4204
100pF
ENET_CTAP_COMMON
10%
3KV
CERM
1808
=GND_CHASSIS_ENET
OUT
Ethernet Connector
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
42
OF
D
104
Yukon Power Control

Allows powering Yukon down during battery sleep to save power
Q4300
FDG6332C_NL
SC70-6
P-CHN
=PP3V3_S3_P3V3S3AC
63
=PP3V3_S3AC_FET
D
63
G
5
PPVIN_S3_P2V5S3_SVIN
1
R4305
100K
100K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
PM_SLP_S3BATT_L
P2V5S3_EN_L
=P2V5S3_EN_L
MAKE_BASE=TRUE
3
Q4304
2N7002DW-X-F
63
2N7002DW-X-F
SOT-363
59
Q4304
59
R4304
SOT-363
S
1
=PPBUS_G3H_S3AC
P1V2S3_RUNSS 5 59
1.2V enable has pull-up to 3.3V
R4302
470K
5%
1/16W
MF-LF
2 402
Q4302
2N7002
PM_SLP_S3BATT
SOT23-LF
S
2
6
D
PM_SLP_S4_L
ENETPWR_S3AC
N-CHN
62 47 23
2 G
FWPWR_EN_L
FDG6332C_NL
SC70-6
R4300
41
Q4300
FWPWR_EN_L_OR_GND
ENETPWR_S3
5%
1/16W
MF-LF
402
R4301
0
5%
1/16W
MF-LF
2 402
When ENETPWR_S3AC BOMOPTION is active:

State
FWPWR_EN_L
S0 AC
0V
3.3V
0V
(3.3V ON)
3.3V
0V
(2.5V ON)
3.3V (1.2V ON)
S0 Batt
0V
3.3V
0V
(3.3V ON)
3.3V
0V
(2.5V ON)
3.3V (1.2V ON)
S3 AC
0V
3.3V
0V
(3.3V ON)
3.3V
0V
(2.5V ON)
3.3V (1.2V ON)
PBUS
3.3V
PBUS (3.3V OFF)
0V
3.3V (2.5V OFF)
0V
(1.2V OFF)
0V
0V
PBUS (3.3V OFF)
0V
Hi-Z (2.5V OFF)
0V
(1.2V OFF)
S5 Batt
PBUS
0V
PBUS (3.3V OFF)
0V
Hi-Z (2.5V OFF)
0V
(1.2V OFF)
G3H Batt
PBUS
0V
PBUS (3.3V OFF)
0V
Hi-Z (2.5V OFF)
0V
(1.2V OFF)
S3 Batt
S5 AC
PM_SLP_S4_L
PM_SLP_S3BATT
PM_SLP_S3BATT_L
P2V5S3_EN_L
P1V2S3_RUNSS
When ENETPWR_S3 BOMOPTION is active:

State
PM_SLP_S4_L
PM_SLP_S3BATT
PM_SLP_S3BATT_L
P2V5S3_EN_L
P1V2S3_RUNSS
S0
3.3V
0V
(3.3V ON)
3.3V
0V
(2.5V ON)
3.3V (1.2V ON)
S3
3.3V
0V
(3.3V ON)
3.3V
0V
(2.5V ON)
3.3V (1.2V ON)
S5
G3H
0V
0V
PBUS (3.3V OFF)

PBUS (3.3V OFF)
0V
0V
Hi-Z (2.5V OFF)

Hi-Z (2.5V OFF)
0V
0V
Yukon Power Control

(1.2V OFF)
SYNC_DATE=(MASTER)
(1.2V OFF)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
43
OF
D
104
PAGE NOTES
0.001A DURING SLEEP

63 =PP3V3_S3_FW
INPUT
=PP3V3_S0_FW - 3.3V POWER FOR FIREWIRE (MOBILE: OFF DURING SLEEP)
=PP3V3_S0_PCI - 3.3V POWER FOR PCI FIREWIRE (MOBILE: OFF DURING SLEEP)
PCI_GNT3_L - PCI GRANT FROM SB
PCI_CLK_FW - NEED TO REFERENCE TO ALIAS PAGE
PCI_RST_L - PCI RESET FROM SB
FW_PC0 - FIREWIRE POWER CLASS IDENTIFIER
PLACE ONE CAP PER TWO PINS STARTING WITH C4424 ON VDD0
1
C4424
10UF
C4418
0.1UF
20%
2 10V
CERM
402
20%
2 6.3V
X5R
603
C4422
C4426
0.1UF
C4428
0.1UF
20%
2 10V
CERM
402
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C4430
0.1UF
20%
2 10V
CERM
402
C4432
0.1UF
20%
2 10V
CERM
402
INPUT/OUTPUT
PCI_AD<0..31>,PCI_C_BE_L<0..3>,PCI_FRAME_L,PCI_IRDY_L,PCI_TRDY_L,
PCI_DEVSEL_L, PCI_STOP_L, PCI_PAR, PCI_PERR_L, PCI_SERR_L
FW_A_TPA_P/N, FW_A_TPB_P/N, FW_A_TPBIAS - PORT 0 FIREWIRE DIFF PAIRS
FW_B_TPA_P/N, FW_B_TPB_P/N, FW_B_TPBIAS - PORT 1 FIREWIRE DIFF PAIRS
FW_C_TPA_P/N, FW_C_TPB_P/N, FW_C_TPBIAS - PORT 2 FIREWIRE DIFF PAIRS
L4400
600-OHM-300MA
1
PLACE ONE CAP PER TWO PINS STARTING WITH C4416

ON VDDA0
PP3V3_S3_FW_AVDD
VOLTAGE=3.3V
0402
OUTPUT
C4416
C4417
10UF
PCI_REQ3_L - PCI REQUEST TO SB

PM_CLKRUN_L - CLOCK-RUN PCI PROTOCOL
INT_PIRQD_L - INTERRUPT TO SB
PCI_PME_FW_L - DEDICATED PME FOR FIREWIRE (SB GPIO1)
0.1UF
20%
2 6.3V
X5R
603
C4429
0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
0.1UF
10%
2 16V
X5R
402
GND_FW_VSSA
40
=PP3V3_S3_PCI
197S0178 3.2MMX2.5MM
CRITICAL
D10
A13
B13
A7
A8
D6
A2
G4
N1
N2
K5
K6
K7
L13
H13
63
Y4403
VDDA5
VDDA4
VDDA3
VDDA2
VDDA1
VDDA0
VDD7
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD9
FIRST REVISION OF PAGE

BGA VERSION OF FW323-06 ADDED
CHANGED INT* TO INT_PIRQD_L (PER ARCHITECTURAL DEFINITION)
CHANGED PCI_ID TO AD19 (PER ARCHITECTURAL DEFINITION)
CHANGED REQ/GNT TO REQ3/GNT3 (PER ARCHITECTURAL DEFINITION)
ADDED 510K PULL-DOWN ON RST* AND REMOVED CONNECTION TO PLT_RST_L
CHANGED CLK,PME,DIFF PAIR NAMES TO BE RE-USE COMPLIANT
REMOVED CONSTRAINT SETS AS THEY WILL BE MANAGED ON BOARD SIDE
REMOVED C4421 - REDUNDANT
BRING OUT PC0 CONNECTION TO BE CONNECTED ON PORT PAGE
CONNECTED PIN E10 TO GND
VDD0
C4425MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
PAGE HISTORY
5/19/2005
6/20/2005
6/21/2005
6/21/2005
6/21/2005
6/22/2005
6/22/2005
6/22/2005
6/22/2005
6/22/2005
7/26/2005
G13 PCI_VIOS
CONNECT TO VDD FOR 3.3V OPERATION
22
IO
PCI_C_BE_L<0>
PCI_C_BE_L<1>
PCI_C_BE_L<2>
PCI_C_BE_L<3>
K12
M9
L3
L1
PCI_CBE0*
PCI_CBE1*
N10
N6
M6
N7
N8
M7
L2
PCI_PAR
PCI_FRAME*
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
PCI_AD<19>
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
IO
22
22
IO
22
IO
22
IO
22
IO
IO
R4431
IO
22
IO
5%
1/16W
MF-LF
402 2
IO
IO
IO
22
26
22
26
22
26
22
26
22
26
22
OUT 26 22
IN
IO
IO
IN
R4432
PCI_RST_L
THIS IS FROM ICH-7M
IN
PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>
22
IO
22
100
5%
1/16W
MF-LF
402
22
26
22
26
22
34
IO
2
OUT
26 22
OUT
22
PCI_PAR
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_DEVSEL_L
PCI_STOP_L
FW_PCI_IDSEL
390
5%
1/16W
MF-LF
402
F10
G10
H10
H12
J13
J12
K13
K10
L12
M13
L11
M12
M11
N12
M10
N11
M4
N5
N4
M3
M2
N3
K4
M1
K2
J4
K1
J2
J1
H2
H4
H1
IO
SM-3.2X2.5MM
R4400
PCI_AD0
24.576MHZ
FW_XO_R
3
2 4
C4411 1
22pF
PCI_AD1
PCI_AD2
CRITICAL
PCI_AD3
U4400
PCI_AD4
PCI_AD5
FW32306
XI
A5
FW_XI
XO
B5
FW_XO
22pF
NEED TO CHECK CRYSTAL LOAD CAPACITANCE
BGA
PCI_AD6
C4412
5%
2 50V
CERM
402
5%
50V
CERM 2
402
OMIT
PCI_AD7
PCI_AD8
RESET*
B4
FW_PWRON_RST_L
R1
A6
FW_R1
PCI_AD9
PCI_AD10
SPEC RECOMMENDS 2.49K
PCI_AD11
PCI_AD12
PCI_AD13
R0
PCI_AD14
TPBIAS0
PCI_AD15
PCI_AD16
TPA0_P
PCI_AD17
TPA0_N
TPB0_P
PCI_AD18
PCI_AD19
TPB0_N
TPBIAS1
PCI_AD20
PCI_AD21
TPA1_P
PCI_AD22
TPA1_N
TPB1_P
PCI_AD23
PCI_AD24
TPB1_N
PCI_AD25
TPBIAS2
TPA2_P
PCI_AD26
PCI_AD27
TPA2_N
PCI_AD28
TPB2_P
TPB2_N
FW_R0
B7
B8
A9
B9
B10
A10
D8
A11
B11
B12
A12
C13
C11
C12
D13
D12
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
R4452
2.49K
1%
1/16W
MF-LF
2 402
FW_A_TPBIAS
FW_A_TPA_P
FW_A_TPA_N
FW_A_TPB_P
FW_A_TPB_N
FW_B_TPBIAS
FW_B_TPA_P
FW_B_TPA_N
FW_B_TPB_P
FW_B_TPB_N
FW_C_TPBIAS
FW_C_TPA_P
FW_C_TPA_N
FW_C_TPB_P
FW_C_TPB_N
C4420
0.1UF
10%
2 16V
X5R
402
R4420
510K
5%
1/16W
MF-LF
2 402
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE2*
PCI_CBE3*
MODE_420
MODE_A
M5
B6
MODE FOR EXTERNAL LINK
PCI_IRDY*
PC0
PC1
PCI_TRDY*
PCI_DEVSEL*
PC2
CONTENDER
PCI_STOP*
PCI_IDSEL
CARDBUSN
MPCI_ACTN_323
PCI_REQ3_L
PCI_GNT3_L
PCI_PERR_L
PCI_SERR_L
E2
E1
M8
N9
PCI_CLK_FW
PM_CLKRUN_L
G2 PCI_CLK
D1 CLKRUN*
FW_PCI_RST_L
INT_PIRQD_L
PCI_PME_FW_L
F1 PCI_RST*
D2 PCI_INTA*
F2 PCI_PME*
PCI_REQ*
E12
F13
F12
G12
B1
E10
42
FW_PC0
IO
DUAL PORT DEVICES ARE POWER CLASS 4 (100)

SINGLE PORT DEVICES ARE POWER CLASS 0 (000)
LOW = NOT BUS MANAGER

LOW = PCI OPERATION
PCI_GNT*
PCI_PERR*
PCI_SERR*
TEST0
TEST1
MANUFACTURING TEST PINS

PTEST
SE
SM
C2
C1
A4
A3
B3
FIREWIRE CONTROLLER
SYNC_MASTER=(M42)
VSSA3
VSSA4
VSSA2
VSSA0
VSSA1
VSS22

E13
E9
D9
D7
D5
VSS20
VSS21
VSS18
VSS19
VSS17
VSS15
VSS16
VSS14
VSS11
VSS12
VSS13
VSS9
VSS10
VSS8
VSS6
VSS7
VSS5
VSS3
VSS4
VSS2
A1
B2
C3
D4
E4
E5
F4
F6
F7
F8
G1
G6
G7
G8
H6
H7
H8
J5
J9
J10
K8
K9
N13
VSS0
VSS1

XW4400
SM
1
SIZE
GND_FW_VSSA
APPLE COMPUTER INC.
40
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
44
OF
D
104
Page Notes
- =PPBUS_S0_FWPWRSW (system supply for bus power)
- =PP3V3_S0_FWPORTPWRSW
- =FWPWR_PWRON (see related text note below)
(NONE)
Port Power Switch

FireWire Port Current Sense
CRITICAL
Q4565
CRITICAL
63
F4565
=PPBUS_S5_FWPWRSW
MINISMDC
R4565
PPBUS_S5_FWPWRSW_F
VOLTAGE=12.6V
C4565 1
470K
8
7
6
5
3
2
1
PPBUS_S5_FW_FET_D_R
20%
16V
CERM 2
402
D4565
SMB
PPBUS_S5_FW_FET_D
VOLTAGE=12.6V
=PPBUS_S5_FW_FET
63
B340XF
VIN+ VIN-
1
63
R4566
INA194
5
5%
1/16W
MF-LF
2 402
C4595 1
1uF
10%
6.3V 2
CERM
402
FWPWR_EN_L
U4595
=PP3V3_S0_FWISENS
330K
Enables port power when machine

is running or on AC.
0.02 2
0.5%
1W
MF
0612
FWPWR_EN_L_DIV
39
VOLTAGE=12.6V
0.01uF
5%
1/16W
MF-LF
2 402
R4570
SOI-LF
1.1A-24V
1
CRITICAL
NDS9407
V+
SOT23-5
OUT
50V/V
51
FWPWR_IOUT
1A = 1V
OUT
GND
2 CRITICAL
Q4560
2N7002DW-X-F
48 47 45 5
SMC_ADAPTER_EN
SOT-363
Q4560
D
4
62 47 23
2N7002DW-X-F
PM_SLP_S3_L
SOT-363
S
1
FireWire Port Power

SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
45
OF
D
104
8
PROVIDED
BY
PHY
PAGE
7
FW
FW
FW
FW
42
42
42
L4620
42
63
Page Notes
D
FERR-250-OHM
=PPFW_PORT1
PPFW_PORT1_VP
VOLTAGE=33V
SM
1

- =PPFW_PORT1
- =PP3V3_S5_FWLATEVG
- =GND_CHASSIS_FW_PORT1
C4624
0.001uF
42
PP3V3_S5_FWLATEVG_R_F
Place close to FireWire PHY

40
FW_A_TPBIAS
DP4620
DP4620
BAV99DW-X-F
1
C4650
C4620 1
0.33uF
0.001uF
SOT-363
2
20%
50V
CERM 2
402
10%
2 6.3V
CERM-X5R
402

(NONE)
BAV99DW-X-F
C4621 1
0.001uF
6
NOTE: FireWire TPA/TPB pairs are NOT

constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.
R4650
56.2
R46511
FW_PORT1_TPA_P
FW_A_TPA_N
FW_PORT1_TPA_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
40
FW_A_TPB_P
40
FW_A_TPB_N
FW_PORT1_TPB_P
MAKE_BASE=TRUE
FW_PORT1_TPB_N
MAKE_BASE=TRUE
2nd TPA/TPB pair unused
FW_B_TPB_P
NC_FW_B_TPBP
40
FW_B_TPB_N
42
FW_PORT1_TPB_P
42
FW_PORT1_TPB_N
42
42
1394A
F-RT-TH-LF
SYM_VER-2
BAV99DW-X-F
SOT-363
2
C4622 1
1%
1/16W
MF-LF
402 2
0.001uF
20%
50V
CERM 2
402
SOT-363
5
42
FW_PORT1_TPA_FL_P
42
FW_PORT1_TPA_FL_N
42
FW_PORT1_TPB_FL_P
42
FW_PORT1_TPB_FL_N
20%
50V
CERM 2
402
FL4621
TPO# (TPA-)
TPI (TPB+)
TPI# (TPB-)
(PPFW_PORT1_VP)
VP
CRITICAL
VGND
7
C4625
0.01uF
20%
2 50V
CERM
603
(TPA+)
TPO
(GND_FW_PORT1_VG)
3
C4623 1
0.001uF
260-OHM-330MA
DP4621
BAV99DW-X-F
42
2
SM1
DP4621
56.2
10
C4626 1
0.01uF
20%
16V
CERM 2
402
514-0255
=GND_CHASSIS_FW_PORT1
1
C4654 R4654
4.99K
1%
1/16W
MF-LF
402 2
5%
2 25V
CERM
402
40
CRITICAL
2
SM1
R46531
220pF
NC_FW_B_TPAN
42
FW_TPA0_C
FW_B_TPA_N
FW_PORT1_TPA_N
FL4620
FW_A_TPA_P
1%
1/16W
MF-LF
2 402
40
PORT 1
1394A
CRITICAL
40
56.2
NC_FW_B_TPAP
42
SYM_VER-2
260-OHM-330MA
40
R4652
NC_FW_B_TPBIAS
1%
1/16W
MF-LF
402 2
FW_B_TPA_P
42
FW_PORT1_TPA_P
56.2
1%
1/16W
MF-LF
2 402
FW_B_TPBIAS
3
4
J4620
1
1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)
40
SOT-363
5
20%
50V
CERM 2
402
40
20%
2 50V
CERM
402
"Snapback" & "Late VG" Protection
Termination

(NONE)
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
3rd TPA/TPB pair unused

40
FW_C_TPBIAS
NC_FW_C_TPBIAS
40
FW_C_TPA_P
NC_FW_C_TPAP
40
FW_C_TPA_N
NC_FW_C_TPAN
40
FW_C_TPB_P
NC_FW_C_TPBP
40
FW_C_TPB_N
NC_FW_C_TPBN
MAKE_BASE=TRUE
NO_TEST=YES
MAKE_BASE=TRUE
NO_TEST=YES
Cable Power
FW_PORT1_TPA_FL_P
FW_PORT1_TPA_FL_N
FW_PORT1_TPB_FL_P
FW_PORT1_TPB_FL_N
FW_110D
FW_110D
FW_110D
FW_110D
NET_TYPE
SPACING
PHYSICAL
MAKE_BASE=TRUE
NO_TEST=YES
MAKE_BASE=TRUE
NO_TEST=YES
MAKE_BASE=TRUE
NO_TEST=YES
NC_FW_B_TPBN
MAKE_BASE=TRUE
NO_TEST=YES
MAKE_BASE=TRUE
NO_TEST=YES
MAKE_BASE=TRUE
NO_TEST=YES
MAKE_BASE=TRUE
NO_TEST=YES
R4699
MAKE_BASE=TRUE
NO_TEST=YES
=GND_CHASSIS_FW_EMI
5%
1/16W
MF-LF
402
FW Power Class Strap

Single-port system sets PC=0
FW_PC0
40
Late-VG Protection Power

A
63
=PP3V3_S5_FWLATEVG
330
5%
1/16W
MF-LF
402
FireWire Ports
L4690
R4690
400-OHM-EMI
PP3V3_S5_FWLATEVG_R
VOLTAGE=3.3V
PP3V3_S5_FWLATEVG_R_F
VOLTAGE=3.3V
2
SM-1
3
C4691 1
0.1uF
20%
10V
CERM 2
402
C4692 1
CRITICAL

MMBZ5227B
1
SOT23

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
SYNC_DATE=(MASTER)
42
D4690
0.001uF
10%
50V
CERM 2
402
46
OF
D
104
Top-Case Connector
63
63
63
=PP3V3_S3_TOPCASE
=PP3V42_G3H_LIDSWITCH
=PP5V_S3_TOPCASE
CRITICAL
J4900
QT500166-L020
48 47
OUT
SMC_LID
OUT
SMC_ONOFF_L
IO
IO
M-ST-SM
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
=USB_TRACKPAD_P
=USB_TRACKPAD_N
CRITICAL
KBDLED_RETURN
KBDLED_ANODE
53
53
27
27
27
27
=SMBUS_TOPCASE_SDA
=SMBUS_TOPCASE_SCL
=I2C_TRACKPAD_SCL
=I2C_TRACKPAD_SDA
D4900
SC-75
OUT
IN
IO
IO
IO
IO
1
3
2
516S0350
RCLAMP0502B
Camera Connector
NO STUFF
L4930
C4931 1
FERR-220-OHM
0.001uF
20%
50V
CERM 2
402
PP5V_S3_CAMERA_F
VOLTAGE=5V
PLACEMENT_NOTE=Place next to J4931 pin 7
CRITICAL
FL4935
165-OHM
J4931
CAMERA-M1-CUS
5 63
0402
CRITICAL
Connector
=PP5V_S3_CAMERA
SM
SYM_VER-2
46
=USB2_CAMERA_N
IO
36
=USB2_CAMERA_P
IO
=SMBUS_ATS_SDA
IO
=SMBUS_ATS_SCL
IO
F-RT-SM
7
shield
2
1
2
3
4
5
6
Twin-Ax Pair 1
(40 AWG)
Twin-Ax Pair 2
(40 AWG)
Standard wires
(28 AWG)
Connector shield
USB2_CAMERA_N_F
USB2_CAMERA_P_F
SMBUS_ATS_SDA_F
SMBUS_ATS_SCL_F
CRITICAL
FL4936
165-OHM
1
SM
SYM_VER-2
NO STUFF
D4930
RCLAMP0502B
SC-75
518S0371
CRITICAL
GND_CAMERA
NO STUFF
C4930 1
VOLTAGE=0V
L4931
FERR-220-OHM
1
2
0402
0.001uF
20%
50V
CERM 2
402
PLACEMENT_NOTE=Place next to J4931 pin 8
Internal USB Connections

SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
49
OF
D
104
Port Power Switch
Right USB Port
CRITICAL
U5290
63
=RTUSB_EN
IN_0
OUT_0
IN_1
OUT_1 7
EN*
GND
1
C5290 1
10uF
20%
6.3V 2
CERM
805-1
C5291
0.1UF
20%
2 10V
CERM
402
OC*
THRML
FERR-250-OHM
PP5V_S3_RTUSB_ILIM
MSOP
2
OUT_2
62
L5205
TPS2051
=PP5V_S3_RTUSB
VOLTAGE=5V
C5295 1
10uF
20%
6.3V 2
CERM
805-1
C5296
=RTUSB_OC_L
NO STUFF
1
OUT
IO
=USB2_RT_N
SM
SYM_VER-2
IO
=USB2_RT_P
CRITICAL
J5200
UAR2X
F-RT-SM-USB-RGT1
5
6
1 VBUS
C5292
20%
2 6.3V
CERM-X5R
402
20%
2 6.3V
POLY
B2
20%
16V
CERM 2
402
CRITICAL
0.47uF
100UF
L5200
165-OHM
5%
1/16W
MF-LF
402
PAD
C5205
0.01uF
R5292
RTUSB_OC_L_RC
PP5V_S3_RTUSB_F
VOLTAGE=5V
SM
USB2_RT_F_N
USB2_RT_F_P
RTUSB_ESD
D5200
C5206
RCLAMP0502B
CRITICAL
D+
GND
20%
16V
CERM 2
402
D-
0.01uF
SC-75
514S0115
L5206
FERR-250-OHM
1
2
SM
=GND_CHASSIS_RTUSB
GND_RTUSB
VOLTAGE=0V
Place L5200, L5205 and L5206 across moat
External USB Connector

SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
52
OF
D
104
Place XW5500 at 5V switcher
(2 Amps)
PP5V_S0_AUDIO_PWR
XW5500
SM
1
=PP5V_S0_AUDIO_XW
63
VOLTAGE=5V
63 5
63 5
(Input from LIO)
63 5
63 5
=PP1V5_S0_LIO
=PP3V42_G3H_LIO
=PPDCIN_G3H_LIO
=PP5V_S5_LIO
(500 mA)
PP5V_S0_AUDIO
XW5505
SM
1
VOLTAGE=5V
CRITICAL
J5500
QT510806-L111-7F
F-ST-SM
84
NC 81
48 47 5
48 47 41 5
48 47 5
34 5
34 5
26 5
48 6 5
6 5
51 5
47 5
47 5
48 47 5
48 47 5
48 47 5
62 5
EXCARD_CLKREQ_L
MINI_CLKREQ_L
LIO_PLT_RESET_L
EXCARD_OC_L
LTUSB_OC_L
LIO_BATT_ISENSE
SMC_SYS_ISET
SMC_BATT_ISET
SMC_EXCARD_CP
SMC_BC_ACOK
LIO_P3V3S0_EN_L
62 5
LIO_DCIN_ISENSE
LIO_P3V3S3_EN
47 5
SMC_EXCARD_PWR_EN
51 5
79 21 5
79 21 5
79 21 5
SYS_ONEWIRE
SMC_ADAPTER_EN
SMC_BATT_CHG_EN
79 21 5
ACZ_SDATAOUT
ACZ_BITCLK
ACZ_SDATAIN<0>
ACZ_SYNC
NC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
83
NC
PCIE_WAKE_L
=SMBUS_LIO_SMC_SDA
=SMBUS_LIO_SMC_SCL
=USB2_EXCARD_N
=USB2_EXCARD_P
=USB2_LT_N
=USB2_LT_P
=SMBUS_LIO_SB_SCL
=SMBUS_LIO_SB_SDA
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_P
=PCIE_MINI_D2R_N
=PCIE_MINI_D2R_P
=PCIE_MINI_R2D_N
=PCIE_MINI_R2D_P
=PCIE_EXCARD_D2R_N
=PCIE_EXCARD_D2R_P
=PCIE_EXCARD_R2D_N
=PCIE_EXCARD_R2D_P
ACZ_RST_L
5 23 37
5 27
5 27
5 6
5 6
5 6
5 6
5 27
5 27
5 34
5 34
5 46
5 46
5 46
5 46
5 34
5 34
5 46
5 46
5 46
5 46
5 21 79
NC
516S0361
5
(500 mA)
GND_AUDIO
XW5515
SM
1
VOLTAGE=0V
(2 Amps)
GND_AUDIO_PWR
XW5510
SM
1
VOLTAGE=0V

SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
55
OF
D
104
PCI-E x1 Port "A" = Ethernet (Yukon)

PCI-E x1 Port "B" = PCI-E Mini Card
C5710
0.1uF
45 5
45 5
=PCIE_MINI_R2D_P
PCIE_MINI_R2D_C_P
PCIE_B_R2D_C_P
MAKE_BASE=TRUE
=PCIE_MINI_R2D_N
10%
16V
X5R
402
PCIE_MINI_R2D_C_N
C5711
0.1uF
1
PCIE_B_R2D_C_N
MAKE_BASE=TRUE
45 5
=PCIE_MINI_D2R_P
45 5
=PCIE_MINI_D2R_N
10%
16V
X5R
402
PCIE_MINI_D2R_P
22
Place caps close to SB

22
PCIE_B_D2R_P
22
PCIE_B_D2R_N
22
MAKE_BASE=TRUE
PCIE_MINI_D2R_N
MAKE_BASE=TRUE
PCI-E x1 Port "C" = ExpressCard

C5720
0.1uF
45 5
45 5
=PCIE_EXCARD_R2D_P
PCIE_EXCARD_R2D_C_P
PCIE_C_R2D_C_P
MAKE_BASE=TRUE
=PCIE_EXCARD_R2D_N
PCIE_EXCARD_R2D_C_N
10%
16V
X5R
402
C5721
0.1uF
1
22
Place caps close to SB

PCIE_C_R2D_C_N
22
PCIE_C_D2R_P
22
PCIE_C_D2R_N
22
PCIE_D_R2D_C_P
22
PCIE_D_R2D_C_N
22
PCIE_D_D2R_P
22
PCIE_D_D2R_N
22
PCIE_E_R2D_C_P
22
PCIE_E_R2D_C_N
22
PCIE_E_D2R_P
22
PCIE_E_D2R_N
22
PCIE_F_R2D_C_P
22
PCIE_F_R2D_C_N
22
PCIE_F_D2R_P
22
PCIE_F_D2R_N
22
MAKE_BASE=TRUE
45 5
=PCIE_EXCARD_D2R_P
45 5
=PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
10%
16V
X5R
402
MAKE_BASE=TRUE
PCIE_EXCARD_D2R_N
MAKE_BASE=TRUE
PCI-E x1 Port "D" = Unused

TP_PCIE_D_R2DP
MAKE_BASE=TRUE
TP_PCIE_D_R2DN
MAKE_BASE=TRUE
TP_PCIE_D_D2RP
MAKE_BASE=TRUE
TP_PCIE_D_D2RN
MAKE_BASE=TRUE
PCI-E x1 Port "E" = Unused

TP_PCIE_E_R2DP
MAKE_BASE=TRUE
TP_PCIE_E_R2DN
MAKE_BASE=TRUE
TP_PCIE_E_D2RP
MAKE_BASE=TRUE
TP_PCIE_E_D2RN
MAKE_BASE=TRUE
PCI-E x1 Port "F" = Unused

TP_PCIE_F_R2DP
MAKE_BASE=TRUE
TP_PCIE_F_R2DN
MAKE_BASE=TRUE
TP_PCIE_F_D2RP
MAKE_BASE=TRUE
TP_PCIE_F_D2RN
MAKE_BASE=TRUE
PCI-E Connections
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
57
OF
D
104
63 48 47
OMIT
23
OUT
P15
P65/KIN5*
P16
P17
P66/IRQ6*/KIN6*
P67/IRQ7*/KIN7*
48
P20
P70/AN0
48
P21
P71/AN1
48
P22
P23
P72/AN2
P73/AN3
P24
P74/AN4
48
P25
P26
P75/AN5
P76/AN6
48
P27
48
48 45 5
OUT
48 45 5
OUT
56 49 21 5
IO
56 49 21 5
IO
56 49 21 5
IO
56 49 21 5
IO
56 49 21 5
IN
26
IN
34
IN
56 49 23 5
OUT
48
OUT
48
OUT
27
IO
48
OUT
48
OUT
48
OUT
48
OUT
53
OUT
49 48 5
OUT
49 48 5
27
IN
P80/PME*
P81/GA20
P32/LAD2
P82/CLKRUN*
P33/LAD3
P34/LFRAME*
P83/LPCPD*
P84/IRQ3*/TXD1
P35/LRESET*
P85/IRQ4*/RXD1
P36/LCLK
P37/SERIRQ
P86/IRQ5*/SCK1/SCL1
P40/TMIO
P90/IRQ2*
P91/IRQ1*
P41/TMO0
P42/SDA1
P92/IRQ0*
P93/IRQ12*
P43/TMI1/EXSCK1
P94/IRQ13*
P44/TMO1
P45
P95/IRQ14*
P96/EXCL
P46/PWX0/PWM0
P97/IRQ15*/SDA0
C7
A7
B7 56
D6 56
C6
A6
B6
K4
J2
J1
J3
J4
H2
H1
G2
52 22
52 22
48
48
51
51
51
51
51
51
51
51
23
48
49 40 23 5
49 48 23 5
48
48
27
51 48 43 5
48 45 5
64 48 5
62 41 23
62 39 23
48 23
35
27
20%
2 6.3V
CERM
805
20%
2 10V
CERM
402
20%
2 10V
CERM
402
20%
2 10V
CERM
402
20%
2 10V
CERM
402
LAYOUT NOTE:
PLACE C5807 NEAR PIN F1
SMC_VCL
1
C5807
LAYOUT NOTE:
VCL IS INTERNAL RAIL 0.47UF
20%
PLACE R5899 AND C5820 NEAR SMC PIN N14,N15
2 6.3V
CERM-X5R
402
63 48 47
=PP3V3_S5_SMC
PP3V3_AVREF_SMC
R5899
4.7
1
5%
1/16W
MF-LF
402
C5820
0.1UF
20%
2 10V
CERM
402
53 51 48 47
OMIT
48
48
1R5801
R5809
10K
10K
5%
1/16W
MF-LF
2402
BGA
E3
RES*
A2
B2
XTAL
MD2
E2
K1
NMI
F4
ETRST*
L1
MD1
EXTAL
=PP3V3_S5_SMC
1
SMC_H8S2116
(3 OF 4)
SMC_RST_L
SMC_XTAL
SMC_EXTAL
63 48 47
U5800
GND_SMC_AVSS
49 48 5
IN
48
PP3V3_AVCC_SMC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
5%
1/16W
MF-LF
2402
SMC_MD1
5 49
SMC_NMI
IN
KBC_MDE
P47/PWX1/PWM1
P50
P51
AVSS
P52/SCL0
VSS
D1
P4
R4
F12
F13
B13
A13
A4
B4
D2
IO
P77/AN7
P30/LAD0
P31/LAD1
N12
R13
P13
R14
P14
R15
N13
P15
52 22
1 C58031 C58041 C58051 C5806

C5802
22UF
0.1UF
0.1UF
0.1UF
0.1UF
M14
M15
OUT
P63/KIN3*
P64/KIN4*
VCL
OUT
57
P13
P14
22
SMC_PM_G2_EN
OUT
SMC_ADAPTER_EN OUT
SPI_ARB
IN
SPI_SCLK
IN
SPI_SI
OUT
SPI_SO
IN
SMC_PROCHOT_3_3_L
IN
SMC_CPU_INIT_3_3_L
IN
SMC_CPU_ISENSE IN
SMC_CPU_VSENSE IN
SMC_GPU_ISENSE IN
SMC_GPU_VSENSE IN
SMC_DCIN_ISENSE IN
SMC_PBUS_VSENSE IN
SMC_BATT_ISENSE IN
SMC_FWIRE_ISENSE
IN
SMC_WAKE_SCI_L IN
SMC_TPM_GPIO
OUT
PM_CLKRUN_L
IO
PM_SUS_STAT_L IN
SC_TX_L
OUT
SC_RX_L
IN
SMB_BSB_CLK
IO
SMC_ONOFF_L
IN
SMC_BC_ACOK
IN
SMC_BS_ALRT_L IN
PM_SLP_S3_L
IN
PM_SLP_S4_L
IN
PM_SLP_S5_L
IN
SMC_SUS_CLK
IN
SMB_0_S0_DATA IO
AVREF
23
IN
OUT
62
48 45 41 5
VCC
48
23
BGA
(1 OF 4)
L13
L14
L15
K12
K13
K14
J12
J13
P2
P1
J15
A1
F1
IN
P61/KIN1*
P62/KIN2*
VCC
VCC
62 26
P60/KIN0*
SMC_H8S2116
P11
P12
VCC
OUT
U5800
P10
N14
N15
PM_LAN_ENABLE
B12
SMC_RSTGATE_L
C13
ALL_SYS_PWRGD
A15
RSMRST_PWRGD
B14
SMC_SB_NMI
B15
PM_RSMRST_L
C14
IMVP_VR_ON
D12
PM_PWRBTN_L
C15
SMC_P20
D13
SMC_P21
D14
SMC_P22
D15
SMC_P23
E12
E14
SMC_BATT_CHG_EN
E15
SMC_P26
E13
SMC_P27
F14
LPC_AD<0>
D9
LPC_AD<1>
C9
LPC_AD<2>
A9
LPC_AD<3>
B9
LPC_FRAME_L
D8
SMC_LRESET_L
C8
PCI_CLK_SMC
A8
INT_SERIRQ
D7
SMC_XDP_TMS
A5
SMC_SYS_LED_16B
B5
SMB_BSB_DATA
D5
SMC_TPM_PP
C3
SMC_XDP_TRST_L
B1
SMC_XDP_TCK
C2
SMC_SYS_LED
D3
SMC_SYS_KBDLED
C1
SMC_TX_L
G1
SMC_RX_L
G4
SMB_0_S0_CLK
F2
AVCC
OUT
AVCC
23
=PP3V3_S5_SMC
AVREF
8
UNUSED PINS HAVE THE FORMAT
SMC_XXX WHERE XXX IS THE PORT NUMBER.
THEY ARE SET BY SOFTWARE TO BE
DRIVEN OUTPUTS ALWAYS SO THEY
CAN BE LEFT NO-CONNECTED.
P12
R12
SMC_TRST_LIN
NOSTUFF
1R5803
1R5802
R5898
10K
0
10K
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
OMIT
21
49 22 5
26 23 5
56 48
48 14
23
IN
IN
OUT
IN
IO
48 45 5
IO
23
OUT
23
23
36
51 5
48 45 5
45 5
OUT
IN
OUT
IN
OUT
IN
OUT
48
IN
48
IN
54
OUT
54
OUT
48
OUT
48
OUT
54
IN
54
IN
48
IN
48
IN
55
IN
55
IN
55
IN
48 IN
48
IN
48
IN
53
IN
53
IN
SMC_RCIN_L
BOOT_LPC_SPI_L
PM_SYSRST_L
SMC_TPM_RESET_L
PM_EXTTS_L
PM_THRM_L
SYS_ONEWIRE
PM_BATLOW_L
SMC_EXTSMI_L
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
ISENSE_CAL_EN
SMC_EXCARD_CP
SMC_EXCARD_PWR_EN
SMC_EXCARD_OC_L
SMC_XDP_TDO_3_3
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_ISENSE
SMC_MEM_ISENSE
ALS_LEFT
ALS_RIGHT
R3
P3
R2
N3
R1
N2
M4
N1
B10
A10
D10
A11
B11
C11
A12
D11
G14
G15
G13
G12
H14
H15
H13
H12
M11
P11
R11
N11
P10
R10
N10
M10
U5800
PA0/KIN8*/PA2DC
SMC_H8S2116
PA1/KIN9*/PA2DD
PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD
PE0
BGA
PE1*/ETCK
(2 OF 4)
PE2*/ETDI
PE3*/ETDO
PA4/KIN12*/PS2BC
PA5/KIN13*/PS2BD
PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD
PB0/LSMI*
PB1/LSCI
PE4*/ETMS
PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3
PF2/IRQ10*/TMOY
PF3/IRQ11*/TMOX
PF4/PWM4
PB2
PF5/PWM5
PB3
PB4
PF6/PWM6
PF7/PWM7
PB5
PG0/EXIRQ8*/TMIX
PB6
PB7
PG1/EXIRQ9*/TMIY
PG2/EXIRQ10*/SDA2
PC0/TIOCA0/WUE8*
PG3/EXIRQ11*/SCL2
PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10*
PG4/EXIRQ12*/EXSDAA
PG5/EXIRQ13*/EXSCLA
PC3/TIOCD0/TCLKB/WUE11*
PG6/EXIRQ14*/EXSDAB
PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13*
PG7/EXIRQ15*/EXSCLB
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*
PD0/AN8
PD1/AN9
PH0/EXIRQ6*
PH1/EXIRQ7*
PH2/FWE
PH3/EXEXCL
PH4
PD2/AN10
PD3/AN11
PH5
M3
M2
M1
L4
L2
M7
P6
R6
N6
M6
R5
P5
N5
P9
R9
N9
P8
R8
M8
P7
R7
E1
F3
K2
C4
D4
B3
48
49 48 5
49 48 5
49 48 5
49 48 5
SMC_CASE_OPEN
IN
SMC_TCK
IN
SMC_TDI
IN
SMC_TDO
OUT
SMC_TMS
IN
SMC_PF0
SMC_PF1
SMC_LID
IN
SMC_CPU_RESET_3_3_L
IN
SMC_BATT_ISET
OUT
SMC_BATT_VSET
OUT
SMC_SYS_ISET
OUT
SMC_SYS_VSET
OUT
SPI_CE_L
IO
SMC_XDP_TCK_3_3 IN
SMB_BSA_DATA
IO
SMB_BSA_CLK
IO
SMB_A_S3_DATA
IO
SMB_A_S3_CLK
IO
SMB_B_S0_DATA
IO
SMB_B_S0_CLK
IO
SMC_PROCHOT
OUT
SMC_THRMTRIP
OUT
SMC_FWE
IN
ALS_GAIN
OUT
SMS_INT_L
OUT
SMS_ONOFF_L
OUT
XW5800
SM
1
GND_SMC_AVSS
47 48 51 53
48
48
48 43
48
45 5
48
45 5
48
52 22
48
27
27
27
27
27
27
48
48
48
76 6 5
48 23
55
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15
OMIT
U5800
SMC_H8S2116
BGA
SMC
(4 OF 4)
G3
H3
K3
L3
N4
M5
N7
M12
M13
L12
K15
J14
NC0
NC12
NC1
NC2
NC13
NC14
NC3
NC15
NC4
NC5
NC16
NC17
NC6
NC7
NC18
NC19
NC8
NC20
NC9
NC10
NC21
NC22
F15
A14
C12
C10
C5
A3
B8
E4
H4
M9
N8

SIZE
NC11
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE

58
OF
D
104
SMC_CPU_INIT_3_3_L
SMC Reset Button / Brownout Detect
FWH_INIT_L
5 21 49
MAKE_BASE=TRUE
47
SMC_NB_ISENSE
63
SMC_P1V05S0_ISENSE
=PP3V3_S0_SMC_LS
SMC 1.05V to 3.3V Level Shifting
51
MAKE_BASE=TRUE
63 48 47
=PP3V3_S5_SMC
47
SMC_MEM_ISENSE
SMC_P1V8S3_ISENSE
51
MAKE_BASE=TRUE
47 14
C5900
R5900
0.1uF
5%
1/16W
MF-LF
2 402
U5900
RN5VD30A-F
SOT23-5
SMC_MANUAL_RST_L
OMIT
R5901
Silk: "SMC RST"
C5901
5
4
NC
47
SMC_SYS_LED
47
SMC_ANALOG_ID
SMC_RST_L
47
SMC_BATT_VSET
5%
1/16W
MF-LF
402 2
10%
16V
CERM 2
402
47
SMC_FAN_2_CTL
TP_SMC_BATT_VSET
48 7
LMC7211
V+
CPU_PROCHOT_L
SMC_FAN_3_CTL
SMC_FAN_3_TACH
47
SMC_XDP_TCK
47
1K
5%
1/16W
MF-LF
402 2
TP_SMC_FAN_2_TACH
MAKE_BASE=TRUE
47
SMC_PROCHOT_3_3_L
V-
R59711
TP_SMC_FAN_2_CTL
47
SM-LF
1
MAKE_BASE=TRUE
SMC_FAN_2_TACH
U5977
2
4
TP_SMC_SYS_VSET
MAKE_BASE=TRUE
47
1.05V Mid-Reference
VOLTAGE=0.46V
MAKE_BASE=TRUE
SMC_SYS_VSET
20%
10V
CERM 2
402
P0V46_SMC_LSREF
TP_SMC_ANALOG_ID
MAKE_BASE=TRUE
47
0.1uF
6.2K
TP_SMC_SYS_LED
OUT
C5977 1
R59701
28 29
MAKE_BASE=TRUE
GND
3
CRITICAL
0.01UF
5%
1/10W
MF-LF
2 603
OUT
CD
NC
DIMM_OVERTEMP_L
1K
VDD
20%
10V
CERM 2
402
PM_EXTTS_L
MAKE_BASE=TRUE
TP_SMC_FAN_3_CTL
MAKE_BASE=TRUE
TP_SMC_FAN_3_TACH
MAKE_BASE=TRUE
TP_SMC_XDP_TCK
MAKE_BASE=TRUE
SMC_XDP_TDO_L
SMC Crystal Circuit
Debug Power Button
CRITICAL
Y5920
20.00MHZ
5X3.2-SM
OUT
R5910
15pF
SMC_EXTAL
SMC_ONOFF_L
OMIT
1
Silk: "PWR BTN"
C5921
2
47
51 48 47 43 5
5%
50V
CERM
402
SMC_XDP_TRST_L
47
SMC_P20
47
SMC_P21
47
SMC_P22
TP_SMC_XDP_TRST_L
CPU_PROCHOT_L
TP_SMC_P20
5%
1/10W
MF-LF
2 603
TP_SMC_P21
2N7002DW-X-F
SMC_P23
47
SMC_P26
47
SMC_PROCHOT
TP_SMC_P23
4
MAKE_BASE=TRUE
TP_SMC_P26
MAKE_BASE=TRUE
47
SMC_P27
47
SMC_PF0
47
SMC_PF1
TP_SMC_P27
MAKE_BASE=TRUE
TP_SMC_PF0
PM_THRMTRIP_L
TP_SMC_PF1
47
SMC AVREF Supply
SMC_TPM_GPIO
2N7002DW-X-F
REF3133
PP3V3_AVREF_SMC
SOT23-3
IN
OUT
VOLTAGE=3.3V
1
SMC_TPM_PP
20%
2 16V
CERM
402
47
TPM_GPIO2
56
TPM_PP
56
63 48 47
63 56
63 55
47
SC_TX_L
47 51 53
SMC_RX_L
47 23
5 47 48 49
56 47
5%
1/16W
MF-LF
402
R5993
VOLTAGE=0V
SMC_TX_L
51 48 47 43 5
5 47 48 49
47 43
5%
1/16W
MF-LF
402
47
49 48 47 5
R5994
47
SMC_EXCARD_OC_L
49 48 47 5
EXCARD_OC_L
47 45 5
64 47 5
49 47 5
SMC PWRGD Circuit

System (Sleep) LED Circuit
49 47 5
49 47 5
49 47 5
Reports when 5V S5 and 3.3V S5 are in regulation
47
63
63
=PP5V_S3_SYSLED
PP5V_S5
=PP3V42_G3H_SMC_PWRGD
47
47
47 45 5
5%
1/16W
MF-LF
402 2
C5960 1
R5950
R59611
100
10K
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402 2
SYS_LED_ILIM
R5963
16.2K
1%
1/16W
MF-LF
2 402
47 45 41 5
20%
10V
CERM 2
402
P1V71_SMC_REF
1.71V Reference
47 45 5
0.1uF
47
47 45 5
2
4
SYS_LED_L_VDIV
Q5950
4.7K
5%
1/16W
MF-LF
402 2
76
R5962
SYS_LED_ANODE
SM-LF
1
V-
10K
1%
1/16W
MF-LF
402 2
OUT
47 23
P5VS5_PGOOD
62
R5930
R5931
10K
10K
SMC_ONOFF_L
SMC_LID
SMC_FWE
SMC_TX_L
SMC_RX_L
R5932
R5933
R5934
R5935
R5936
10K
100K
10K
10K
100K
SYS_ONEWIRE
SMC_BS_ALRT_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_CPU_RESET_3_3_L
SMC_XDP_TCK_3_3
SMC_XDP_TDO_3_3
R5937
R5938
R5939
R5940
R5941
R5942
R5980
R5981
R5982
ONEWIRE_PU
2.0K 1
2
5%
100K 1
2
5%
10K 1
2
5%
10K 1
2
5%
10K 1
2
5%
10K 1
2
5%
10K 1
2
5%
10K 1
2
5%
10K 1
2
SMC_BATT_CHG_EN
SMC_ADAPTER_EN
SMC_CASE_OPEN
SMC_BC_ACOK
SMC_EXCARD_CP
PM_SUS_STAT_L
PM_SLP_S5_L
R5943
R5944
R5945
R5946
R5947
R5948
R5983
R5984
10K
10K
10K
10K
470K
10K
100K
100K
R5964
1%
1/16W
MF-LF
2 402
Q5952
61
2N7002
402
402
402
402
402
5%
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
402
402
402
402
402
5%
5%
5%
5%
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
402
402
402
402
SMC Support
SOT23-LF
IN
=P3V3S5_PGOOD
ISL6269 undervoltage threshold 81-87% (2.67 - 2.87V)
NOTE: R5965 acts as 10K pull-up for PGOOD signal
SYNC_DATE=(MASTER)

47
RSMRST_PWRGD
MAKE_BASE=TRUE
1

OUT

C5969
0.0022uF
SIZE
10%
2 50V
CERM
402
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
10K
1/16W
1/16W
1/16W
1/16W
1/16W
SMC_SYS_LED_16B
5%
5%
5%
5%
5%
R5965
5%
1/16W
MF-LF
2 402
10K
5V Comp threshold set to 4.480V (89.6%)
IN
1/16W MF-LF 402

1/16W MF-LF 402
OUT
SYS_LED_L
47
5%
5%
1
5
R5952
P5VS5_COMP_POS
2N3906
SOT23-LF
56 49 47 23 5
LMC7211
V+
47 45 5
U5960
=PP3V3_S5_SMC
=PP3V3_S3_TPM
=PP3V3_S3_SMS
SMS_INT_L
SMC_TPM_RESET_L
5 6 45
5%
1/16W
MF-LF
402
2.2K
SOT-363
5%
1/16W
MF-LF
402
SC_RX_L
20%
6.3V 2
X5R
603
GND_SMC_AVSS
56
R5992
10uF
20%
2 6.3V
CERM-X5R
402
5%
1/16W
MF-LF
402
C5967
0.01uF
C5965 C5966 1
SMC_THRMTRIP
R5991
R5995
47
0.47uF
TPM_GPIO1
SMC_TPM_GPIO2
SMC_TPM_PP
47
GND
47
VR5965
1
5%
1/16W
MF-LF
402
CRITICAL
=PP3V42_G3H_SMCVREF
Q5995
R5990
R59511
7 14 21
MAKE_BASE=TRUE
SMC_TPM_GPIO1
63
SOT-363
MAKE_BASE=TRUE
63
Q5995
TP_SMC_P22
MAKE_BASE=TRUE
47
7 48
MAKE_BASE=TRUE
MAKE_BASE=TRUE
5%
50V
CERM
402
47
MAKE_BASE=TRUE
15pF
SMC_XTAL
SMC 3.3V to 1.05V Level Shifting
TP_SMC_XDP_TMS
MAKE_BASE=TRUE
C5920
47
TP_SMC_XDP_TDO_L
MAKE_BASE=TRUE
SMC_XDP_TMS
59
OF
D
104
CRITICAL
LPCPLUS
J6000
QT500306-L021-9F
NC
48 21 5
34 5
56 47 21 5
56 47 21 5
56 47 23 5
56 48 47 23 5
48 47 5
48 47 5
48 47 5
47 5
48 47 5
23 5
FWH_INIT_L
PCI_CLK_PORT80_LPC
LPC_AD<2>
LPC_AD<3>
INT_SERIRQ
PM_SUS_STAT_L
SMC_TDI
SMC_TCK
SMC_RST_L
SMC_NMI
SMC_RX_L
SV_SET_UP (GPIO15)
NC
32
M-ST-SM
31
10
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
34
33
NC
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
LPC_AD<0>
LPC_AD<1>
LPC_FRAME_L
PM_CLKRUN_L
BOOT_LPC_SPI_L
SMC_TMS
DEBUG_RST_L
SMC_TRST_L
SMC_TDO
SMC_MD1
SMC_TX_L
5 63
5 63
5 21 47 56
5 21 47 56
5 21 47 56
5 23 40 47 56
5 22 47
5 47 48
5 26
5 47
5 47 48
5 47
5 47 48
NC
516S0384

SYNC_MASTER=M42

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
60
OF
D
104
GPU / Heat Pipe Thermal Sensor

72
ATI_TDIODE_P
ATI_TDIODE_N
GPUTHM_A_GPU
R61111
GPUTHM_A_GPU
1
R6110
5%
1/16W
MF-LF
402 2
0
5%
1/16W
MF-LF
2 402
63
GPUTHM_A_DIODE
Placement note:
Q6115
GPUTHMSNS_DX_A_P
5%
1/16W
MF-LF
402
2N3904LF
Layout note:
GPUTHM_A_DIODE
SOT23
GPUTHMSNS_DX_A_DIO_N
Minimize stubs
J6120
Place in between VRAM
20%
10V
2 CERM
402
U6100
XW6111
SM
1
HSTHMSNS_DX_P
HSTHMSNS_HAS
MAX6695AUB
UMAX
GPUTHMSNS_DXP1
GPUTHMSNS_DXN
GPUTHMSNS_DXP2
2 DXP1
3 DXN
4 DXP2
SMBDATA
SMBCLK
ALERT*
2
OT1*
CRITICAL
OT2*
C6120 1
NC
0.0022uF
XW6121
SM
HSTHMSNS_DX_N
NC
9
7
8
=SMBUS_GPUTHMSNS_SDA
=SMBUS_GPUTHMSNS_SCL
NC
5
10
NC
NC
27
27
GND
10%
50V
CERM 2
402
C6100
0.1uF
0.0022uF
SYM_1
402
XW6120
SM
F-RT-SM
Placement note:
VCC
GPUTHMSNS_DX_A_N
88460-0201
3
PP3V3_S0_GPUTHMSNS_R
10%
50V
CERM 2
402
5%
1/16W
MF-LF
402
CRITICAL
C6110
R6116
GPUTHMSNS_DX_A_DIO_P
47
5%
1/16W
XW6110
MF-LF
SM
R6115
Place near GPU center
R6100
=PP3V3_S0_GPUTHMSNS
72
Placement note:
Keep all 4 XWs as close
to U6100 as possible
518S0226
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
RES,0,1/16W,0402
C6120
116S0004
CRITICAL
BOM OPTION
HSTHMSNS_NOT
Right-Side/Fin Stack Thermal Sensor

63
C6150 1
CRITICAL
88460-0201
SYM_1
Placement note:
Place near speaker hole
NC
RSFSTHMSNS_D_P
499
RSFSTHMSNS_D_N
518S0226
499
VDD
1
C6160
0.001UF
R6161
5%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402
NC
10K
10%
16V 2
X5R
402
R6160
F-RT-SM
R61511
0.1UF
J6160
3
=PP3V3_S0_RSTHMSNS
20%
50V
2 CERM
402
RSFSTHMSNS_D_R_P
RSFSTHMSNS_D_R_N
2 D+
3 D-
ALERT*/ 6
THM2*
THM* 4
MSOP
CRITICAL
1%
1/16W
MF-LF
402
SCLK 8
SDATA 7
R6152
10K
5%
1/16W
MF-LF
2 402
RSTHMSNS_ALERT_L
U6150
ADT7461
RSTHMSNS_THM_L
27
27
=SMBUS_RSTHMSNS_SCL
=SMBUS_RSTHMSNS_SDA
IO
IO
GND
5
Placement note:
Place U6150 below and to the
left of the speaker hole.
CPU Back-Up Thermal Diode

CPUTHM_DIODE
R6190
Placement note:
CPUTHMSNS_DIO_P
Place near CPU center

3
Q6190
THRM_CPU_DX_P
CPUTHM_DIODE
SOT23
10
Layout note:
2N3904LF
Minimize stubs between

these Rs and R1001 & R1002
Thermal Sensors
R6191
5%
1/16W
MF-LF
402
CPUTHMSNS_DIO_N
THRM_CPU_DX_N
10
SYNC_DATE=(MASTER)
5%
1/16W
MF-LF
402

R1001 / R1002 are not currently BOMOPTIONed. Can not

programatically unstuff those parts to stuff these.

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
61
OF
D
104
XW6209
SM
=PPVCORE_S0_CPU
R6209
CPUVSENSE_IN
4.53K2
SMC_CPU_VSENSE
47
1%
1/16W
MF-LF
402
Place short near U0700 center
Q6215
OUT
FDG6332C_NL
0.22UF
63
63
This half of Q6216 acts

as a level-shifter
between PBUS and 3.42V
=PP3V42_G3H_PBUSVSENS
47 48 51 53
SMC_ONOFF_L
GPUVSENSE_IN
Enables PBUS VSense divider when

SMC_ONOFF_L is low (power button
pressed or driven low by SMC)
R6259
4.53K2
1
SMC_GPU_VSENSE
47
1%
1/16W
MF-LF
402
Place short near U8400 center
47
2N7002DW-X-F
R62861
SOT-363
This half of Q6216 acts as a

diode to keep Q6215 from
pulling SMC_ONOFF_L low.
62
=PBUSVSENS_EN
2 G
C6285
GND_SMC_AVSS
Q6215
OUT
20%
6.3V
2 X5R
402
6
N-CHN
20%
2 6.3V
X5R
402
SMC_PBUS_VSENSE
0.22UF
1%
1/16W
MF-LF
402 2
R5808 is pull-up
0.22UF
5.49K
OUT
Rthevanin = 4573 ohms
PBUSVSENS_EN_L
Q6216
C6259
27.4K
1%
1/16W
MF-LF
402 2
1
S
GPU Voltage Sense / Filter
R62851
1%
1/16W
MF-LF
402 2
PBUSVSENS_PWRBTN_L
PPBUS_G3H_VSENSE
G
5
100K
2N7002DW-X-F
4 S
VOLTAGE=12.6V
SOT-363
48 47 43 5
R62151
Q6216
XW6259
SM
P-CHN
PPBUS_G3H
4
GND_SMC_AVSS
Place RC close to SMC
=PPVCORE_S0_GPU
SC70-6
C6209
20%
2 6.3V
X5R
402
72 67 63 51
PBUS Voltage Sense Enable & Filter
CPU Voltage Sense / Filter

63 51 9 8
47 48 51 53
FDG6332C_NL
SC70-6
GND_SMC_AVSS
Enables PBUS VSense divider when high.
47 48 51 53
C
FireWire Current Sense Filter
DCIN Current Sense Filter
R6230
41
IN
4.53K2
FWPWR_IOUT
1%
1/16W
MF-LF
402
R6280
47
SMC_FWIRE_ISENSE
45 5
IN
OUT
LIO_DCIN_ISENSE
R6290
4.53K2
47
1%
1/16W
MF-LF
402
C6230
0.22UF
GND_SMC_AVSS
4.53K2
CPUVCORE_IOUT
IN
1%
1/16W
MF-LF
402
SMC_CPU_ISENSE
66
OUT
IN
4.53K2
GPUVCORE_IOUT
1%
1/16W
MF-LF
402
C6270
0.22UF
GND_SMC_AVSS
47 48 51 53
4.53K2
0.22UF
SMC_GPU_ISENSE
60
OUT
IN
P1V8S3_IOUT
48
1%
1/16W
MF-LF
402
0.22UF
SMC_BATT_ISENSE
OUT
C6290
0.22UF
GND_SMC_AVSS
47 48 51 53
SMC_P1V8S3_ISENSE
47 48 51 53
1.05V S0 (NB) Current Sense Filter

61
OUT
IN
P1V05S0_IOUT
4.53K2
1%
1/16W
MF-LF
402
C6235
0.22UF
20%
6.3V
2 X5R
402
20%
6.3V
2 X5R
402
GND_SMC_AVSS
GND_SMC_AVSS
47 48 51 53
R6240
4.53K2
C6275
47
20%
6.3V
2 X5R
402
R6235
47
20%
6.3V
2 X5R
402
LIO_BATT_ISENSE
1%
1/16W
MF-LF
402
1.8V S3 (Memory) Current Sense Filter
R6275
47
45 5
IN
OUT
C6280
GND_SMC_AVSS
47 48 51 53
GPU Current Sense Filter
R6270
57
SMC_DCIN_ISENSE
20%
6.3V
2 X5R
402
20%
6.3V
2 X5R
402
CPU Current Sense Filter
Battery Current Sense Filter
48
SMC_P1V05S0_ISENSE
OUT
C6240
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS
47 48 51 53
47 48 51 53
Current Sense Calibration Circuit

Switches in fixed load on power supplies to calibrate current sense circuits
Q6229
FDG6332C_NL
SC70-6
63 51 9 8
63 5
=PPVCORE_S0_CPU
72 67 63 51
=PPVCORE_S0_GPU
ISENSE_CAL_EN_LS5V
R62291
G
5
470K
5%
1/16W
MF-LF
402 2
R6220
R6228
470K
CPUVCORE_ISENSE_CAL
GPUVCORE_ISENSE_CAL
7
N-CHN
FDG6332C_NL
FDC796N
SUPERSOT-6
SC70-6
1
2 3
Q6221
P1V8S3_ISENSE_CAL
7
2 3
P1V05S0_ISENSE_CAL
7
1.0A / 1.8W
CRITICAL
D
Q6222
FDC796N
SUPERSOT-6
S
6
1%
1/4W
MF-LF
1206 2
1.2A / 1.44W
CRITICAL
D
FDC796N
SUPERSOT-6
Q6229
R62271
Q6220
2 G
1.00
1%
1/4W
MF-LF
1206 2
R62231
1.82
1%
1/4W
MF-LF
1206 2
CRITICAL
ISENSE_CAL_EN
=PP1V05_S0_REG
R6222
1.00
ISENSE_CAL_EN_L
IN
63 61 5
R6221
1%
1/4W
MF-LF
1206 2
5%
1/16W
MF-LF
2 402
47 5
=PP1V8_S3_REG
1.00
63 60 5
P-CHN
=PP5V_S0_ISENSECAL
3 5
Current & Voltage Sensing
Q6223
FDC796N
SUPERSOT-6
S
6
1.05A / 1.1W
CRITICAL
D
S
6
3 5
6
100K
5%
1/16W
MF-LF
402 2

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
SYNC_DATE=(MASTER)
62
OF
D
104
63
=PP3V3_S5_ROM
D
1
1
1
R6302
R6301
3.3K
3.3K
20%
2 10V
CERM
5%
1/16W
MF-LF
4022
402
5%
1/16W
MF-LF
4022
C6312
0.1UF
CRITICAL
8 OMIT
U6301
SPI_CE_L
5%
1/16W
MF-LF
402
C6309
22pF
5%
2 50V
CERM
402
NOSTUFF
16MBIT
SPI_SCLK_R
SOI
1 CE*
SPI_WP_L3
7
SPI_HOLD_L
C6308
22pF R6309
10K
5%
2 50V
CERM
402
6 SCK
SI 5
SST25VF016B
47 22
SPI_SCLK
5%
1/16W
MF-LF
402
SO 2
WP*
HOLD*
R6306
47
1
5%
1/16W
R6303
402
47 MF-LF
1
SPI_SO_R
5%
1/16W
MF-LF
402
VSS
C6301
22pF
5%
2 50V
CERM
5%
1/16W
MF-LF
402
SPI_SI_R
402
SPI_SI
22 47
SPI_SO
22 47
C6311
22pF
5%
2 50V
CERM
402
47 22
R6307
47
R6308
10K
1
VDD
C
R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH
R6307
AND
R6306
SHOULD
BE
PLACED
LESS
THAN
100
MILS
FORM ICH7M
ICH7M AND TEKOA(LAN CHIP)
R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM
SPI BOOTROM
SYNC_MASTER=M42

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
63
OF
D
104
Right ALS Circuit

63
=PP3V3_S3_RTALS
C6405 1
0.1UF
20%
10V
CERM 2
402
Left ALS Filter
CRITICAL
U6405
RTALS_OP_IN and RTALS_OP_COMP need to be matched

4
V+
R6401
Left ALS circuit has 1K series-R

RTALS_PHOTODIODE
R6430
76 5
LTALS_OUT
3.48K2
1%
1/16W
MF-LF
402
47
ALS_LEFT
OUT
PD6400
20%
2 6.3V
X5R
402
GND_SMC_AVSS
R64001
BS520EOF
0.22UF
RTALS_OP_IN
5.1M
TH
SOT23-6-LF
1
R6410
ALS_RT_OUT
4.53K2
1%
1/16W
MF-LF
402
5
V-
47
ALS_RIGHT
OUT
C6410
0.22UF
20%
2 6.3V
X5R
402
C6400
GND_SMC_AVSS
0.01UF
5%
1/16W
MF-LF
402 2
MAX4236EUTT
1%
1/16W
MF-LF
402
CRITICAL
C6430
1K
20%
2 16V
CERM
402
C6406 1
0.22UF
20%
6.3V 2
X5R
402
47 48 51 53
47 48 51 53
R6406
120K
5%
1/16W
MF-LF
2 402
RTALS_OP_COMP
R64081
R6407
1K
15.0K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
RTALS_GAIN_L
3
Q6408
2N7002
IN
=RTALS_GAIN
SOT23-LF
Keyboard LED Driver

B
B
CRITICAL
L6450
63
22uH
=PP5V_S0_KBDLED
1
2
3.8x3.8x1.5MM
63
1
R64511 C6450
1uF
10K
IN
SMC_SYS_KBDLED
KBDLED_HAS
VDD
10%
6.3V
CERM 2
402
5%
1/16W
MF-LF
402 2
47
KBDLED_SW
=PP3V3_S0_KBDLED
KBDLED_NOT
CRITICAL
SW
U6450
MM3120
NC
3 CNTRLLLP VOUT 8
43
KBDLED_ANODE
6 NC
43
KBDLED_RETURN
R64521
FB 4
THRML_PAD 9
10K
PGND
5%
1/16W
MF-LF
402 2
AGND
NC
1
OUT
IN
C6455 R6455
25.5
0.22uF
20%
2 25V
X5R
603
1%
1/8W
MF-LF
2 805
ALS Support
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
64
OF
D
104
Left Fan
C
63 5
63
Right Fan
=PP5V_S0_FAN_LT
=PP3V3_S0_FAN_LT
63
63
=PP5V_S0_FAN_RT
=PP3V3_S0_FAN_RT
CRITICAL
47K
5%
1/16W
MF-LF
402 2
R6555
47
SMC_FAN_0_TACH
47K
NC
5%
1/16W
MF-LF
402
NC
100K
5%
1/16W
MF-LF
402 2
47
SMC_FAN_0_CTL
Q6560
2N7002DW-X-F
G
4 S
SOT-363
3
5
J6560
R65601
47K
5%
1/16W
MF-LF
402 2
R6565
1
2
3
4
FAN_LT_TACH
R65511
CRITICAL
J6550
SM-2MT-LF
R65501
47
SMC_FAN_1_TACH
47K
NC
1
2
3
4
FAN_RT_TACH
5%
1/16W
MF-LF
402
R65611
NC
100K
5%
1/16W
MF-LF
402 2
518S0293
FAN_LT_PWM
47
SMC_FAN_1_CTL
2
G
1 S
Q6560
2N7002DW-X-F
SOT-363
D 6
5
SM-2MT-LF
5
518S0293
FAN_RT_PWM
Fan Connectors
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
65
OF
D
104
63 48
=PP3V3_S3_SMS
R66201
5%
1/16W
MF-LF
402 2
C6620
0.1uF
20%
2 10V
CERM
402
10K
VDD
U6620
KXM52-2050
QFN
SMS_ACC_SELFTEST
OUTPUTX 2
SMS_X_AXIS
47
9 PS
OUTPUTY 13
SMS_Y_AXIS
47
5 PARITY
OUTPUTZ 14
SMS_Z_AXIS
47
10 SELF
TEST
47
SMS_ONOFF_L
NC
4
6
7
11
R6621
10K
5%
1/16W
MF-LF
1 402
CRITICAL
RSVD
RSVD
DNC 1
GND
THRML
PAD
3 12 15
Desired orientation when

placed on board top-side:
Package Top
NC
RSVD
RSVD
C6604
0.033UF
20%
2 10V
X7R
402
C6606
0.033UF
20%
2 10V
X7R
402
Top-through View
+Y
+Z (up)
Desired orientation when

placed on board bottom-side:
+Y
+X
C6605
0.033UF
20%
2 10V
X7R
402
+X
+Z (dn)
M1 placement: Bottom-side
Sudden Motion Sensor (SMS)

SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
66
OF
D
104
63 56
=PP3V3_S0_TPM
NOSTUFF
1 C6701
1 C6702
C6700
0.1UF 0.1UF 0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
5%
1/8W
MF-LF
2805
OMIT
NOSTUFF
R6700
0
LAYOUT NOTE:
5%
PLACE WHERE ACCESSIBLE
1/16W
MF-LF
2402
48
IO
49 47 21 5
IO
34
IO
49 47 21 5
IN
49 47 21 5
IN
49 48 47 23 5
IN
49 47 23 5
IO
49 47 40 23 5
IO
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
26
23
20
17
PCI_CLK_TPM
LPC_FRAME_L
21
22
16
PM_SUS_STAT_L 28
INT_SERIRQ
27
PM_CLKRUN_L
15
TPM_PP
48
TPM_GPIO1
48
TPM_GPIO2
7
6
NC 1
2
TPM_XTALI
TPM_XTALO
13
14
35
LAD1
LAD2
LAD3
U6700
TPM
TSSOP
3V0
VDD
3V1
VDD
3V2
VDD
3VSB
VNC
VSB
LCLK
NC
LFRAME*
VBAT
LRESET*
LPCPD*
10
19
24
NC
26
IN
TPM_LRESET_L
VOLTAGE=3.3V
NC
R6702
10K
5%
1/16W
MF-LF
2402
CLKRUN/GPIO*
CLKRUN*
PP/GPIO (INT PD)
PP
GPIO_EXPRESS_00
GPIO
GPIO/SM_DAT
NC
TESTBI/BADD/GPIO
GPIO/SM_CLK
TESTBI/BADD
GPIO2
TESTI
C6703
0.1UF
10%
2 16V
X5R
402
12 NC
SERRIRQ
=PP3V3_S3_TPM
48 63
5%
1/8W
MF-LF
805
BASE ADDR = 0X4E/4F
LAYOUT NOTE:
PLACE R6702-03 WHERE ACCESSIBLE
9 TPM_BADD
8
NOSTUFF
XTALI/32K_IN
XTALO
R6704
0
PP3V3_TPM_3VSB
GND
R6703
10K
5%
1/16W
MF-LF
2402
4
11
18
25
35
LAD0
GND2
GND3
=PP3V3_S0_TPM
IO
49 47 21 5
GND0
GND1
63 56
49 47 21 5
NOTE:
SINCE CURRENT OF VSB IS NOT YET ON SPEC,
1/8W (R6704/R6705) IS USED FOR NOW
R6705
0
10%
2 16V
X5R
402
BASE ADDR = 0X2E/2F
R6798
0
1
5%
1/16W
MF-LF
402
TPM_RST_L
NOSTUFF
B
48 47
IN
SMC_TPM_RESET_L
R6799
0
1
5%
1/16W
MF-LF
402
TPM
SYNC_MASTER=M38

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
67
OF
D
104
=PPVIN_S0_IMVP6
63 57
63
These caps for Q7500
10
R7544
499
C7528 1
9
9
9
(IMVP6_NTC)
9
9
CRITICAL
C7546 1
470K
10%
16V
CERM 2
402
0.01uF
402
2
21 7
IN
79
IN
62
26
R7547
IN
1%
1/16W
MF-LF
402 2
R7532
C7532 1
OUT
47
4.02K
26 14
IN
OUT
147K
0.015uF
1%
1/16W
MF-LF
2 402
10%
16V 2
X7R
402
46
45
2
3
VR_PWRGD_CK410_L
IMVP_VR_ON
VR_PWRGOOD_DELAY
IMVP6_VR_TT
IMVP6_NTC
(GND_IMVP6_SGND)
IMVP6_SOFT
48
47
44
1
5
6
VID6
22
R7536
2.0K
10%
50V
CERM 2
402
1%
1/16W
MF-LF
2 402
IMVP6_VDIFF_RC
VDD
OMIT
VID5
U7530
VID4
36
BOOT1
BOOT2 26
1-Phase
CCM
1-Phase
DCM
1-Phase
QFN
VID3
35
UGATE1
IMVP6_UGATE1
34
IMVP6_PHASE1
LGATE1 32
IMVP6_LGATE1
VID2
PHASE1
C7550 1
IMVP6_BOOT1
IMVP6_BOOT2
ISL6262
VID0
DPRSLPVR
0.22uF
20%
25V
2 X5R
603
PGND1 33
(GND)
ISEN1 24
PGD_IN
IMVP6_ISEN1
UGATE2
PHASE2
27
IMVP6_UGATE2
Q7501
DCM
HAT2165H
CLK_EN*
LGATE2
VR_ON
28
IMVP6_PHASE2
30
IMVP6_LGATE2
PGND2
29
(GND)
PGOOD
VR_TT*
Q7502
LFPAK
20%
6.3V
X5R
402
NO STUFF
C7501
0.0022UF
10%
2 50V
CERM
402
R7506
3.65K
1%
1/10W
MF-LF
2 603
B340LBXF
0.0022UF
10%
2 50V
CERM
402
D7500
SMB
1 2 3
C7502
(IMVP6_ISEN1)
ISEN2
C
CRITICAL
23
IMVP6_ISEN2
19
8
18
16
IMVP6_VSUM
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP
Q7550
HAT2168H
LFPAK
NTC
CRITICAL
VSUM
7 SOFT
4 RBIAS
13 VDIFF
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
12
11
10
9
VO
DROOP
57
0.001uF
1%
1/16W
MF-LF
402
C7580 1
VW
R7542
TPAD
HAT2165H
1%
1/16W
MF-LF
2 402
5%
50V
CERM 2
402
LFPAK
9.31K
180pF
1%
1/16W
MF-LF
2 402
Q7551
R7541 C7540 1
1K
10%
25V
CERM 2
402
5%
1/16W
MF-LF
402 2
CRITICAL
4
0.0068uF
R75571
10%
50V
CERM 2
402
3.01K2
14
RTN 15
HAT2165H
CRITICAL
10%
16V
2 CERM
402
330pF
10%
50V
CERM 2
402
R7543
11K
1%
1/16W
MF-LF
2 402
0.22UF
1
20%
6.3V
X5R
402
GND_IMVP6_SGND
C7543
10K
1%
1/16W
MF-LF
402
Q7552
1 2 3
(IMVP6_VO)
1
C7555
R7555
CRITICAL
LFPAK
49
2
SM-PCC
C7542 1
R7540
IMVP6_DFB
VSEN
COMP
0.36uH
(IMVP6_PHASE2)
NO STUFF
FB
L7555
1 2 3
FB2
21
C7535
0.22UF
1%
1/16W
MF-LF
402
HAT2165H
NO STUFF
3V3
VSS
10%
2 50V
CERM
402
10K
63
C7505
R7505
CRITICAL
0.01uF
390pF
5%
1/16W
MF-LF
402 2
CRITICAL
0.22uF
20%
25V
X5R 2
603
(IMVP6_FB)
C7534
20%
16V
X5R
1210
Vout = Variable
36A max output
(Inductors limit)
R75071
C7500
PSI*
1.40K
22UF
20%
16V 2
X5R
1210
DPRSTP*
IMVP6_RBIAS
(GND_IMVP6_SGND)
IMVP6_VDIFF
1%
1/16W
MF-LF
2 402
VID1
R7533
1%
1/16W
MF-LF
402 2
PVCC
1.82K
1 2 3
25 NC
R75351
CCM
31
DFB 17
470pF
2-Phase
CRITICAL
NO STUFF
1
LFPAK
OCSET
5
C7533
CPU_DPRSTP_L
IMVP_DPRSLPVR
CPU_PSI_L
IMVP_PWRGD_IN
IMVP6_NTC_R
10%
16V 2
X5R
603
VIN
9
22UF
20%
16V 2
X5R
1210
=PPVOUT_S0_IMVP6_REG
2
SM-PCC
1uF
20
1%
1/16W
MF-LF
402
R7546
0.36uH
(IMVP6_PHASE2)
43
42
41
40
39
38
37
22UF
20%
16V 2
X5R
1210
L7505
DPRSLPVR DPRSTP* PSI* Operation Mode
10%
16V 2
X5R
402
IMVP6_VID<6>
IMVP6_VID<5>
IMVP6_VID<4>
IMVP6_VID<3>
IMVP6_VID<2>
IMVP6_VID<1>
IMVP6_VID<0>
22UF
20%
16V
X5R
1210
CRITICAL
C7560 1 C7561 1 C7562 1 C7563
22UF
20%
16V 2
X5R
1210
1 2 3
0.1uF
R7545
PM_DPRSLPVR
IN
22UF
20%
16V 2
X5R
1210
HAT2168H
C7531
1%
1/16W
MF-LF
2 402
22UF
LFPAK
VOLTAGE=12V
1
499
79 23 14
Q7500
1uF
PPVIN_S0_IMVP6_R
VOLTAGE=3.3V
10%
6.3V 2
CERM
402
PP3V3_S0_IMVP6_R
5%
1/16W
MF-LF
402
10
5%
1/16W
MF-LF
402
R7528
10
C7530 1
20%
16V 2
X5R
1210
CRITICAL
20%
2 6.3V
CERM
603
VOLTAGE=5V
22UF
C7529
4.7uF
PP5V_S0_IMVP6_VDD
R7531
=PPVIN_S0_IMVP6
5%
1/16W
MF-LF
402
=PP3V3_S0_IMVP6
These caps for Q7550
C7510 1 C7511 1 C7512 1 C7513
63
=PP5V_S0_IMVP6
R7530
63 57
NO STUFF
R7548
3.92K
1%
1/16W
MF-LF
402 2
NO STUFF
C7551
0.0022UF
C7552
10%
2 50V
CERM
402
R7556
3.65K
1%
1/10W
MF-LF
2 603
B340LBXF
0.0022UF
10%
2 50V
CERM
402
D7550
SMB
1 2 3
IMVP6_VO_R
IMVP6_COMP_RC
(IMVP6_VW)
CRITICAL
R75341
C7537 1
182K
47pF
1%
1/16W
MF-LF
402 2
5%
50V
CERM 2
402
R7537
R7549
C7544 1
4.42K
1%
1/16W
MF-LF
2 402
10KOHM-5%
0.22uF
20%
6.3V 2
X5R
402
0603-LF
2
(IMVP6_ISEN2)
(IMVP6_COMP)
R7581
(IMVP6_VSUM)
(IMVP6_VO)
79
79
NO STUFF
XW7530
SM
2
C7541 1
C7582 1
0.22UF
0.01uF
20%
6.3V
X5R 2
402
10%
16V
CERM 2
402
0.01uF
10%
16V
2 CERM
402
63
C7598
=PP3V3R5V_S0_CPUISENS
470pF
1
C7595
1uF
10%
6.3V 2
CERM
402
OUT
1M
CPUVCORE_IOUT
CPUISENS_POS
C7592
1
1M
8 79
30.1K2
SYNC_DATE=(MASTER)
IMVP6_DROOP

57

1%
1/16W
MF-LF
402
SIZE
APPLE COMPUTER INC.
10%
50V
CERM
402
CPU_VCCSENSE_N
1%
1/16W
MF-LF
402
<Rc>
1
R7591
2
470pF
0.1uF
IMVP6 CPU VCore Regulator
R7592
Vout @ 36A = 2.44V-2.60V
C7594
8 79
R7582
5%
1/16W
MF-LF
402
<Ra + Rb>
= Rc / (Ra + Rb)
Voffset worst-case ~2.3mV (+/- ~1A offset)
CPU_VCCSENSE_P
20%
2 10V
CERM
402
Voffset = (Vdrp_offset * Kdroop) + Vamp_offset
CPUISENS_NEG_RC
NO STUFF
SOT23-5
1
= Gain * ((2.1 mV/A * Iload) + Voffset)
Gain
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
U7595 5
51
<Rb>
R7594
R7598
LMV2011MF
<Ra>
<Rc>
10%
50V
CERM
402
5%
1/16W
MF-LF
402
R7593
30.1K2
1
CPUISENS_NEG
Vout
IMVP6_VSEN_P
IMVP6_VSEN_N
CPU VCore Current Sense
C7581
5%
1/16W
MF-LF
402
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
75
OF
D
104
7
63
=PPVIN_S5_P5VP1V5
1
C7640
22UF
20%
2 16V
X5R
1210
C7641
R7600
22UF
C7680 1
C7681 1
20%
16V 2
X5R
1210
20%
16V 2
X5R
1210
22UF
10
20%
2 16V
X5R
1210
5%
1/16W
MF-LF
2 402
22UF
D
R76231
931
C7623
0.1uF
1%
1/16W
MF-LF
402 2
7
FDC796N
SUPERSOT-6
S
5
C7624
20%
10V
2 CERM
402
CRITICAL
0.1uF
4.7uH
2
SM5
CRITICAL
Q7621
P5VS5_SW
SW1
P5VS5_BG
BG1
10%
2 25V
X7R
402
10%
50V
CERM 2
402
1000pF
62 5
U7600
LTC3728LXC
P1V5S0_BOOST
17
15
P1V5S0_SW
BG2 18
P1V5S0_BG
SW2
QFN
P5VP1V5_FSEL
PLLFLTR 2
30 SENSE1+
12
SENSE2+
11
SENSE2-
SENSE1-
P5VS5_VOSNS
1 VOSENSE1
P5VS5_ITH
P5VS5_RUNSS
BOOST2
VOSENSE2
28 RUN_SS1
4 FCB
47pF
470pF
21 EXTVCC
10%
50V
CERM 2
402
5%
2 50V
CERM
402
10%
2 50V
CERM
402
10K
R7625
C7628
22K
1000pF
1%
1/16W
MF-LF
402 2
0.1uF
5%
1/16W
MF-LF
2 402
10%
2 25V
X7R
402
C7630
NO STUFF
SGND
P5VS5_ITH_RC
<Rb>
R76281
P1V5S0_VOSNS
10%
2 50V
CERM
402
20%
2 10V
CERM
402
CRITICAL
7 8
C7662
IRF7832PBF
C7665 C7666 1
470pF
<Ra>
R7667
34.0K
470pF
1%
1/16W
MF-LF
2 402
10%
50V
CERM 2
402
5%
50V
CERM 2
402
20%
6.3V 2
CERM
805
C7667 1
100pF
10%
2 50V
CERM
402
330uF
22UF
1
1 2
C7692
20%
2 2.5V-ESR9V
POLY
CASE-D2E-LF
C7691
SO-8
NO STUFF
C7661
20%
6.3V
2 CERM
805
Q7661
4
C7690
22UF
10%
25V
X7R 2
402
NC
NC
NC
NC
NC3 29
NC4 32
L7660
1000pF
NC2 16
CRITICAL
2.2uH-14A
5 63
Vout = 1.49V
8A max output
(L7660 & Q7660 limit)
1
2
IHLP2525CZ-SM
NC
NC1 10
0.001uF
INTVCC 20
PGND
470pF
1%
1/16W
MF-LF
402 2
PGOOD 27
C7626 C7625 1
THRML_PAD
=PP1V5_S0_REG
FDC796N
SUPERSOT-6
0.1uF
20%
10V
CERM 2
402
1%
1/16W
MF-LF
402 2
CRITICAL
P1V5S0_SNS_R_P
P1V5S0_SNS_R_N
P1V5S0_ITH_RC
C7670 1
R76651
20%
10V
CERM 2
402
5%
1/16W
MF-LF
402 2
<Rb>
R7668
NO STUFF
C7668 1
10K
0.1uF
19
52.3K
C7627
33
C7664
0.1uF
10%
16V
2 X5R
402
58
P1V5S0_RUNSS
RUN_SS2 13
3_3VOUT 7
<Ra>
R76271
Q7660
G
1
P1V5S0_ITH
ITH2 8
ITH1
P1V5S0_TG
TG2 14
CRITICAL
PLLIN
P5VS5_SNS_P
P5VS5_SNS_N
0.001uF
C7621
D7621
B240-X-F
SMB
1
2
22UF
20%
2 6.3V
CERM
805
C7622
NO STUFF
C7651
CRITICAL
FDC796N
SUPERSOT-6
TG1
CRITICAL
D
C7660
1.21K
5%
1/16W
MF-LF
2 402
R76691
R7664
5%
1/16W
MF-LF
402 2
BOOST1
NC
P5VS5_BOOST
20%
6.3V
CERM 2
805
150uF
20%
6.3V 2
POLY
SMC-LF
22UF
C7650 1
26
P5VS5_TG
C7652 1
1
1M
VIN
1%
1/16W
MF-LF
402 2
P1V5S0_BOOST_RC
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402 2
Q7620
L7620
1M
3.65K
R76701
R7630
CRITICAL
1%
1/16W
MF-LF
2 402
R76241
R76601
CMDSH-3
10%
2 16V
X5R
603
P5VS5_BOOST_RC
1.21K
D7664
SOD-323
1uF
R7629
C7600
CMDSH-3
1%
1/16W
MF-LF
2 402
CRITICAL
1%
1/16W
MF-LF
2 402
58
3.92K
10%
16V
X5R 2
402
Vout = 4.98V
8A max output
(L7620 limit)
909
CRITICAL
R7620
D7624
SOD-323
1
1
0.1uF
PP5V_S5_P5VP1V5_INTVCC
PPVIN_S5_P5VP1V5_R
VOLTAGE=12V
1
C7620
=PP5V_S5_REG
R7663
0.1uF
10%
16V
X5R 2
402
CRITICAL
63
C7663 1
10%
16V
2 X5R
402
58
39.2K
1000pF
1%
1/16W
MF-LF
2 402
10%
25V 2
X7R
402
GND_P5VP1V5_SGND
VOLTAGE=0V
XW7600
SM
C7607
0.01uF
Connect to RUNSS pins to control outputs.

If unconnected, powers up with VIN.
NOTE: Be aware of pull-ups to VIN on these signals.
10%
2 16V
CERM
402
=P5VP1V5_PGOOD
VOLTAGE=5V
P5VP1V5_SKIP
Vout = 0.8V * (1 + Ra / Rb)

62
58
R7606
C7601 1
5%
1/16W
MF-LF
2 402
R7603
4.7uF
20%
6.3V 2
CERM
603
P5VP1V5_FCB
30K
5%
1/16W
MF-LF
2 402
P5VP1V5_FSEL
63
=PP5V_S5_P5VP1V5_VCC
5%
1/16W
MF-LF
2 402
10%
6.3V 2
CERM
402
1uF
10%
6.3V
2 CERM
402
1K
C7604
0.01uF
5%
1/16W
MF-LF
2 402
10%
2 16V
CERM
402
Q7615
FDC638P
FDC638P
SM-LF
=PP5V_S3_FET
SM-LF
=PP5V_S0_FET
63
C7602
R7604
5V S0 FET
Q7610
=PP5V_S3_P5VS3
1uF
63
R7607
C7605 1
5V S3 FET
58
P5VP1V5_CONT
63
5
4
5V / 1.5V Power Supply
63
=PP5V_S0_P5VS0
5
4
C7616
22UF
20%
6.3V
CERM 2
805
R7610
62
=P5VS3_EN_L
100K 2
C7610
0.0022uF
1
P5VS3_EN_L_RC
5%
1/16W
MF-LF
402
10%
50V
CERM
402
62
=P5VS0_EN_L
100K 2
C7615
0.0022uF
R7615
P5VS0_EN_L_RC
5%
1/16W
MF-LF
402
10%
50V
CERM
402

1
C7617
22UF
20%
2 6.3V
CERM
805
SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
SYNC_DATE=(MASTER)
76
OF
D
104
2.5V S3 Regulator
D
63
=PPVIN_S3_P2V5S3
R7700
1
10
39
R77011
1M
C7701
2.5V S0 FET
SVIN PVIN
10%
2 6.3V
CERM
402
5
62
10UF
20%
2 6.3V
X5R
603
1uF
5%
1/16W
MF-LF
402 2
C7700
PPVIN_S3_P2V5S3_SVIN
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
CRITICAL
U7700
L7700
LTC3411
MIN_NECK_WIDTH=0.25 mm 2.2uH-1.32A
4
1
2
P2V5S3_SW
CDRH4D18-SM
9
P2V5S3_VFB
MSOP-LF
P2V5S3_SHDNRT
P2V5S3_MODE
=P2V5S3_PGOOD
SW
SHDN/RT
SYNC/MODE VFB
PGOOD
PGND
5
ITH 10 P2V5S3_ITH
SGND
3
R77061
CRITICAL
4.99K
R7705
324K
1%
1/16W
MF-LF
2 402
C7704
0.0033uF
GND_P2V5S3_SGND
39
=PP2V5_S0_P2V5S0
SI3446DV
1
=PP2V5_S0_FET
63
TSOP-LF
C7720
0.0022uF
3
4
R7720
R7708
62
4.7K
=P2V5S0_EN
C7709
100K 2
P2V5S0_EN_RC
5%
1/16W
MF-LF
402
22UF
1%
1/16W
MF-LF
2 402
100pF
5%
50V
CERM 2
402
63
<Rb>
C7703 1
10%
50V
2 CERM
402
Q7720
63
10%
50V
CERM 2
402
1M
5%
1/16W
MF-LF
402 2
R7707
1%
1/16W
MF-LF
2 402
5%
50V
CERM 2
402
P2V5S3_ITH_RC
R77041
<Ra>
1
10K
22pF
1%
1/16W
MF-LF
402 2
Continuous
Mode
C7706 1
=PP2V5_S3_REG
Vout = 2.52V
1.25A max output
(Switcher limit)
20%
2 6.3V
CERM
805
XW7700
SM
1
VOLTAGE=0V
=P2V5S3_EN_L
Vout = 0.8V * (1 + Ra / Rb)
1.2V S3 Regulator
=PPVIN_S3_P1V2S3
5%
1/16W
MF-LF
402 2
P1V2S3_RUNSS
Connect RUNSS off-page to control
If unconnected, powers up with PVIN.
NOTE: Be aware of pull-up on this signal.
P1V2S3_ITH_RC
1
C7753
0.0022uF
10%
2 50V
CERM
402
C7754 1
22pF
5%
50V
CERM 2
402
5
7
RT
RUN/SS
P1V2S3_ITH
P1V2S3_MODE
3
6
ITH
SYNC/MODE
R7756
0
PGOOD 2
C7757 1
470pF
10%
50V
CERM 2
402
VFB
10
11
14
15
CRITICAL
L7750
P1V2S3_SW
1%
1/16W
MF-LF
402 2
C7755 1
22UF
1 C7750
20%
6.3V 2
22pF
5%
50V
2 CERM
402
CERM
805
=PP1V2_S0_P1V2S0
SI3446DV
1
=PP1V2_S0_FET
63
TSOP-LF
C7770 1
0.0022uF
10%
50V
CERM 2
402
R7770
22UF
62
=P1V2S0_EN
100K 2
P1V2S0_EN_RC
5%
1/16W
MF-LF
402
VOLTAGE=0V
63
C7756
20%
2 6.3V
CERM
805
XW7750
SM
1
63
Vout = 1.205V
2.5A max output
(Switcher limit)
SM-LF
47.0K
309K
=PP1V2_S3_REG
<Ra>
R77501
R7754
GND_P1V2S3_SGND
Q7770
1.0UH-3.48A
1%
1/16W
MF-LF
2 402
1.2V S0 FET
=P1V2S3_PGOOD 62
THERM
SGND PGND PAD
5%
1/16W
MF-LF
2 402
20%
2 6.3V
CERM
805
TSSOP-LF
P1V2S3_RT
Burst
1%
1/16W
MF-LF
402 2
9
16
LTC3412
C7752
22UF
20%
6.3V 2
CERM
805
U7750
22UF
SW
R77531
8.25K
C7751 1
SVIN PVIN
5%
1/16W
MF-LF
2 402
39 5
CRITICAL
R7755
17
1M
NO STUFF
1
12
13
R77571
Continuous
63
P1V2S3_VFB
<Rb>
R77511
61.9K
1%
1/16W
MF-LF
402 2
P1V2S3_VFB_DIV
<Rc>
R77521
30.9K
1%
1/16W
MF-LF
402 2
2.5V & 1.2V Regulators

Vout = 0.8V * (1 + Ra / (Rb + Rc))
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
77
OF
D
104
1.8V S3 Current Sense

P1V8ISENS_NTC
1
63
63
22UF
C7801 1
1uF
10%
16V 2
X5R
603
R7802
2.2UF
20%
6.3V
CERM1 2
603
5%
1/16W
MF-LF
2 402
R7809
C
62
12
PVCC
20%
6.3V
CERM1 2
603
U7800
P1V8S3_FSET
=P1V8S3_EN
4
3
16
5
=P1V8S3_PGOOD
5
C7806 1
0.01UF
10%
16V
CERM 2
402
P1V8S3_COMP
R7808
1%
1/16W
MF-LF
2 402
64.9K
1%
1/16W
MF-LF
2 402
C7807 1
P1V8S3_FB
BOOT 13
PHASE 15
ISEN 9
EN
FCCM
PGOOD
COMP
1%
1/16W
MF-LF
402 2
1 2 3
5%
1/16W
MF-LF
2 402
PGND 10
20.0K2
L7820
1.0uH-20.5
P1V8S3_LG
Q7821
C7822
LFPAK
1000pF
CRITICAL
C7821
10%
25V
2 X7R
402
1 2 3
20.0K2
1uF
U7895
LMV2011MF
SOT23-5
P1V8S3_IOUT
R7892
1
1M
Placement Note:
C7892
1%
1/16W
MF-LF
402
NC
470pF
2
Keep C7890, R7890,

R7894 and R7897
close to inductor
10%
50V
CERM
402
=PP1V8_S3_REG
<Rb>
R78221
1.62K
1%
1/16W
MF-LF
402 2
B340LBXF
1
51
OUT
P1V8ISENS_POS
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402 2
D7820
SMB
1000pF
10%
25V
X7R 2
402
P1V8ISENS_NEG
C7895
10%
2 6.3V
CERM
402
1%
1/16W
MF-LF
402
R7891
1 2 3
NO STUFF
HAT2165H
3.32K
LFPAK
Q7822
1M
<Ra>
R78211
HAT2165H
10%
50V
CERM
402
CRITICAL
NO STUFF
1%
1/16W
MF-LF
402
C7808 1
GND_P1V8S3_SGND
C7890
SM1
3.01K2
1%
1/16W
MF-LF
402
XW7800
SM
R7893
CRITICAL
R7810
P1V8S3_ISEN
10%
50V
CERM 2
402
1%
1/16W
MF-LF
402
SWITCH_NODE=TRUE
0.0022uF
R78901
649
CRITICAL
R7805
1K
P1V8ISENS_RC
HAT2168H
P1V8S3_COMP_R
1
R7898
10%
6.3V
CERM
402
P1V8S3_PHASE
THRML
PAD
17
R7894
Q7820
2
2
1uF
20%
2 16V
X5R
1210
LFPAK
8 VO
5%
50V
CERM 2
402
22UF
P1V8S3_BOOT
6 FB
15PF
C7833
CRITICAL
4
UG 14
LG 11
1
57.6K
20%
2 6.3V
X5R
402
QFN
CRITICAL
R7806
C7832
20%
2 16V
X5R
1210
C7809
P1V8S3_UG
7 FSET
P1V8S3_FCCM
62
0.22uF
5%
1/16W
MF-LF
402 2
2
VCC
ISL6269
1 VIN
0
2.2UF
5%
1/16W
MF-LF
402 2
NO STUFF
P1V8S3_BOOT_R
470pF
0603-LF
PP5V_S3_P1V8S3_VCC
R78041
C7831
C7898
10KOHM-5%
20%
16V
2 X5R
1210
22UF
C7802 1
1%
1/16W
MF-LF
402 2
22UF
20%
16V
2 X5R
1210
NO STUFF
C7800 1
VOLTAGE=5V
NO STUFF
C7830
=PP3V3R5V_S3_P1V8ISENS
R7897
1K
1
63
CRITICAL
R78961
=PP5V_S3_P1V8S3
=PPVIN_S3_P1V8S3
R7820
C7840 1
C7842 1
20%
6.3V 2
CERM
805
20%
2.5V-ESR9V 2
POLY
CASE-D2E-LF
22UF
5%
1/16W
MF-LF
2 402
5 51 63
Vout = 1.83V
17A max output
(Q7820 limit)
NO STUFF
330uF
P1V8S3_FB_RC
NO STUFF
C7820 1
0.0022uF
10%
50V
CERM 2
402
(P1V8S3_FB)
C7841
22UF
C7843
330uF
20%
2 6.3V
CERM
805
20%
2 2.5V-ESR9V
POLY
CASE-D2E-LF
Vout = 0.6V * (1 + Ra / Rb)
1.8V S0 FET
Q7845
FDC796N
SUPERSOT-6
63
=PP1V8_S0_P1V8S0
=PPBUS_S0_P1V8S0
=PP1V8_S0_FET
63
63
3
2
R7846
0.0022uF
470K
5%
1/16W
MF-LF
402 2
62
=P1V8S0_EN
C7845
R7845
1
10%
2 50V
CERM
402
P1V8S0_EN_RC
C7846 1
22UF
20%
6.3V 2
CERM
805
C7847
22UF
20%
2 6.3V
CERM
805
1.8V Supply
5%
1/16W
MF-LF
402
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
78
OF
D
104
7
Q7947
3.3V S0 FET
63
SM-LF
=PP3V3_S0_FET
63
63
=PP3V3_S0_P3V3S0
3.3V S5 Regulator
=PP5V_S5_P3V3S5
=PPVIN_S5_P3V3S5
Q7945
C7901 1
PP5V_S5_P3V3S5_VCC
R7909
VOLTAGE=5V
R7904
20%
6.3V
CERM1 2
603
5%
1/16W
MF-LF
2 402
R7949
62
=P3V3S5_EN
P3V3S5_FSET
4
3
16
5
=P3V3S5_PGOOD
P3V3S5_COMP
C7906 1
R7908
1%
1/16W
MF-LF
2 402
10%
16V
CERM 2
402
C7907
51.1K
P3V3S5_FB
6 FB
470pF
1%
1/16W
MF-LF
2 402
10%
50V
CERM 2
402
R7905
0
5%
1/16W
MF-LF
2 402
C7908 1
0.022uF
CRITICAL
L7920
<Ra>
R79211
1000pF
10%
25V
X7R 2
402
CRITICAL
D7920
SMB
<Rb>
R79221
MBRS140XXG
C7942
150uF
20%
2 6.3V
POLY
SMC-LF
5%
1/16W
MF-LF
402
732
22UF
20%
2 6.3V
CERM
805
R7920
GND_P3V3S5_SGND
C7940
C7941 1
22UF
20%
6.3V 2
CERM
805
1%
1/16W
MF-LF
402 2
XW7900
SM
63
Vout = 3.32V
4.5A max output
(L7920 limit)
P3V3S5_FB_RC
FDC796N
SUPERSOT-6
10%
2 25V
CERM
402
Q7921
C7920
0.0047uF
1%
1/16W
MF-LF
402 2
CRITICAL
4
C7921
3.32K
NO STUFF
C7949
10%
50V
CERM
402
=PP3V3_S5_REG
3.01K2
P3V3S5_LG
20%
2 16V
CERM
402
P3V3S3_EN_L_RC
0.01uF
10%
16V
CERM-X5R 2
402
FDC796N
SUPERSOT-6
R7910
NO STUFF
100K 2
5%
1/16W
MF-LF
402
IHLP
1%
1/16W
MF-LF
402
P3V3S5_COMP_R
4.7uH
PGND 10
THRML
PAD
17
=P3V3S3_EN_L
P3V3S5_ISEN
8 VO
62
Q7920
P3V3S5_PHASE
SWITCH_NODE=TRUE
LG 11
57.6K
0.01UF
CRITICAL
D
C7945
0.0022uF
R7945
P3V3S5_BOOT
R7906
20%
6.3V
2 X5R
402
BOOT 13
PHASE 15
ISEN 9
EN
FCCM
PGOOD
COMP
D
3
0.22uF
UG 14
7 FSET
20%
16V
2 X5R
1210
C7909
QFN
CRITICAL
22UF
P3V3S5_UG
ISL6269
P3V3S5_EN_RC
P3V3S5_FCCM
5
2
VCC
U7900
1 VIN
5%
1/16W
MF-LF
402
48
12
PVCC
2.2UF
C7930
C7902 1
NO STUFF
5%
1/16W
MF-LF
402 2
63
5
4
10%
25V
CERM
402
5%
1/16W
MF-LF
402
P3V3S0_EN_L_RC
P3V3S5_BOOT_R
=P3V3S0_EN_L
=PP3V3_S3_FET
6
=PP3V3_S3_P3V3S3
63
5%
1/16W
MF-LF
2 402
0.0047uF
R7947
62
C7947
SM-LF
R7902
20%
6.3V
CERM1 2
603
FDC638P
2.2UF
C7900
10%
16V 2
X5R
603
NO STUFF
1uF
3.3V S3 FET
5
4
100K 2
1
63
FDC638P
Vout = 0.6V * (1 + Ra / Rb)
1.05V Current Sense

C7980
P1V05ISENS_NTC
22UF
63
63
20%
16V
X5R 2
1210
1.05V S0 Regulator
=PP5V_S0_P1V05S0
=PPVIN_S0_P1V05S0
10%
16V 2
X5R
603
R7952
2.2UF
20%
6.3V
CERM1 2
603
R7959
=P1V05S0_EN
P1V05S0_FCCM
=P1V05S0_PGOOD
5
C7956 1
0.01UF
10%
16V
CERM 2
402
P1V05S0_COMP
P1V05S0_UG
ISL6269
4
3
16
5
CRITICAL
BOOT 13
PHASE 15
ISEN 9
LG 11
R7956
57.6K
R7958
1%
1/16W
MF-LF
2 402
30.9K
1%
1/16W
MF-LF
2 402
C7957 1
15PF
5%
50V
CERM 2
402
P1V05S0_FB
6 FB
SWITCH_NODE=TRUE
P1V05S0_ISEN
5%
1/16W
MF-LF
2 402
649
1%
1/16W
MF-LF
402 2
8 VO
2.8K 2
P1V05S0_LG
6 7
Q7971
IRF7832PBF
SO-8
1
2 3
1000pF
1M
C7995
1uF
10%
6.3V
2 CERM
402
1%
1/16W
MF-LF
402
P1V05ISENS_NEG
U7995
LMV2011MF
SOT23-5
1
P1V05S0_IOUT
OUT
51
R7991
CRITICAL
NC
L7970 3
1.53uH
20.0K2
P1V05ISENS_POS
1%
1/16W
MF-LF
402
R7992
1M
Placement Note:
C7992
1%
1/16W
MF-LF
402
470pF
2
Keep C7990, R7990,

R7994 and R7997
close to inductor
10%
50V
CERM
402
=PP1V05_S0_REG
<Ra>
R79711
3.32K
NO STUFF
1
R7970
1%
1/16W
MF-LF
402 2
C7985
22UF
5%
1/16W
MF-LF
2 402
20%
2 6.3V
CERM
805
P1V05S0_FB_RC
NO STUFF
C7970 1
C7986 1
(P1V05S0_FB)
20%
6.3V 2
CERM
805
10%
50V
CERM 2
402
5 51 63
Vout = 1.05V
10A max output
(Q7970 & L7970 limit)
1
C7989
330uF
20%
2 2.5V-ESR9V
POLY
CASE-D2E-LF
0.0022uF
4.42K
XW7950
SM
GND_P1V05S0_SGND
1%
1/16W
MF-LF
402
20.0K2
<Rb>
R79721
10%
25V 2
X7R
402
20%
16V
CERM 2
402
C7990
1%
1/16W
MF-LF
402 2
NO STUFF
10%
50V
CERM
402
CRITICAL
4
0.01uF
R7993
SM
R7960
1%
1/16W
MF-LF
402
C7958 1
1%
1/16W
MF-LF
402
C7971 1
R7955
R79901
P1V05S0_PHASE
P1V05S0_COMP_R
1
FDC796N
SUPERSOT-6
PGND 10
THRML
PAD
17
Q7970
UG 14
EN
FCCM
PGOOD
COMP
D
G
P1V05S0_BOOT
1K
P1V05ISENS_RC
7 FSET
R7998
1uF
CRITICAL
4
R7994
QFN
2
2
10%
6.3V
CERM
402
P1V05S0_FSET
20%
6.3V
2 X5R
402
62
U7950
1 VIN
0.22uF
5%
1/16W
MF-LF
402 2
2
VCC
C7959
5%
1/16W
MF-LF
2 402
C7982
20%
2 16V
X5R
1210
20%
6.3V
CERM1 2
603
62
12
PVCC
2.2UF
R7954
C7952 1
NO STUFF
22UF
VOLTAGE=5V
NO STUFF
470pF
0603-LF
P1V05S0_BOOT_R
C7998
10KOHM-5%
5%
1/16W
MF-LF
2 402
R7997
20%
2 16V
X5R
1210
NO STUFF
C7950 1
PP5V_S0_P1V05S0_VCC
C7981
22UF
1uF
1%
1/16W
MF-LF
402 2
63
CRITICAL
1K
C7951
R79961
22UF
3.3V / 1.05V Power Supplies

SYNC_DATE=(MASTER)
Vout = 0.6V * (1 + Ra / Rb)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
79
OF
D
104
Power Control Signals

63 62
State
3.425V "G3Hot" Supply
=PP5V_S5_PWRCTL
SMC_PM_G2_ENABLE
PM_SLP_S4_L
PM_SLP_S3_L
1
1
1
0
1
1
0
0
1
0
0
0
Run (S0)
Sleep (S3)
Supply needs to guarantee 3.31V delivered to SMC VRef generator
Soft-Off (S5)
R80501 R80511
10K
5%
1/16W
MF-LF
402 2
66
IN
R8052
10K
10K
5%
1/16W
MF-LF
402 2
63
5%
1/16W
MF-LF
2 402
Battery Off (G3Hot)
=PPVIN_G3H_P3V42G3H
P3V42G3H5_BOOST
GPU requires 1.2V, 1.8V, 2.5V and

3.3V rise after VCore is up.
C8000 1
=GPUVCORE_PGOOD
PM_SLP_S3_LS5V_L
Need to ensure that

ISL6269 PGOOD does not
deassert while GPU
PowerPlay is changing
GPU core voltage.
=P2V5S0_EN
=P1V2S0_EN
MAKE_BASE=TRUE
P3V3S0_EN_L
=P3V3S0_EN_L
61
=P1V8S0_EN
60
MAKE_BASE=TRUE
P1V8S0_EN
MAKE_BASE=TRUE
6
Q8055
TSOT23-8
SHDN*
NC
NC
FB
L8010
33uH
=PP3V42_G3H_REG
1
2
CDPH4D19F-SM
SWITCH_NODE=TRUE
C8010 1
348K
22pF
1%
1/16W
MF-LF
2 402
5%
50V
CERM 2
402
4
5
<Rb>
R8011
SOT-363
PM_SLP_S3_LS5V
R8054
100K
SOT-363
27.4K
=P1V05S0_EN
=ENET_VMAIN_AVLBL
=MEMVREF_EN
=PBUSVSENS_EN
MAKE_BASE=TRUE
1%
1/16W
MF-LF
402 2
61
37
63 62
P1V5S0_COMP_POS
R8062
10K
GPUVCORE_EN
=GPUVCORE_EN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402 2
66
Ensure 1.2V and 2.5V S3 supplies are up

before enabling GPU VCore to support
removing ethernet power in battery sleep.
=PP5V_S5_PWRCTL
61
58
Q8055
IN
SOT-363
5%
1/16W
MF-LF
402 2
(PM_SLP_S4_L)
63
63
60
P5VS5_PGOOD
=P3V3S5_EN
(P5VS5_PGOOD)
MAKE_BASE=TRUE
P1V5P1V05S0_PGOOD
MAKE_BASE=TRUE
=PP3V3_S0_ALLSYSPG
R8059
470K
SMC_PM_G2_EN_L
R8075
100K
1%
1/16W
MF-LF
402 2
SOT-363
0.1uF
1
R8072
124K
20%
10V
CERM 2
402
V1
V2
U8070
7 V3
1%
1/16W
MF-LF
2 402
OUT
26 47
3 V4
LTC2908
LLP
CRITICAL
S0PGOOD_1V2_DIV
6 VADJ1
S0PGOOD_0V9_DIV
8 VADJ2
S0PGOOD_PWROK
LTC2908 sources 6uA at 5.0V
R8076 R8076 serves as pull-down
549K
and 3.3V level-shifter.
RST* 2
GND
R8073
THRML
PAD
9
1%
1/16W
MF-LF
2 402
100K
1%
1/16W
MF-LF
2 402
3.3V G3Hot Supply & Power Control

SYNC_DATE=(MASTER)
2N7002DW-X-F

LTC2908 threshold is 95% (4.75V, 3.135V, 2.375V, 1.71V, 1.14V, 0.86V)
SOT-363
ALL_SYS_PWRGD
0.1uF
Q8059
SC70
U8080 4
C8071
MC74VHC1G08
20%
2 10V
CERM
402
61
2N7002DW-X-F
C8070 1
1%
1/16W
MF-LF
402 2
Q8059
20%
10V
CERM 2
402
68.1K
5 45
5%
1/16W
MF-LF
2 402

R80581
63
0.1UF
R8074
44
P5VS5_RUNSS
5 58
5V Enable has pull-up to PBUS
57
C8080 1
PP5V_S0
PP3V3_S0
PP2V5_S0
PP1V8_S0
PP1V2_S0
PP0V9_S0
1
=PP3V42_G3H_PWRCTL
OUT
63
=P1V8S3_EN
=RTUSB_EN
LIO_P3V3S3_EN
MAKE_BASE=TRUE
SMC_PM_G2_EN
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
Other S0 Rails PWRGD Circuit
63
10K
10K
Reports when 5V S0, 3.3V S0, 2.5V S0, 1.8V S0, 1.2V S0 and 0.9V S0 are in regulation
63
2.5V S3 and 1.2V S3 supplies are controlled

by ethernet power control circuit.
100K
63 62
R8065
R8064
63
R80571
=P1V05S0_PGOOD
ISL6269 undervoltage threshold 81-87% (0.85 - 0.91V)
NOTE: R8065 acts as 10K pull-up for PGOOD signal
2N7002DW-X-F
IN
V-
B
=P3V3S3_EN_L
=P5VS3_EN_L
MAKE_BASE=TRUE
47
IMVP_PWRGD_IN
LMC7211
SM-LF
1
P1V5S0_PGOOD
1.5V Comp threshold set to 1.32V (88%)

61
PM_SLP_S4_LS5V
PM_SLP_S4_L
TP_P1V8S3_PGOOD
MAKE_BASE=TRUE
U8060
5
1
5%
1/16W
MF-LF
402 2
IN
4
V+
10K
48
P1V0_P1V5PG_REF
51
R80551
IN
1%
1/16W
MF-LF
2 402
0.89V Reference
32
5%
1/16W
MF-LF
2 402
NO STUFF
P2V5S3_P1V2S3_PGOOD
=P1V8S3_PGOOD
20%
10V
CERM 2
402
4.99K
10K
R8060
47 39 23
R8063
R8053
MAKE_BASE=TRUE
TP_P5V_P1V5_PGOOD
0.1uF
=P2V5S3_PGOOD
=P1V2S3_PGOOD
=P5VP1V5_PGOOD
MAKE_BASE=TRUE
R80611
(PM_SLP_S3_L)
IN
PP1V5_S0
58
C8060 1
5%
1/16W
MF-LF
402 2
IN
63
SOT-363
100K
59
=PP3V3_S5_P1V5PG
2N7002DW-X-F
R80561
59
63
60
Q8057
PM_SLP_S3_L
Unused PGOOD Signals
Reports when 1.5V S0 and 1.05V S0 are in regulation
2N7002DW-X-F
PM_SLP_S3
D
IN
1.5V / 1.05V PWRGD Circuit
Q8057
47 41 23
5 45
5%
1/16W
MF-LF
2 402
SOT-363
Vout = 1.25V * (1 + Ra / Rb)
58
P1V5S0_RUNSS
5 58
1.5V Enable has pull-up to PBUS
Q8050
2N7002DW-X-F
=P5VS0_EN_L
LIO_P3V3S0_EN_L
MAKE_BASE=TRUE
3
20%
2 6.3V
CERM
805
1%
1/16W
MF-LF
2 402
=PP3V42_G3H_PWRCTL
C8015
200K
63 62
22UF
P3V42G3H_FB
2N7002DW-X-F
63
Vout = 3.425
200mA max output
(Switcher limit)
<Ra>
R8010
GND
4
Q8050
CRITICAL
P3V42G3H_SW
5
7
CRITICAL
SOT-363
SW
BIAS
2N7002DW-X-F
SOT-363
20%
6.3V 2
X5R
402
LT3470
1.8V Enable has pull-up to PBUS
0.22uF
U8000
Q8056
2N7002DW-X-F
10%
25V 2
X5R
1206
59
C8005 1
6
BOOST
3
VIN
10uF
59
100K
5%
1/16W
MF-LF
402 2
SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
80
OF
D
104
PP3V42_G3H
PP0V9_S0
31
=PP0V9_S0_MEMVTT_LDO
62
=PP0V9_S0_MEM_TERM
=PP3V42_G3H_REG
30
PP1V05_S0
VOLTAGE=1.05V
MAKE_BASE=TRUE
61 51 5
=PP1V05_S0_REG
=PP1V05_S0_CPU
=PP1V05_S0_FSB_NB
=PP1V05_S0_NB_CRT
=PP1V05_S0_NB_VTT
=PP1V05_S0_SB_CPU_IO
=PPVCORE_S0_NB
=PPVCORE_S0_SB
7 8 9 11
12 19 34
19
17 19
=PP1V2_S3_ENET
=PP1V2_S0_P1V2S0
=PP3V3_S5_REG
37
59
PP1V2_S0
62
VOLTAGE=1.2V
MAKE_BASE=TRUE
=PP1V2_S0_FET
=PP1V2_S0_GPU_VDDPLL
=PP1V2_S0_PCIE_GPU
=PP1V2_S0_PCIE_GPU_PVDD
=PP1V2_S0_PCIE_GPU_VDDR
72
65
65
65
PP1V5_S0
=PP1V5_S0_REG
61
=PP3V3_S3_FET
8 9
19
19
19
13 19
19
19
16 17 19
17 19
25
24 25
24 25
=PP1V8_S3_MEM
=PP1V8_S3_MEM_NB
=PP1V8_S3_MEMVREF
=PP1V8_S0_MEMVTT
=PP1V8_S0_P1V8S0
24 25
5 45
61
=PP3V3_S0_FET
14 16 19
32
31
60
62
VOLTAGE=1.8V
MAKE_BASE=TRUE
60
=PP1V8_S0_FET
=PP1V8R2V0_S0_FB_GPU
=PP1V8_S0_FB_VDD
=PP1V8_S0_FB_VDDQ
67 68
70 71
70 71
PP2V5_S3
VOLTAGE=2.5V
MAKE_BASE=TRUE
59
=PP2V5_S3_REG
=PP2V5_S3_ENET
=PP2V5_S0_P2V5S0
37
59
PP2V5_S0
62
VOLTAGE=0
MAKE_BASE=TRUE
59
=PP2V5_S0_FET
=PP2V5_S0_GPU
=PP2V5_S0_GPU_PVDD
=PP2V5_S0_GPU_VDD25
=PP2V5_S0_GPU_VDDC_CT
17 19
73
72
72
72
PPVCORE_S0_GPU
VOLTAGE=1.2V
MAKE_BASE=TRUE
66
=PPVCORE_S0_GPU_REG
=PPVCORE_S0_GPU
=PPVCORE_S0_GPU_BBP
51 67 72
=PP3V3_S0_GPU
=PP3V3_S0_GPUBBP
=PP3V3_S0_GPUBBN
=PP3V3_S0_GPU_VDDR3
=PP3V3_S0_GPU_GPIOS
=PP1V8R3V3_S0_GPU_VDDR4
PPDCIN_G3H
=PPDCIN_G3H_LIO
=PP3V3_S0_DDC_DVI
=PP3V3_S0_DDC_LCD
=PP3V3_S0_CK410
=PP3V3_S0_IDE
=PP3V3_S0_IMVP6
=PP3V3_S0_INVERTER
=PP3V3_S0_NB
=PP3V3_S0_NB_VCC_HV
=PP3V3_S0_SB
=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_PCI
=PP3V3_S0_SB_PM
=PP3V3_S0_SB_VCC3_3
=PP3V3_S0_SB_VCCLAN3_3
=PP3V3_S0_TPM
=PP3V3_S0_VGASYNC
=PP3V3_S0_KBDLED
=PP3V3_S0_THRM_SNR
=PP3V3_S0_GPUTHMSNS
=PP3V3_S0_RSTHMSNS
=PP3V3_S0_SMBUS_SB
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_SMC_BSB
=PP3V3_S0_RSTBUF
=PP3V3_S0_SMC_LS
=PP3V3_S0_ALLSYSPG
=PP3V3_S0_FAN_LT
=PP3V3_S0_FAN_RT
=PP3V3_S0_FWISENS
=PP3V3R5V_S0_CPUISENS
=PP3V3R5V_S0_GPUISENS
=PPSPD_S0_MEM
=PPVIN_G3H_P3V42G3H
62
GND
VOLTAGE=0V
PNBB_S0_GPU
5 45
51
66
=PNVOUT_S0_GPUBBN_REG
=PNBB_S0_GPU
47 48
PPBB_S0_GPU
5 49
VOLTAGE=1.9V
MAKE_BASE=TRUE
66
=PPVOUT_S0_GPUBBP_LDO
=PPBB_S0_GPU
67
PPVCORE_S0_CPU
23 25
24
VOLTAGE=1.1V
MAKE_BASE=TRUE
22
11 23 26
22
57
=PPVOUT_S0_IMVP6_REG
=PPVCORE_S0_CPU
8 9 51
PPBUS_G3H
51
24 25
24 25
VOLTAGE=12.6V
MAKE_BASE=TRUE
52
62
42
64 5
=PPBUS_G3H_LIO_CONN
=PPBUS_G3H_S3AC
=PPVIN_S5_P5VP1V5
=PPVIN_S0_IMVP6
=PPVIN_S5_P3V3S5
=PPBUS_S5_FWPWRSW
=PPVIN_S3_P1V8S3
=PPVIN_S0_P1V05S0
=PPVIN_S0_GPUVCORE
=PPBUS_S0_INVERTER
=PPBUS_S0_P1V8S0
61
59
74
61
39
53
39
58
57
61
41
60
61
66
74
60
27
PPBUS_S5_FW_FET
48 56
76
43
VOLTAGE=33V
MAKE_BASE=TRUE
48 55
41
=PPBUS_S5_FW_FET
=PPFW_PORT1
42
PP5V_S5
48
5 76
32
VOLTAGE=5V
MAKE_BASE=TRUE
40
40
60
58
=PP5V_S5_REG
=PP5V_S5_SB
=PP5V_S5_P3V3S5
=PP5V_S5_P5VP1V5_VCC
=PP5V_S5_LIO
=PP5V_S5_PWRCTL
=PP5V_S3_P5VS3
=PP5V_S3_P1V8S3
=PP5V_S3_RTUSB
=PP5V_S0_P5VS0
=PP5V_S0_GPUVCORE
=PP5V_S0_P1V05S0
59
62
75
74
33 34
36
57
25
61
58
5 45
62
58
60
44
58
66
61
74
14 19 20
PP5V_S3
VOLTAGE=5V
MAKE_BASE=TRUE
17 19
22 25
24 25
58
=PP5V_S3_FET
=PP5V_S3_SYSLED
=PP5V_S3_CAMERA
=PP5V_S3_IR
=PP5V_S3_TOPCASE
21 23
26
26
48
5 43
76
43
24 25
24 25
PP5V_S0
62
VOLTAGE=5V
MAKE_BASE=TRUE
24 25
24 25
56
58
=PP5V_S0_FET
=PP5V_S0_DVI_DDC
=PP5V_S0_IDE
=PP5V_S0_HDD
=PP5V_S0_IMVP6
=PP5V_S0_INVERTER
=PP5V_S0_MEMVTT
=PP5V_S0_SB
=PP5V_S0_FAN_LT
=PP5V_S0_FAN_RT
=PP5V_S0_KBDLED
=PP5V_S0_GPUBBCTL
=PP5V_S0_LPCPLUS
=PP5V_S0_AUDIO_XW
=PP5V_S0_ISENSECAL
75
53
10
50
50
27
27
27
27
26
48
62
54
75
36
76
57
74
31
25
5 54
54
53
66
5 49
45
5 51
54
41
57
66
61
28 29
Power Aliases
66 69 72
SYNC_DATE=(MASTER)
66
66
72

69
72

72

APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
67
43
SIZE
37
VOLTAGE=-0.7V
MAKE_BASE=TRUE
35
66
VOLTAGE=18.5V
MAKE_BASE=TRUE
45 5
=PP3V3_S3_P3V3S3AC
=PP3V3_S3_RTALS
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_TPM
=PP3V3_S3_SMS
=PP3V3_S3_BT
=PP3V3_S3_TOPCASE
=PP3V3_S3_LTALS
=PP3V3_S3_MEMVREF
=PP3V3_S3_FW
=PP3V3_S3_PCI
=PPVIN_S3_P1V2S3
VOLTAGE=3.3V
MAKE_BASE=TRUE
24 25
28 29
PP1V8_S0
=PP3V3_S5_SB
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA
=PP3V3_S5_SB_IO
=PP3V3_S5_SB_PM
=PP3V3_S5_SB_USB
=PP3V3_S5_ROM
=PP3V3_S5_P1V5PG
=PP3V3_S5_FWLATEVG
=PP3V3_S3_P3V3S3
=PPVIN_S3_P2V5S3
=PP3V3_S0_LCD
=PP3V3_S0_P3V3S0
PP3V3_S0
24 25
PP1V8_S3
=PP1V8_S3_REG
=PP3V3_S3_ENET
24 25
VOLTAGE=1.8V
MAKE_BASE=TRUE
60 51 5
=PP3V3_S3AC_FET
48
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
62
=PP1V5_S0_CPU
=PP1V5_S0_NB
=PP1V5_S0_NB_3G
=PP1V5_S0_NB_3GPLL
=PP1V5_S0_NB_PCIE
=PP1V5_S0_NB_PLL
=PP1V5_S0_NB_TVDAC
=PP1V5_S0_NB_VCCAUX
=PP1V5_S0_SB
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCCSATAPLL
=PP1V5_S0_SB_VCCUSBPLL
=PP1V5_S0_LIO
39
26
PP3V3_S3
VOLTAGE=0
MAKE_BASE=TRUE
58 5
62
VOLTAGE=3.3V
MAKE_BASE=TRUE
24 25
PP1V2_S3
59
27
PP3V3_S5
16 19
VOLTAGE=1.2V
MAKE_BASE=TRUE
=PP1V2_S3_REG
PP3V3_S3AC
VOLTAGE=3.3V
MAKE_BASE=TRUE
48
21 24 25
61
59
=PP3V42_G3H_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SB_RTC
=PP3V42_G3H_SMC_PWRGD
=PP3V42_G3H_SMC_CLK
=PP3V42_G3H_LIO
=PP3V42_G3H_PBUSVSENS
=PP3V42_G3H_LIDSWITCH
=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
"S3AC" rail is ON in S3 on AC, OFF in S3 on battery
VOLTAGE=3.425V
MAKE_BASE=TRUE
62
VOLTAGE=0.9V
MAKE_BASE=TRUE
81
OF
D
104
Left I/O Power Connector

CRITICAL
J8200
87438
M-RT-SM
=PPBUS_G3H_LIO_CONN
5 63
1
2
3
4
5
6
518S0368
Battery Connector (Digital Signals)

CRITICAL
J8250
SM-2MT-LF
5
1
2
3
4
6
NC
5
27
5
27
5
NC
GND_BATT
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SMC_BS_ALRT_L
IO
IO
OUT
R8250
10
518S0293
5%
1/16W
MF-LF
2 402
PBus-In & Battery Connectors

SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
82
OF
D
104
OMIT
U8400
M56P
BGA
(1 OF 7)
13
IN
C8420
PEG_R2D_C_P<0>
0.1uF
2
10% 16V X5R 402
13
IN
C8421
PEG_R2D_C_N<0>
0.1uF
PEG_R2D_P<0>
PEG_R2D_N<0>
AJ31
AH31
PCIE_TX0P
PCIE_TX0N
PCIE_RX0P
PCIE_RX0N
AK27
AJ27
PEG_D2R_C_P<0>
PEG_D2R_C_N<0>
IN
C8422
PEG_R2D_C_P<1>
0.1uF
2
10% 16V X5R 402
13
IN
C8423
PEG_R2D_C_N<1>
0.1uF
PEG_R2D_P<1>
PEG_R2D_N<1>
AH30
AG30
PCIE_TX1P
PCIE_TX1N
PCIE_RX1P
PCIE_RX1N
PEG_R2D_C_P<2>
C8424
13
IN
PEG_R2D_C_N<2>
C8425
0.1uF
2
10% 16V X5R 402
0.1uF
IN
C8426
PEG_R2D_C_P<3>
0.1uF
IN
C8427
PEG_R2D_C_N<3>
0.1uF
PEG_R2D_P<2>
PEG_R2D_N<2>
AG32
AF32
C8428
PEG_R2D_C_P<4>
0.1uF
IN
C8429
PEG_R2D_C_N<4>
0.1uF
PEG_R2D_P<3>
PEG_R2D_N<3>
AF31
AE31
PCIE_RX3P
PCIE_RX3N
PEG_R2D_P<4>
PEG_R2D_N<4>
AE30
AD30
PCIE_RX4P
PCIE_RX4N
2
10% 16V X5R 402
13
IN
C8430
PEG_R2D_C_P<5>
0.1uF
2
10% 16V X5R 402
13
IN
C8431
PEG_R2D_C_N<5>
0.1uF
PEG_R2D_P<5>
PEG_R2D_N<5>
AD32
AC32
PCIE_RX5P
PCIE_RX5N
2
10% 16V X5R 402
13
IN
C8432
PEG_R2D_C_P<6>
0.1uF
2
10% 16V X5R 402
13 IN
C8433
PEG_R2D_C_N<6>
0.1uF
AJ25
AH25
PEG_D2R_C_P<1>
PEG_D2R_C_N<1>
AH28
AG28
PEG_D2R_C_P<2>
PEG_D2R_C_N<2>
PEG_R2D_P<6>
PEG_R2D_N<6>
AC31
AB31
PCIE_RX6P
PCIE_RX6N
PCIE_TX3P
PCIE_TX3N
AG27
AF27
PEG_D2R_C_P<3>
PEG_D2R_C_N<3>
63
=PP1V2_S0_PCIE_GPU_VDDR
=PP1V2_S0_PCIE_GPU_PVDD
13
IN
13
IN
C8435
PEG_R2D_C_N<7>
0.1uF
PCIE_TX4P
PCIE_TX4N
AF25
AE25
PEG_D2R_C_P<4>
PEG_D2R_C_N<4>
PCIE_TX5P
PCIE_TX5N
AE28
AD28
PEG_D2R_C_P<5>
PEG_D2R_C_N<5>
PEG_R2D_C_P<8>
C8436
0.1uF
IN
13
PEG_R2D_C_N<8>
C8437
0.1uF
IN
13
BGA
(2 OF 7)
OMIT
PCIE_PVDD_12
(1.2V)
N23
P23
U23
V23
C8402 1 C8401
1uF
10%
6.3V
CERM 2
402
PCI EXPRESS POWER & GROUND
PCIE_VDDR_12
(1.2V)
PCIE_VSS
PCIE_PVSS
C8438
PEG_R2D_C_P<9>
1uF
10%
6.3V
CERM 2
402
C8400
0.1uF
2
10% 16V X5R 402
VOLTAGE=1.2V
13
PCIE_TX6P
PCIE_TX6N
AD27
AC27
PEG_D2R_C_P<6>
PEG_D2R_C_N<6>
IN
C8439
PEG_R2D_C_N<9>
0.1uF
22UF
20%
6.3V
2 CERM
805
13
IN
PEG_R2D_C_P<10>
C8440
0.1uF
PEG_R2D_C_N<10>
C8441
0.1uF
PEG_R2D_P<7>
PEG_R2D_N<7>
AB30
AA30
PCIE_RX7P
PCIE_RX7N
PCIE_TX7P
PCIE_TX7N
AC25
AB25
PEG_D2R_C_P<7>
PEG_D2R_C_N<7>
C8407 1 C8406
1uF
1uF
10%
6.3V
CERM 2
402
10%
6.3V
CERM 2
402
13 IN
C8405
PEG_R2D_C_P<11>
C8442
0.1uF
20%
6.3V
2 CERM
805
13
IN
PEG_R2D_C_N<11>
C8443
0.1uF
PEG_R2D_P<8>
PEG_R2D_N<8>
AA32
Y32
PCIE_RX8P
PCIE_RX8N
PCIE_TX8P
PCIE_TX8N
AB28
AA28
PEG_D2R_C_P<8>
PEG_D2R_C_N<8>
IN
PEG_R2D_C_P<12>
C8444
0.1uF
10% 16V X5R 402
C8413 1 C8412
1uF
1uF
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
C8411
1uF
10%
6.3V 2
CERM
402
13
C8410
IN
PEG_R2D_C_N<12>
C8445
0.1uF
20%
2 6.3V
CERM
805
13
IN
PEG_R2D_C_P<13>
C8446
0.1uF
2
10% 16V X5R 402
13 IN
PEG_R2D_C_N<13>
C8447
0.1uF
Y31
W31
PCIE_RX9P
PCIE_RX9N
PCIE_TX9P
PCIE_TX9N
AA27
Y27
PEG_D2R_C_P<9>
PEG_D2R_C_N<9>
13
IN
N24
N30
P24
P25
P26
P28
P29
P30
R23
R24
R25
R26
R29
R31
T24
T26
T27
T29
U24
U26
U28
U29
U30
V24
V25
V26
V29
V31
W24
W26
13
IN
PEG_R2D_P<10>
PEG_R2D_N<10>
W30
V30
PCIE_RX10P
PCIE_RX10N
PCIE_TX10P
PCIE_TX10N
Y25
W25
PEG_D2R_C_P<10>
PEG_D2R_C_N<10>
C8448
0.1uF
PEG_R2D_C_N<14>
C8449
0.1uF
IN
PEG_R2D_C_P<15>
C8450
0.1uF
2
10% 16V X5R 402
13
IN
PEG_R2D_C_N<15>
C8451
0.1uF
C8462
0.1uF
IN
34 IN
13
PEG_D2R_N<2>
OUT
13
PEG_D2R_P<3>
OUT
13
PEG_D2R_N<3>
OUT
13
PEG_D2R_P<4>
OUT
13
PEG_D2R_N<4>
OUT
13
PEG_D2R_P<5>
OUT
13
PEG_D2R_N<5>
OUT
13
PEG_D2R_P<6>
OUT
13
PEG_D2R_N<6>
OUT
13
PEG_D2R_P<7>
OUT
13
PEG_D2R_N<7>
OUT
13
PEG_D2R_P<8>
OUT
13
PEG_D2R_N<8>
OUT
13
PEG_D2R_P<9>
OUT
13
PEG_D2R_N<9>
OUT
13
PEG_D2R_P<10>
OUT
13
PEG_D2R_N<10>
OUT
13
PEG_D2R_P<11>
OUT
13
PEG_D2R_N<11>
OUT
13
PEG_D2R_P<12>
OUT
13
PEG_D2R_N<12>
OUT
13
PEG_D2R_P<13>
OUT
13
PEG_D2R_N<13>
OUT
13
PEG_D2R_P<14>
OUT
13
PEG_D2R_N<14>
OUT
13
PEG_D2R_P<15>
OUT
13
PEG_D2R_N<15>
OUT
C8463
0.1uF
C8464
0.1uF
C8465
0.1uF
C8466
0.1uF
C8467
0.1uF
C8468
0.1uF
C8469
0.1uF
C8470
0.1uF
C8471
0.1uF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
C8472
0.1uF
C8473
0.1uF
C8474
0.1uF
C8475
0.1uF
C8476
0.1uF
10% 16V X5R 402
10% 16V X5R 402
PEG_R2D_P<11>
PEG_R2D_N<11>
V32
U32
PCIE_RX11P
PCIE_RX11N
PCIE_TX11P
PCIE_TX11N
W28
V28
PEG_D2R_C_P<11>
PEG_D2R_C_N<11>
C8477
0.1uF
C8478
0.1uF
C8479
0.1uF
C8480
0.1uF
C8481
0.1uF
C8482
0.1uF
C8483
0.1uF
C8484
0.1uF
10% 16V X5R 402
10% 16V X5R 402
PEG_R2D_P<12>
PEG_R2D_N<12>
U31
T31
PCIE_RX12P
PCIE_RX12N
PCIE_TX12P
PCIE_TX12N
V27
U27
PEG_D2R_C_P<12>
PEG_D2R_C_N<12>
10% 16V X5R 402
10% 16V X5R 402
PEG_R2D_P<13>
PEG_R2D_N<13>
T30
R30
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
U25
T25
PEG_D2R_C_P<13>
PEG_D2R_C_N<13>
10% 16V X5R 402
10% 16V X5R 402
PEG_R2D_P<14>
PEG_R2D_N<14>
R32
P32
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
T28
R28
PEG_D2R_C_P<14>
PEG_D2R_C_N<14>
10% 16V X5R 402

1
2
10% 16V X5R 402
PEG_R2D_P<15>
PEG_R2D_N<15>
P31
N31
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
R27
P27
PEG_D2R_C_P<15>
PEG_D2R_C_N<15>
C8485
0.1uF
C8486
0.1uF
10% 16V X5R 402
10% 16V X5R 402
=PP1V2_S0_PCIE_GPU
PEG_CLK100M_GPU_P
PEG_CLK100M_GPU_N
AL28
AK28
PCIE_REFCLKP
PCIE_REFCLKN
63
R8495
2.0K
26
IN
PEG_RESET_L
NC
AG24
AF24
PERST*
PERST*_MASK
AA24
PCIE_TEST
PCIE_CALRP
PCIE_CALRN
AD24
AE24
GPU_PCIE_CALRP
GPU_PCIE_CALRN
PCIE_CALI
AB24
GPU_PCIE_CALI
R84971
1.47K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
R8496
562
1%
1/16W
MF-LF
2 402
ATI M56 PCI-E

SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
10% 16V X5R 402
10% 16V X5R 402

34
OUT
10% 16V X5R 402
10% 16V X5R 402

13
0.1uF
PEG_R2D_C_P<14>
PEG_D2R_P<2>
10% 16V X5R 402
10% 16V X5R 402
W23
C8461
10% 16V X5R 402
PCIE_VSS
PEG_R2D_P<9>
PEG_R2D_N<9>
10% 16V X5R 402
22UF
13
10% 16V X5R 402
10% 16V X5R 402

13
OUT
10% 16V X5R 402
10% 16V X5R 402
22UF
C8460
0.1uF
OUT
PEG_D2R_N<1>
10% 16V X5R 402
10% 16V X5R 402
2000mA
10% 16V X5R 402

IN
PEG_D2R_P<1>
13
10% 16V X5R 402
10% 16V X5R 402
13
N25
N26
N27
N28
N29
AL29
AL30
AL31
AL32
AM27
AM28
AM29
AM30
AM31
IN
PP1V2_S0_PCIE_GPU_PVDD_F
100mA
0.1uF
13
10% 16V X5R 402
13
M56P
C8459
OUT
10% 16V X5R 402
10% 16V X5R 402
U8400
W27
W29
Y24
Y26
Y28
Y29
Y30
AA23
AA25
AA26
AA29
AA31
AB23
AB26
AB27
AB29
AC23
AC24
AC26
AC28
AC29
AC30
AD25
AD26
AD29
AD31
AE26
AE27
AE29
AF26
AF28
AF29
AF30
AG25
AG26
AG29
AG31
AH24
AH26
AH27
AH29
AJ26
AJ28
AJ29
AJ30
AJ32
AK26
AK29
AK30
AK31
AK32
AL27
10% 16V X5R 402
0402
PEG_D2R_N<0>
10% 16V X5R 402
10% 16V X5R 402
L8400
0.1uF
10% 16V X5R 402
200-OHM-EMI
C8434
PEG_R2D_C_P<7>
0.1uF
OUT
13
10% 16V X5R 402
10% 16V X5R 402

63
C8458
PEG_D2R_P<0>
10% 16V X5R 402
10% 16V X5R 402

13
PCIE_TX2P
PCIE_TX2N
PCIE_RX2P
PCIE_RX2N
10% 16V X5R 402

13 IN
C8457
0.1uF
13
10% 16V X5R 402
10% 16V X5R 402

13
10% 16V X5R 402
10% 16V X5R 402

13
PCI-EXPRESS BUS INTERFACE
IN
0.1uF
10% 16V X5R 402
10% 16V X5R 402

13
0.1uF
C8456
2
10% 16V X5R 402
13
C8455
84
OF
D
104
GPU VCore Current Sense

GPUISENS_NTC
1
63
63
C8501
R8502
2.2UF
20%
6.3V
CERM1 2
603
5%
1/16W
MF-LF
2 402
R8509
12
PVCC
20%
6.3V
CERM1 2
603
U8500
GPUVCORE_FSET
4
3
16
5
=GPUVCORE_PGOOD
GPUVCORE_COMP
R8508
C8507
150K
C8506 1
0.01UF
10%
16V
CERM 2
402
R8506
1%
1/16W
MF-LF
2 402
FCCM
PGOOD
COMP
CRITICAL
649
GPUVCORE_LG
<Ra>
R85211
Q8521
10%
25V 2
X7R
402
LFPAK
CRITICAL
C8521
3.01K
1%
1/16W
MF-LF
402 2
GPUVCORE_IOUT
10%
2 25V
X7R
402
OUT
51
R8592
1M
C8592
1%
1/16W
MF-LF
402
470pF
2
10%
50V
CERM
402
R8520
20%
2.5V-ESR9V 2
POLY
CASE-D2E-LF
330uF
GPUVCORE_FB_RC
NO STUFF
C8520 1
0.0022uF
10%
50V
CERM 2
402
1%
1/16W
MF-LF
402 2
C8542 1
20%
6.3V 2
CERM
805
22UF
5%
1/16W
MF-LF
2 402
5.11K
B340LBXF
C8540 1
63
Vout = 1.10V / 0.95V

17A max output
(Q8520 limit)
NO STUFF
1
<Rb>
R85221
D8520
SMB
1000pF
1 2 3
SOT23-5
1
GPUISENS_POS
1 2 3
NO STUFF
=PPVCORE_S0_GPU_REG
LFPAK
1000pF
1uF
U8595
LMV2011MF
Keep C8590, R8590,

R8594 and R8597
close to inductor
HAT2165H
HAT2165H
Placement Note:
CRITICAL
Q8522
GPUISENS_NEG
C8595
10%
2 6.3V
CERM
402
C8522 1
L8520
1.0uH-20.5
NO STUFF
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
SM1
3.01K2
GND_GPUVCORE_SGND
20.0K2
CRITICAL
NC
1%
1/16W
MF-LF
402 2
1M
R8591
R85901
10%
50V
CERM
402
GPUISENS_RC
Q8520
1%
1/16W
MF-LF
402
XW8500
SM
10%
6.3V
CERM
402
10%
50V
CERM 2
402
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
1uF
R8510
PGND 10
470pF
C8590
20.0K2
GPUVCORE_ISEN
THRML
PAD
17
R8593
GPUVCORE_PHASE
SWITCH_NODE=TRUE
1K
1%
1/16W
MF-LF
402
20%
2 16V
X5R
1210
1 2 3
C8508 1
R8505
C8532
22UF
20%
2 16V
X5R
1210
CRITICAL
NO STUFF
1
22UF
HAT2168H
GPUVCORE_COMP_R
57.6K
8 VO
5%
50V
CERM 2
402
C8531
LFPAK
BOOT 13
PHASE 15
ISEN 9
EN
6 FB
15pF
1%
1/16W
MF-LF
2 402
GPUVCORE_FB
GPUVCORE_BOOT
LG 11
1
20%
2 6.3V
X5R
402
UG 14
7 FSET
=GPUVCORE_EN
0.22UF
QFN
1 VIN
C8530
20%
2 16V
X5R
1210
C8509
GPUVCORE_UG
ISL6269
GPUVCORE_FCCM
62
5%
1/16W
MF-LF
402 2
2
VCC
CRITICAL
62
22UF
2.2UF
R8598
GPUVCORE_BOOT_R
C8502 1
5%
1/16W
MF-LF
2 402
2
2
R8594
470pF
0603-LF
VOLTAGE=5V
R8504
C8598
10KOHM-5%
NO STUFF
C8500 1
PP5V_S0_GPUVCORE_VCC
1K
1%
1/16W
MF-LF
402 2
NO STUFF
10%
16V
X5R 2
603
=PP3V3R5V_S0_GPUISENS
R8597
1uF
63
CRITICAL
R85961
GPU VCore Supply
=PP5V_S0_GPUVCORE
=PPVIN_S0_GPUVCORE
C8541
22UF
330uF
20%
2 6.3V
CERM
805
(GPUVCORE_FB)
C8543
20%
2 2.5V-ESR9V
POLY
CASE-D2E-LF
<Rc>
R8523
12.4K2
Vout(low) = 0.6V * (1 + Ra / Rb)

Vout(high) = 0.6V * (1 + Ra / Req)
Req = Rb || Rc
Back-Bias Positive Supply

Back-bias positive supply provides VDDC + 0.5V when active.
When inactive, provides VDDC to BBP pins.
NOTE: BBP tracks VDDC based on GPU voltage GPIO.
63
Q8575
TSOP-LF
GPUBB_EN
2.2uF
24.9K
20%
6.3V
CERM1 2
603
GPUBBP_ADJ
NO STUFF
C8556 1
20%
6.3V 2
CERM
805
<Rb>
R8556
R8554
174K
16.2K
1%
1/16W
MF-LF
2 402
NO STUFF
Q8554
2N7002
66
GPU_VCORE_HIGH
SOT23-LF
63
C8557
Pull-up voltage must be high enough to

satisfy BBP FET Vgs (where Vs = 1.2V)
SI3446DV max Vgs is 1.6V
Vin must be > 2.8V
72
GPU_GENERICD
5%
1/16W
MF-LF
402
2N7002
66
66
GPUBB_EN
68.1K
GPUBBN_CAPP
1
66
SOT23-LF
1%
1/16W
MF-LF
402 2
8
4
SHDN_L
CAP+
C8581
IN
FB
OUT
Vout = -Vin * Rb / Ra
<Rb> Recommended values:
1
R8588
11.3K
Ra = Vin / 50 uA
1%
1/16W
MF-LF
Rb = -Vout / 50 uA
402
GPUBBN_FB
U8580
MAX1673
SOI
C8570
0.0022uF
10%
2 50V
CERM
402
CAP-
LIN/SKIP_L
GND
7
=PNVOUT_S0_GPUBBN_REG
1
C8589
20%
2 6.3V
CERM
805

10K
5%
1/16W
MF-LF
402 2
SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
SYNC_DATE=(MASTER)
63
Vout = -0.55V
125mA max output
(Regulator limit)
22UF
R85601
GPU (M56) Core Supplies
CRITICAL
GPUBBN_CAPN
Q8570
GPUBB_EN
<Ra>
R85871
20%
6.3V
2 CERM1
603
R8561
=PP3V3_S0_GPUBBN
2.2uF
GPUBB_EN_L
GPU_BB_CTL
SOT-363
Back-bias negative supply provides VSS - 0.55V when active.

When inactive, provides VSS to BBN pins.
5%
1/16W
MF-LF
402 2
10%
16V
CERM-X5R 2
402
Back-Bias Negative Supply
20%
6.3V 2
X5R
603
100K
10uF
R8570
SOT-363
0.022uF
Q8523
C8580 1
=PP5V_S0_GPUBBCTL
For proper M56 power sequence, this

pull-up must be powered before VCore
10K
Vout(low) = 0.59V * (1 + Ra/Rb)

Vout(high) = 0.59V * (1 + Ra/Req)
Req = Rb || Rc
C8523
5%
1/16W
MF-LF
402 2
63
R8524
20%
6.3V
2 CERM
805
GPUBBP_ADJ_LOW
GPU_VCORE_LOW
1
22UF
1%
1/16W
MF-LF
2 402
<Rc>
69
63
Vout = (1.58V /) 1.50V

180mA max output
(LDO limit)
22UF
1%
1/16W
MF-LF
2 402
10%
16V
CERM 2
402
2N7002DW-X-F
GPU_VCORE_HIGH_RC
2N7002DW-X-F
<Ra>
R8555
0.01UF
GND
2
C8551 1
5%
1/16W
MF-LF
402
3
D
C8555 1
10K
Q8523
R8525
1
=PPVOUT_S0_GPUBBP_LDO
SOT23-6-LF
1 VIN
VOUT 6
4 PG
3 EN
ADJ 5
GPU_VCORE_HIGH
U8550
66
66
FAN2558
=PP3V3_S0_GPUBBP
63
10K
5%
1/16W
MF-LF
402 2
GPUBB_EN_L
66
R85261
1
2
GPUVCORE_FB_LOW
1%
1/16W
MF-LF
402
=PP3V3_S0_GPU
SI3446DV
=PPVCORE_S0_GPU_BBP
CRITICAL
72 69 63
85
OF
D
104
Page Notes
- =PP1V5_GPU_VDD15
- =PP1VR1V3_GPU_VCORE
(NONE)
(NONE)
U8400
M56P
=PPBB_S0_GPU
C8690
BGA
(7 OF 7)
100mA (Preliminary)
22UF
20%
6.3V
CERM 2
805
72 63 51
=PPVCORE_S0_GPU
C8600
C8691
1uF
10%
6.3V
2 CERM
402
C8692
0.1uF
10%
16V
2 X5R
402
14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI

1
22UF
20%
6.3V
CERM 2
805
C8601 1
22UF
C8604
1uF
20%
6.3V
CERM 2
805
10%
6.3V
2 CERM
402
C8611
1uF
10%
6.3V
2 CERM
402
1uF
10%
6.3V
2 CERM
402
C8605
C8606
1uF
10%
6.3V
2 CERM
402
C8612
1uF
10%
6.3V
2 CERM
402
C8613
1uF
10%
6.3V
2 CERM
402
1uF
10%
6.3V
2 CERM
402
C8607
C8614
1uF
10%
6.3V
2 CERM
402
1uF
10%
6.3V
2 CERM
402
C8608
C8615
1uF
10%
6.3V
2 CERM
402
1uF
10%
6.3V
2 CERM
402
C8609
C8610
1uF
10%
6.3V
2 CERM
402
C8616
1uF
10%
6.3V
2 CERM
402
R86301
0
5%
1/10W
MF-LF
603 2
K18
M23
V10
AC14
OMIT
BBP
BBN
VDDC
(1.0V/1.2V)
PPVCORE_S0_GPU_VDDCI
VOLTAGE=1.2V
C8630 1
22UF
20%
6.3V
CERM 2
805
68 63
C8650
22UF
C8631
1uF
10%
6.3V
2 CERM
402
C8632
1uF
10%
6.3V
2 CERM
402
C8633
1uF
10%
6.3V
2 CERM
402
C8634
1uF
10%
6.3V
2 CERM
402
2.0A @ 500MHz 1.8V GDDR3

1
20%
6.3V 2
CERM
805
C8651
22UF
20%
6.3V 2
CERM
805
C8652
22UF
20%
6.3V 2
CERM
805
C8653
22UF
20%
6.3V 2
CERM
805
C8655
1uF
10%
2 6.3V
CERM
402
C8661
1uF
C8667
C8668
1uF
10%
6.3V
2 CERM
402
10%
6.3V
2 CERM
402
C8673
1uF
10%
6.3V
2 CERM
402
C8662
10%
6.3V
2 CERM
402
1uF
1uF
10%
6.3V
2 CERM
402
C8656
1uF
10%
2 6.3V
CERM
402
C8674
1uF
10%
6.3V
2 CERM
402
C8679
1uF
10%
6.3V
2 CERM
402
C8680
1uF
10%
6.3V
2 CERM
402
C8657
1uF
10%
2 6.3V
CERM
402
C8663
1uF
10%
6.3V
2 CERM
402
C8669
1uF
10%
6.3V
2 CERM
402
C8675
1uF
10%
6.3V
2 CERM
402
C8681
1uF
10%
6.3V
2 CERM
402
C8658
1uF
10%
2 6.3V
CERM
402
C8664
1uF
10%
6.3V
2 CERM
402
C8670
1uF
10%
6.3V
2 CERM
402
C8676
1uF
10%
6.3V
2 CERM
402
C8682
1uF
10%
6.3V
2 CERM
402
C8659
1uF
10%
2 6.3V
CERM
402
C8665
1uF
10%
6.3V
2 CERM
402
C8671
1uF
10%
6.3V
2 CERM
402
C8677
1uF
10%
6.3V
2 CERM
402
C8683
1uF
10%
6.3V
2 CERM
402
C8660
1uF
10%
2 6.3V
CERM
402
C8666
1uF
10%
6.3V
2 CERM
402
C8672
1uF
10%
6.3V
2 CERM
402
C8678
1uF
10%
6.3V
2 CERM
402
K15
R10
Y23
AC17
C8697
0.1uF
10%
16V 2
X5R
402
C8696 1
1uF
10%
6.3V 2
CERM
402
100mA (Preliminary)
P14
P18
P19
R15
R17
R18
R19
T16
T17
T18
U15
U16
U17
V14
V15
V16
V18
W14
W15
W19
AC11
AC12
AD11
MEMORY & CORE POWER / GROUND
63
K14
P16
T14
T23
U19
W10
W17
A3
A9
A12
A15
A18
A21
A24
A30
C1
C32
F32
H13
H19
J1
J10
J11
J13
J18
J19
J20
J32
K11
K13
K19
K20
K21
K24
L23
L24
L32
M1
M10
N9
N10
P8
P9
P10
R1
R9
V1
Y8
Y9
Y10
AA1
VDDCI
(1.0V/1.2V)
VSS
VDDR1
(1.8V/2.0V)
K23
A2
A8
A11
A13
A16
A19
A22
A25
A31
B1
B32
C4
C5
C6
C9
C10
C15
C18
C20
C21
C24
C27
D11
D30
E5
E8
E9
E12
E13
E16
E19
E25
E28
E30
E32
F3
F6
F10
F13
F15
F16
F18
F19
F21
F22
F24
F27
F30
G13
G16
G19
G20
G21
G22
G25
H1
H5
H7
H16
H20
H21
H28
H32
J3
J6
J9
J12
J16
J21
J24
J28
J30
K10
K12
K16
K17
K27
K30
L1
L6
L7
L29
M3
VSS
VSS
C8695
22UF
20%
2 6.3V
CERM
805
=PNBB_S0_GPU
63
M6
M7
M8
M9
M24
M28
M32
N3
N7
N8
P1
P5
P6
P7
P15
P17
R3
R6
R14
R16
T10
T15
T19
U1
U5
U6
U7
U8
U9
U10
U14
U18
V3
V6
V17
V19
W16
W18
Y1
Y5
Y6
Y7
AA4
AA6
AC9
AC10
AD6
AD7
AD8
AD9
AD10
AD13
AD14
AD15
AD16
AD17
AE8
AE14
AE15
AE16
AE17
AF14
AF16
AG11
AG16
AG23
AH10
AH11
AH16
AJ10
AK16
AL1
AL13
AM2
AM13
ATI M56 Core Power

SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
86
OF
D
104
Page Notes
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
B
1
R8710
R8712
40.2
40.2
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
68 67 63
IO
70
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
70
IO
FB_A_DQ<0>
FB_A_DQ<1>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<4>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<14>
FB_A_DQ<15>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<18>
FB_A_DQ<19>
FB_A_DQ<20>
FB_A_DQ<21>
FB_A_DQ<22>
FB_A_DQ<23>
FB_A_DQ<24>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<28>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<31>
FB_A_DQ<32>
FB_A_DQ<33>
FB_A_DQ<34>
FB_A_DQ<35>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<44>
FB_A_DQ<45>
FB_A_DQ<46>
FB_A_DQ<47>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<53>
FB_A_DQ<54>
FB_A_DQ<55>
FB_A_DQ<56>
FB_A_DQ<57>
FB_A_DQ<58>
FB_A_DQ<59>
FB_A_DQ<60>
FB_A_DQ<61>
FB_A_DQ<62>
FB_A_DQ<63>
GPU_MVREFD0
GPU_MVREFS0
R87111 C8711 1
100
R8713
100
0.1uF
1%
1/16W
MF-LF
402 2
C31
C30
A27
A28
C8713
0.1uF
1%
1/16W
MF-LF
2 402
10%
16V 2
X5R
402
M31
M30
L31
L30
H30
G31
G30
F31
M27
M29
L28
L27
J27
H29
G29
G27
M26
L26
M25
L25
J25
G28
H27
H26
F26
G26
H25
H24
H23
H22
J23
J22
E23
D22
D23
E22
E20
F20
D19
D18
B19
B18
C17
B17
C14
B14
C13
B13
D17
E18
E17
F17
E15
E14
F14
D13
H18
H17
G18
G17
G15
G14
H14
J14
M56P
M56P
BGA
(3 OF 7)
BGA
(4 OF 7)
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
MVREFD_0
MVREFS_0
(1.8V/
VDDRH0 2.0V)
VSSRH0
DQMA_0*
DQMA_1*
DQMA_2*
DQMA_3*
DQMA_4*
DQMA_5*
DQMA_6*
DQMA_7*
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
QSA_0*
QSA_1*
QSA_2*
QSA_3*
QSA_4*
QSA_5*
QSA_6*
QSA_7*
CLKA0
CLKA0*
CSA0_0*
CSA0_1*
D26
F28
D28
D25
E24
E26
D27
F25
C26
B26
D29
B27
E27
E29
B25
C25
H31
J29
J26
G23
E21
B15
D14
J17
70
70
70
70
70
70
70
70
70
70
70
70
69
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
K31
K28
K26
G24
D21
C16
D15
J15
70
70
70
70
70
70
70
70
D31
E31
B29
C28
OUT
OUT
70
70
70
IO
71
IO
71
IO
OUT
71
IO
OUT
71
IO
71
IO
OUT
IO
71
IO
OUT
71
IO
71
IO
OUT
71
IO
OUT
71
IO
OUT
71
IO
71
IO
71
IO
IO
71
IO
IO
71
IO
IO
71
IO
IO
71
IO
OUT
IO
IO
71
IO
71
IO
IO
71
IO
71
IO
FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>
IN
IO
IN
71
IO
IN
71
IO
IN
71
IO
IN
71
IO
IN
71
IO
IN
71
IO
IN
71
IO
71
IO
OUT
71
IO
OUT
71
IO
71
IO
OUT
71
IO
OUT
71
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
B30
70
FB_A_CKE<0>
OUT
B28
70
FB_A_RAS_L<0>
OUT
CASA0*
C29
70
FB_A_CAS_L<0>
OUT
WEA0*
B31
70
FB_A_WE_L<0>
OUT
CLKA1
CLKA1*
B20
C19
CSA1_0*
CSA1_1*
B23
C23
71
TP_FB_A_ODT<0>
70
70
70
FB_A_CLK_P<1>
FB_A_CLK_N<1>
FB_A_CS_L<1>
OUT
OUT
68 67 63
OUT
OUT
NC
R8720
R8722
40.2
CKEA1
C22
70
FB_A_CKE<1>
OUT
RASA1*
B24
70
FB_A_RAS_L<1>
OUT
CASA1*
B22
70
FB_A_CAS_L<1>
OUT
WEA1*
B21
70
FB_A_WE_L<1>
OUT
ODTA1
D24
TP_FB_A_ODT<1>
OUT
40.2
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
71
IO
GPU_MVREFD1
GPU_MVREFS1
R87211 C8721
100
R8723
100
0.1uF
1%
1/16W
MF-LF
402 2
10%
2 16V
X5R
402
FB_B_DQ<0>
FB_B_DQ<1>
FB_B_DQ<2>
FB_B_DQ<3>
FB_B_DQ<4>
FB_B_DQ<5>
FB_B_DQ<6>
FB_B_DQ<7>
FB_B_DQ<8>
FB_B_DQ<9>
FB_B_DQ<10>
FB_B_DQ<11>
FB_B_DQ<12>
FB_B_DQ<13>
FB_B_DQ<14>
FB_B_DQ<15>
FB_B_DQ<16>
FB_B_DQ<17>
FB_B_DQ<18>
FB_B_DQ<19>
FB_B_DQ<20>
FB_B_DQ<21>
FB_B_DQ<22>
FB_B_DQ<23>
FB_B_DQ<24>
FB_B_DQ<25>
FB_B_DQ<26>
FB_B_DQ<27>
FB_B_DQ<28>
FB_B_DQ<29>
FB_B_DQ<30>
FB_B_DQ<31>
FB_B_DQ<32>
FB_B_DQ<33>
FB_B_DQ<34>
FB_B_DQ<35>
FB_B_DQ<36>
FB_B_DQ<37>
FB_B_DQ<38>
FB_B_DQ<39>
FB_B_DQ<40>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<43>
FB_B_DQ<44>
FB_B_DQ<45>
FB_B_DQ<46>
FB_B_DQ<47>
FB_B_DQ<48>
FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<51>
FB_B_DQ<52>
FB_B_DQ<53>
FB_B_DQ<54>
FB_B_DQ<55>
FB_B_DQ<56>
FB_B_DQ<57>
FB_B_DQ<58>
FB_B_DQ<59>
FB_B_DQ<60>
FB_B_DQ<61>
FB_B_DQ<62>
FB_B_DQ<63>
IO
71
CKEA0
F29
IO
71
RASA0*
ODTA0
71
OUT
OUT
FB_A_CS_L<0>
IO
OUT
OUT
FB_A_CLK_P<0>
FB_A_CLK_N<0>
IO
71
OUT
OUT
FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>
FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>
71
71
FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>
FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>
70
J31
K29
K25
F23
D20
B16
D16
H15
FB_A_MA<0>
FB_A_MA<1>
FB_A_MA<2>
FB_A_MA<3>
FB_A_MA<4>
FB_A_MA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>
TP_FB_A_MA12
FB_A_BA<2>
FB_A_BA<0>
FB_A_BA<1>
1%
1/16W
MF-LF
2 402
10%
16V 2
X5R
402
PP1V8R2V0_S0_GPU_VDDRH1
C8723
0.1uF
10%
2 16V
X5R
402
GPU_TEST_MCLK
GPU_TEST_YCLK
GPU_MEMTEST
B12
C12
B11
C11
C8
B7
C7
B6
F12
D12
E11
F11
F9
D8
D7
F7
G12
G11
H12
H11
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
K9
L9
K5
L4
K4
L5
N5
N6
P4
R4
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
V7
W7
W8
W9
B3
C3
F1
E1
AA5
AA2
AA7
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
MVREFD_1
MVREFS_1
(1.8V/
VDDRH1 2.0V)
VSSRH1
TEST_MCLK
TEST_YCLK
MEMTEST
G4
E6
E4
H4
J5
G5
F4
H6
G3
G2
D4
F2
F5
D5
H2
H3
71
DQMB_0*
DQMB_1*
DQMB_2*
DQMB_3*
DQMB_4*
DQMB_5*
DQMB_6*
DQMB_7*
B8
D9
G9
K7
M5
V2
W4
T9
71
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
B9
D10
H10
K6
N4
U2
U4
V8
71
QSB_0*
QSB_1*
QSB_2*
QSB_3*
QSB_4*
QSB_5*
QSB_6*
QSB_7*
B10
E10
G10
J7
M4
U3
V4
V9
71
CLKB0
CLKB0*
B4
B5
71
71
FB_B_CLK_P<0>
FB_B_CLK_N<0>
CSB0_0*
CSB0_1*
D2
E3
71
FB_B_CS_L<0>
OUT
71
71
71
71
71
71
71
71
71
71
71
69
71
71
71
71
71
71
71
71
71
L8715
FERR-220-OHM
71
71
71
71
71
71
68 67 63
FERR-220-OHM
71
71
71
71
71
71
PP1V8R2V0_S0_GPU_VDDRH0
0402
XW8715
SM
0402
C8715 1 C8716
1
C8725 1
1uF
1uF
10%
6.3V
CERM 2
402
10%
6.3V
CERM 2
402
1uF
10%
6.3V
CERM 2
402
XW8725
SM
GND_GPU_VSSRH0
VOLTAGE=0V
C8726
1uF
10%
6.3V
CERM 2
402
R8730
4.7K
5%
1/16W
MF-LF
2 402
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
CKEB0
C2
71
FB_B_CKE<0>
OUT
RASB0*
E2
71
FB_B_RAS_L<0>
OUT
CASB0*
D3
71
FB_B_CAS_L<0>
OUT
WEB0*
B2
71
FB_B_WE_L<0>
OUT
ODTB0
D6
TP_FB_B_ODT<0>
OUT
CLKB1
CLKB1*
N2
P3
71
71
FB_B_CLK_P<1>
FB_B_CLK_N<1>
CSB1_0*
CSB1_1*
K2
K3
71
FB_B_CS_L<1>
OUT
OUT
OUT
NC
CKEB1
L3
71
FB_B_CKE<1>
OUT
RASB1*
J2
71
FB_B_RAS_L<1>
OUT
CASB1*
L2
71
FB_B_CAS_L<1>
OUT
WEB1*
M2
71
FB_B_WE_L<1>
OUT
ODTB1
J4
TP_FB_B_ODT<1>
OUT
FB_DRAM_RST
OUT
DRAM_RST
OUT
NC
AA3
71
70
R8733
4.7K
5%
1/16W
MF-LF
402 2
VOLTAGE=1.8V
OUT
FB_B_WDQS<0>
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_B_WDQS<4>
FB_B_WDQS<5>
FB_B_WDQS<6>
FB_B_WDQS<7>
71
4.7K
L8725
VOLTAGE=1.8V
OUT
FB_B_RDQS<0>
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_B_RDQS<4>
FB_B_RDQS<5>
FB_B_RDQS<6>
FB_B_RDQS<7>
71
R8731
OUT
FB_B_DQM_L<0>
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_B_DQM_L<4>
FB_B_DQM_L<5>
FB_B_DQM_L<6>
FB_B_DQM_L<7>
71
67 63
68
FB_B_MA<0>
FB_B_MA<1>
FB_B_MA<2>
FB_B_MA<3>
FB_B_MA<4>
FB_B_MA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>
TP_FB_B_MA12
FB_B_BA<2>
FB_B_BA<0>
FB_B_BA<1>
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15
MEMORY INTERFACE B
70
OMIT
U8400
READ STROBE

(NONE)
OMIT
WRITE STROBE

(NONE)
U8400
MEMORY INTERFACE A

- =PP1V8R2V0_S0_FB_GPU
READ STROBE
WRITE STROBE
5%
1/16W
MF-LF
2 402
1
R8732
243
1%
1/16W
MF-LF
2 402
ATI M56 Frame Buffer I/F
GND_GPU_VSSRH1
VOLTAGE=0V
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
87
OF
D
104
ROMCFGID[3..0]
63
0000
0010
0100
0110
=PP3V3_S0_GPU_GPIOS
NO STUFF
R88001
IPD
TESTIN[0]
TX_PWRS_ENb
TESTIN[1]
TX_DEEMPH_EN
72
GPU_GPIO_1
IPD
GPU_GPIO_2
TESTIN[2]
Reserved
72
72
GPU_GPIO_3
72
GPU_GPIO_4
72
GPU_MEM_256M
R88121
10K
10K
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
NO STUFF
1
R8803
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
NO STUFF
1
R8805
10K
5%
1/16W
MF-LF
2 402
R8808
10K
5%
1/16W
MF-LF
2 402
GPU_MEM_64M
1
R8813
NO STUFF
GPU_MEM_HYNIX
R8811
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R8827
10K
5%
1/16W
MF-LF
2 402
Renamed signals
34
VDD_VCL
GPU_CLK27M
GPU_XTALIN
Unused signals
TESTIN[3]
Reserved
DEBUG_ACCESS
NC_GPU_XTALOUT
GPU_GPIO_5
TESTIN[5]
Reserved
NC_ATI_ROMCS_L
GPU_GPIO_6
TESTIN[6]
Reserved
72
GPU_GPIO_7
ENA_BL
TESTIN[7]
72
TESTWR
72
GPU_GPIO_8
ROMSO
72
GPU_GPIO_9
72
GPU_GPIO_10
IPD
ROMSCK
MAKE_BASE=TRUE
TESTOUT[9]
ROMIDCFG[0]
72
GPU_GPIO_11
GPU_GPIO_12
IPD
TESTOUT[10]
ROMIDCFG[1]
72
TESTOUT[11]
ROMIDCFG[2]
72
GPU_GPIO_13
IPD
72
GPU_GPIO_14
72
GPU_GPIO_15
72
GPU_GPIO_16
72
GPU_GPIO_17
MAKE_BASE=TRUE
72
GPU_GPIO_18
72
GPU_GPIO_19
72
GPU_GPIO_20
72
GPU_GPIO_21
MAKE_BASE=TRUE
TESTIN[8]
TESTIN[9]
72
GPU_GPIO_23
72
GPU_GPIO_24
72
GPU_GPIO_25
MAKE_BASE=TRUE
NC_GPU_GPIO_14
MAKE_BASE=TRUE
PWRCNTL
GPU_VCORE_LOW
MAKE_BASE=TRUE
SS_IN
GPU_CLK27MSS_IN
MAKE_BASE=TRUE
Thm Mon Int
NC_GPU_GPIO_17
MAKE_BASE=TRUE
Required for debug access
NC_GPU_VGA_R
NC_GPU_VGA_G
MAKE_BASE=TRUE
72
GPU_GPIO_26
72
GPU_GPIO_27
72
GPU_GPIO_28
72
GPU_GPIO_29
72
GPU_GPIO_30
72
GPU_GPIO_31
72
GPU_GPIO_32
72
GPU_GPIO_33
72
GPU_GPIO_34
72
GPU_VGA_R
73
GPU_VGA_G
73
GPU_VGA_B
73
GPU_VGA_HSYNC
73
GPU_VGA_VSYNC
73
GPU_TV_Y
73
GPU_TV_C
73
GPU_TV_COMP
73
LVDS_U_DATA_P<3>
73
LVDS_U_DATA_N<3>
73
LVDS_L_DATA_P<3>
73
LVDS_L_DATA_N<3>
73
ATI_DVPCLK
72
ATI_DVPCNTL<2..0>
72
ATI_DVPDATA<15..0>
72
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
66
TP_GPU_VGA_HSYNC
34
TP_GPU_VGA_VSYNC
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_TV_Y
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_TV_COMP
NC_GPU_GPIO_19
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_20
NC_LVDS_U_DATAP<3>
NC_GPU_GPIO_21
NC_LVDS_U_DATAN<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_22
NC_LVDS_L_DATAP<3>
NC_GPU_GPIO_23
NC_LVDS_L_DATAN<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
GPU_MEM_256M
NO_TEST=TRUE
NC_ATI_DVPCLK
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_ATI_DVPCNTL<2..0>
MAKE_BASE=TRUE
NC_GPU_GPIO_26
NO_TEST=TRUE
NC_ATI_DVPDATA<15..0>
MAKE_BASE=TRUE
GPU_MEMID
NO_TEST=TRUE
NC_GPU_TV_C
NC_GPU_GPIO_25
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
72
GPU_GENERICC
NO_TEST=TRUE
NC_GPU_VGA_B
NC_GPU_GPIO_18
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
72
GPU_GENERICB
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
GPU_GENERICA
NO_TEST=TRUE
NC_GPU_GENERICC
68
NO_TEST=TRUE
NC_GPU_GENERICB
68
TP_FB_B_MA12
NO_TEST=TRUE
NC_GPU_GENERICA
MAKE_BASE=TRUE
GPU_GPIO_22
MAKE_BASE=TRUE
TP_GPU_GPIO_10
72
TP_FB_A_MA12
NO_TEST=TRUE
NC_FB_B_MA12
ROMIDCFG[3]
TESTOUT[8]
IPD
72
MAKE_BASE=TRUE
74
72
TP_ATI_ROMCS_L
NO_TEST=TRUE
NC_FB_A_MA12
GPU_BLON
MAKE_BASE=TRUE
GPU_XTALOUT
NO_TEST=TRUE
MAKE_BASE=TRUE
Reserved
ROMSI
72
MAKE_BASE=TRUE
TESTIN[4]
IPD
MAKE_BASE=TRUE
R88241
10K
Straps
GPU_GPIO_0
GPU_MEM_256M
5%
1/16W
MF-LF
402 2
10K
72
R88091
10K
R8801
Misc
NO STUFF
R88061
5%
1/16W
MF-LF
402 2
GPU_DEEPMH_EN
TestBus
NO STUFF
R88041
128MB
256MB
64MB
Reserved
10K
Serial ROM
NO STUFF
R88021
=
=
=
=
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_GPIO_28
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_29
NC_GPU_GPIO_30
TP_ATI_DVPDATA<23..16>
ATI_DVPDATA<23..16>
MAKE_BASE=TRUE
NC_GPU_GPIO_31
72
Also required: GPIO10 - GPIO13
NC_GPU_GPIO_32
NC_GPU_GPIO_33
NC_GPU_GPIO_34
72 66 63
=PP3V3_S0_GPU
R93901 R93911
4.7K
4.7K
5%
1/16W
MF-LF
402 2
73
73
5%
1/16W
MF-LF
402 2
GPU_DDC_B_CLK
GPU_DDC_B_DATA
GPU Straps
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
88
OF
D
104
C8903
0.1uF
10%
2 16V
X5R
402
C8904
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
M12 VDD5
V2 VDD6
V11 VDD7
L8910
FERR-220-OHM
1
PP1V8_S0_FB_A0_VDDA0
K1 VDDA0
K12 VDDA1
VOLTAGE=1.8V
0402
L8915
FERR-220-OHM
1
VOLTAGE=1.8V
0402
Connect to designated pin, then GND

71 70 63
IN
C8910
0.1uF
C8915
0.1uF
10%
2 16V
X5R
402
U8900.J12
10%
2 16V
X5R
402
U8900.J1
=PP1V8_S0_FB_VDDQ
C8920 1
22UF
20%
6.3V 2
CERM
805
C8921
0.1uF
C8922
0.1uF
C8923
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
(2 OF 2)
C8924
0.1uF
C8925
0.1uF
C8926
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4
C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9
R8930
2.37K
R8932
2.37K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
FB_A0_VREF0
V12
1
R8931
5.49K
R8933
R89421
121
R8941
1K
5%
1/16W
MF-LF
2 402
70 68
IN
70 68
IN
70 68
IN
70 68
IN
70 68
IN
70 68
IN
70 68
IN
70 68
IN
68
IN
68
IN
68
IN
68
IN
68
IN
68
IN
68
IN
121
R8945
60.4
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
121
68
68
68
68
68
68
IN
OUT
OUT
OUT
OUT
IN
IN
68
IN
68
IN
70 68
IN
70 68
70 68
IN
IN
68
N10
68
N3
68
DQ0
B2
B3
68
C2
68
FB_A_CKE<0>
FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_CS_L<0>
FB_A_WE_L<0>
FB_A_CAS_L<0>
FB_A_RAS_L<0>
H9
J11
CKE
J10
CK*
CS*
K2
M4
K11
L9
F4
H4
F9
H10
A4
A9
V4
V9
D3
D10
P10
P3
1%
1/16W
MF-LF
402 2
100
A7
A8/AP
A9
A10
A11
CK
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
WE*
CAS*
RAS*
DQ10
DQ11
DQ12
DQ13
DQ14
ZQ
MF
DQ15
DQ16
SEN
DQ17
RESET
DQ18
DQ19
RDQS0
RDQS1
RDQS2
RDQS3
DQ20
DQ21
DQ22
D2
WDQS0
D11
P11
WDQS1
DQ25
WDQS2
WDQS3
DQ26
DQ27
DQ28
G9
G4
NC
NC
A6
DQ23
DQ24
P2
FB_A_BA<0>
FB_A_BA<1>
FB_A_BA<2>
0.1uF
C8972
0.1uF
BA0
BA1
H3
BA2
J2
RFU1
RFU2
J3
DQ29
DQ30
DQ31
68
68
C3
E2
68
F3
68
F2
G3
68
B11
B10
68
C11
68
C10
E11
68
F10
68
F11
G10
68
M11
68
L10
N11
68
M10
R11
68
R10
68
68
68
68
68
68
68
68
T11
T10
68
M2
68
L3
N2
68
M3
68
R2
R3
68
T2
T3
68
68
68
68
68
C8973
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>
FB_A_DQ<0>
FB_A_DQ<1>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<4>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<15>
FB_A_DQ<14>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<19>
FB_A_DQ<16>
FB_A_DQ<18>
FB_A_DQ<17>
FB_A_DQ<23>
FB_A_DQ<21>
FB_A_DQ<20>
FB_A_DQ<22>
FB_A_DQ<24>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<28>
FB_A_DQ<31>
(2 OF 2)
C8974
0.1uF
10%
2 16V
X5R
402
C8975
0.1uF
C8976
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4
C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9
J4 VDDQ10
J9 VDDQ11
N1 VDDQ12
N4 VDDQ13
N9 VDDQ14
N12 VDDQ15
R8980
2.37K
R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20
R8982
2.37K
1%
1/16W
MF-LF
402 2
R89901
R89921
121
1%
1/16W
MF-LF
402 2
V12
R8991
IN
70 68
IN
IN
70 68
IN
IN
70 68
IN
IN
70 68
IN
70 68
IN
IO
IO
IO
IO
IO
IO
IO
70 68
IN
70 68
IN
70 68
IN
70 68
IN
70 68
IN
70 68
IN
70 68
IN
R89941
121
IO
IN
IO
68
IN
IO
68
IN
IO
68
IO
68
IN
IO
68
IN
IO
68
IN
IN
R8995
1%
1/16W
MF-LF
2 402
IO
IO
IO
68
68
68
68
OUT
OUT
OUT
OUT
68
IO
68
IO
68
IN
IO
68
IN
70 68
IN
IO
IO
IO
70 68
70 68
IN
IN
IN
IN
121
U8950
DM0
DM1
E3
E10
68
FBGA
A2
A3
(1 OF 2)
DM2
DM3
N10
68
N3
68
DQ0
B2
B3
68
C2
68
C3
E2
68
F3
68
F2
G3
68
FB_A_CKE<1>
FB_A_CLK_P<1>
FB_A_CLK_N<1>
FB_A_CS_L<1>
FB_A_WE_L<1>
FB_A_CAS_L<1>
FB_A_RAS_L<1>
H9
J11
CKE
B11
B10
68
J10
CK*
CS*
C11
68
C10
E11
68
F10
68
F11
G10
68
M11
68
L10
N11
68
M10
R11
68
R10
68
T11
T10
68
M2
68
L3
N2
68
M3
68
R2
R3
68
T2
T3
68
M9
K4
H2
K3
L4
K2
M4
K11
L9
A4
A5
A6
A7
A8/AP
A9
A10
A11
F4
H4
F9
H10
A4
A9
V4
V9
FB_DRAM_RST
FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>
D3
D10
P10
P3
FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>
243
1%
1/16W
MF-LF
402 2
R8999
100
NC
NC
DQ4
DQ5
DQ6
CK
DQ9
DQ10
DQ11
WE*
CAS*
RAS*
DQ12
DQ13
DQ14
ZQ
MF
DQ15
DQ16
SEN
DQ17
RESET
DQ18
DQ19
RDQS0
RDQS1
DQ20
DQ21
DQ22
RDQS2
RDQS3
D2
WDQS0
D11
P11
WDQS1
DQ25
WDQS2
WDQS3
DQ26
DQ27
DQ28
G9
G4
DQ3
DQ23
DQ24
P2
FB_A_BA<0>
FB_A_BA<1>
FB_A_BA<2>
DQ1
DQ2
DQ7
DQ8
BA0
BA1
H3
BA2
J2
RFU1
RFU2
DQ29
DQ30
DQ31
IO
5%
1/16W
MF-LF
2 402
VSSQ1
VSSQ2
B4
B9
VSSQ3
B12
VSSQ4
VSSQ5
D1
D4
VSSQ6
VSSQ7
D9
VSSQ8
D12
G2
VSSQ9
VSSQ10
G11
L2
VSSQ11
L11
VSSQ12
VSSQ13
P1
P4
VSSQ14
P9
VSSQ15
VSSQ16
P12
T1
VSSQ17
VSSQ18
T4
T9
T12
CRITICAL
OMIT
1%
1/16W
MF-LF
2 402
A1
R8998
B1
A0
VSSQ0
R8997
IO
IO
J1
J12
10%
2 16V
X5R
402
K10
IO
IO
VSSA1
VSSA0

(NONE)
V10
VDDQ21
K9
H11
IO
IN
V3
VSSQ19
FB_A_MA<0>
FB_A_MA<1>
FB_A_MA<2>
FB_A_MA<3>
FB_A_MA<4>
FB_A_MA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>
IO
IO
VSS6
VSS7

(NONE)
FB_A1_ZQ
FB_A1_MF
FB_A1_SEN
71 70 68
L1
L12
C8983
IO
68
G12
VSS4
VSS5
1%
1/16W
MF-LF
402 2
60.4
1%
1/16W
MF-LF
2 402
VSS3
60.4
1%
1/16W
MF-LF
402 2
R8993
A10
G1
R89961
121
A3
VSS1
VSS2
0.1uF
10%
2 16V
X5R
402
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
C8981
0.1uF
5.49K
VSS0

- =PP1V8_S0_FB_VDD
- =PP1V8_S0_FB_VDDQ
H1 VREF0
H12 VREF1
R8983
121
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
E3
E10
FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>
C8971
1K
DM2
DM3
FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
5.49K
DM1
243
20%
6.3V 2
CERM
805
R8981
DM0
R8949
22UF
FB_A1_VREF1
FBGA
R8948
C8970 1
U8900
K3
L4
10%
2 16V
X5R
402
U8900.J12
=PP1V8_S0_FB_VDDQ
(1 OF 2)
IN
C8965
0.1uF
10%
2 16V
X5R
402
U8900.J1
FB_A1_VREF0
A2
A3

71 70 63
C8960
0.1uF
VOLTAGE=1.8V
0402
FBGA
M12 VDD5
V2 VDD6
V11 VDD7
A1
FB_DRAM_RST
VDDQ21
A0
H2
10%
2 16V
X5R
402
U8950
K1 VDDA0
K12 VDDA1
VSSQ18 T9
VSSQ19 T12
K10
FB_A0_ZQ
FB_A0_MF
FB_A0_SEN
71 70 68
VSSQ15 P12
VSSQ16 T1
VSSQ17 T4
K9
H11
A4
A5
C8954
0.1uF
10%
2 16V
X5R
402
FERR-220-OHM
VSSQ12 P1
VSSQ13 P4
VSSQ14 P9
FB_A_MA<0>
FB_A_MA<1>
FB_A_MA<2>
FB_A_MA<3>
FB_A_MA<4>
FB_A_MA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>
M9
K4
10%
2 16V
X5R
402
L8965
VSSQ0 B1
VSSQ1 B4
VSSQ2 B9
CRITICAL
OMIT
1%
1/16W
MF-LF
2 402
0.1uF
VOLTAGE=1.8V
1%
1/16W
MF-LF
402 2
K4J52324QC-BC20
IN
R8943
C8953
0402
NOTE: U8900 DQ0-7 MUST connect to GPU

DQA0-7 or DQA8-15. Bits can be swapped
within byte-lane, but software must know
how these bits are mapped for GPU to support
GDDR3 vendor/device identification scheme.
1
R8947
MFHIGH
IN
70 68
1%
1/16W
MF-LF
402 2
10%
2 16V
X5R
402
16MX32-GDDR3-500MHZ
IN
70 68
60.4
1%
1/16W
MF-LF
402 2
FERR-220-OHM
VSSA0 J1
VSSA1 J12
0.1uF
MFHIGH
IN
70 68
R89461
121
C8952
L8960
C8933
MFHIGH
70 68
R89441
1%
1/16W
MF-LF
402 2
10%
2 16V
X5R
402
1%
1/16W
MF-LF
402 2
121
1%
1/16W
MF-LF
402 2
C8931
0.1uF
5.49K
1%
1/16W
MF-LF
402 2
R89401
0.1uF
10%
2 16V
X5R
402
H1 VREF0
H12 VREF1
FB_A0_VREF1
VSS6 V3
VSS7 V10
VSSQ9 G11
VSSQ10 L2
VSSQ11 L11
J4 VDDQ10
J9 VDDQ11
N1 VDDQ12
0.1uF
20%
6.3V
CERM 2
805
VSSQ6 D9
VSSQ7 D12
VSSQ8 G2
R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20
VSS3 G12
VSS4 L1
VSS5 L12
C8951
22UF
VSSQ3 B12
VSSQ4 D1
VSSQ5 D4
N4 VDDQ13
N9 VDDQ14
N12 VDDQ15
C8950 1
A2 VDD0
A11 VDD1
F1 VDD2
F12 VDD3
M1 VDD4
K4J52324QC-BC20
K4J52324QC-BC20
C8902
0.1uF
10%
2 16V
X5R
402
20%
6.3V
CERM 2
805
VSS0 A3
VSS1 A10
VSS2 G1
MFHIGH
0.1uF
FBGA
Page Notes
CRITICAL
OMIT
=PP1V8_S0_FB_VDD
16MX32-GDDR3-500MHZ
C8901
22UF
U8900
IN
MFHIGH
C8900 1
A2 VDD0
A11 VDD1
F1 VDD2
F12 VDD3
M1 VDD4
71 70 63
16MX32-GDDR3-500MHZ
CRITICAL
OMIT
=PP1V8_S0_FB_VDD
K4J52324QC-BC20
IN
16MX32-GDDR3-500MHZ
71 70 63
MFHIGH
J3
68
68
68
68
68
68
68
68
68
68
68
68
68
FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>
FB_A_DQ<32>
FB_A_DQ<34>
FB_A_DQ<33>
FB_A_DQ<35>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<46>
FB_A_DQ<44>
FB_A_DQ<47>
FB_A_DQ<45>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<55>
FB_A_DQ<54>
FB_A_DQ<53>
FB_A_DQ<60>
FB_A_DQ<59>
FB_A_DQ<61>
FB_A_DQ<57>
FB_A_DQ<62>
FB_A_DQ<56>
FB_A_DQ<63>
FB_A_DQ<58>
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GDDR3 Frame Buffer A
IO
IO
IO
IO
IO

IO
IO

5%
1/16W
MF-LF
2 402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
SYNC_DATE=(MASTER)
89
OF
D
104
C9003
0.1uF
10%
2 16V
X5R
402
C9004
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
M12 VDD5
V2 VDD6
V11 VDD7
L9010
FERR-220-OHM
1
PP1V8_S0_FB_B0_VDDA0
K1 VDDA0
K12 VDDA1
VOLTAGE=1.8V
0402
L9015
FERR-220-OHM
1
VOLTAGE=1.8V
0402

71 70 63
IN
C9010
0.1uF
C9015
0.1uF
10%
2 16V
X5R
402
U9000.J1
10%
2 16V
X5R
402
U9000.J12
=PP1V8_S0_FB_VDDQ
C9020 1
22UF
20%
6.3V 2
CERM
805
C9021
0.1uF
10%
2 16V
X5R
402
C9022
0.1uF
C9023
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
(2 OF 2)
C9024
0.1uF
10%
2 16V
X5R
402
C9025
0.1uF
C9026
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4
C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9
R9030
2.37K
R9032
2.37K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
FB_B0_VREF0
V12
1
R9031
5.49K
R9033
R90421
121
R9041
1K
5%
1/16W
MF-LF
2 402
71 68
IN
71 68
IN
71 68
IN
71 68
IN
71 68
IN
71 68
IN
71 68
IN
71 68
IN
68
IN
68
IN
68
IN
68
IN
68
IN
68
IN
68
IN
R9045
1%
1/16W
MF-LF
2 402
68
68
68
68
68
68
IN
OUT
OUT
OUT
OUT
IN
IN
68
IN
68
IN
71 68
IN
71 68
71 68
IN
IN
20%
6.3V 2
CERM
805
10%
2 16V
X5R
402
R9080
2.37K
5.49K
R90921
5%
1/16W
MF-LF
2 402
E3
E10
68
N10
68
N3
68
DQ0
B2
B3
68
C2
68
FB_B_CKE<0>
FB_B_CLK_P<0>
FB_B_CLK_N<0>
FB_B_CS_L<0>
FB_B_WE_L<0>
FB_B_CAS_L<0>
FB_B_RAS_L<0>
H9
J11
CKE
J10
CK*
CS*
K2
M4
K11
L9
F4
H4
F9
H10
A4
A9
V4
V9
D3
D10
P10
P3
A9
A10
A11
CK
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
WE*
CAS*
RAS*
DQ10
DQ11
DQ12
DQ13
DQ14
ZQ
MF
DQ15
DQ16
SEN
DQ17
RESET
DQ18
DQ19
RDQS0
RDQS1
RDQS2
RDQS3
DQ20
DQ21
DQ22
D2
WDQS0
DQ23
DQ24
D11
P11
WDQS1
DQ25
WDQS2
WDQS3
DQ26
DQ27
DQ28
P2
G9
G4
NC
NC
A7
A8/AP
BA0
BA1
H3
BA2
J2
RFU1
RFU2
J3
DQ29
DQ30
DQ31
68
68
C3
E2
68
F3
68
F2
G3
68
B11
B10
68
C11
68
C10
E11
68
F10
68
F11
G10
68
68
M11
68
L10
N11
68
M10
R11
68
R10
68
68
68
68
68
68
68
T11
T10
68
M2
68
L3
N2
68
M3
68
R2
R3
68
T2
T3
68
68
68
68
68
C9073
0.1uF
10%
2 16V
X5R
402
C9074
0.1uF
C9075
0.1uF
C9076
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_B_DQM_L<0>
FB_B_DQ<15>
FB_B_DQ<12>
FB_B_DQ<14>
FB_B_DQ<13>
FB_B_DQ<8>
FB_B_DQ<9>
FB_B_DQ<11>
FB_B_DQ<10>
FB_B_DQ<18>
FB_B_DQ<17>
FB_B_DQ<19>
FB_B_DQ<16>
FB_B_DQ<20>
FB_B_DQ<22>
FB_B_DQ<23>
FB_B_DQ<21>
FB_B_DQ<29>
FB_B_DQ<30>
FB_B_DQ<28>
FB_B_DQ<31>
FB_B_DQ<27>
FB_B_DQ<24>
FB_B_DQ<26>
FB_B_DQ<25>
FB_B_DQ<1>
FB_B_DQ<6>
FB_B_DQ<0>
FB_B_DQ<5>
FB_B_DQ<3>
FB_B_DQ<7>
FB_B_DQ<2>
FB_B_DQ<4>
A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4
C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9
J4 VDDQ10
J9 VDDQ11
N1 VDDQ12
R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20
R9082
2.37K
1%
1/16W
MF-LF
402 2
V12
IN
71 68
IN
IN
71 68
IN
IN
71 68
IN
IN
71 68
IN
71 68
IN
IO
IO
IO
IO
IO
IO
IO
71 68
IN
71 68
IN
71 68
IN
71 68
IN
71 68
IN
71 68
IN
71 68
IN
C9081
0.1uF
5.49K
R90941
121
IO
IN
IO
68
IN
IO
68
IN
IO
68
IO
68
IN
IO
68
IN
IO
68
IN
IN
R9095
1%
1/16W
MF-LF
2 402
IO
IO
IO
68
68
68
68
OUT
OUT
OUT
OUT
68
IO
68
IO
68
IN
IO
68
IN
71 68
IN
IO
IO
IO
71 68
71 68
IN
IN
IN
IN
121
U9050
DM0
DM1
E3
E10
68
FBGA
A2
A3
(1 OF 2)
DM2
DM3
N10
68
N3
68
DQ0
B2
B3
68
C2
68
C3
E2
68
F3
68
F2
G3
68
FB_B_CKE<1>
FB_B_CLK_P<1>
FB_B_CLK_N<1>
FB_B_CS_L<1>
FB_B_WE_L<1>
FB_B_CAS_L<1>
FB_B_RAS_L<1>
H9
J11
CKE
B11
B10
68
J10
CK*
CS*
C11
68
C10
E11
68
F10
68
F11
G10
68
M11
68
L10
N11
68
M10
R11
68
R10
68
T11
T10
68
M2
68
L3
N2
68
M3
68
R2
R3
68
T2
T3
68
M9
K4
H2
K3
L4
K2
M4
K11
L9
A4
A5
A6
A7
A8/AP
A9
A10
A11
F4
H4
F9
H10
A4
A9
V4
V9
FB_DRAM_RST
FB_B_RDQS<6>
FB_B_RDQS<5>
FB_B_RDQS<4>
FB_B_RDQS<7>
D3
D10
P10
P3
FB_B_WDQS<6>
FB_B_WDQS<5>
FB_B_WDQS<4>
FB_B_WDQS<7>
243
1%
1/16W
MF-LF
402 2
R9099
100
NC
NC
DQ4
DQ5
DQ6
CK
DQ9
DQ10
DQ11
WE*
CAS*
RAS*
DQ12
DQ13
DQ14
ZQ
MF
DQ15
DQ16
SEN
DQ17
RESET
DQ18
DQ19
RDQS0
RDQS1
DQ20
DQ21
DQ22
RDQS2
RDQS3
D2
WDQS0
D11
P11
WDQS1
DQ25
WDQS2
WDQS3
DQ26
DQ27
DQ28
G9
G4
DQ3
DQ23
DQ24
P2
FB_B_BA<0>
FB_B_BA<1>
FB_B_BA<2>
DQ1
DQ2
DQ7
DQ8
BA0
BA1
H3
BA2
J2
RFU1
RFU2
DQ29
DQ30
DQ31
IO
5%
1/16W
MF-LF
2 402
VSSQ1
VSSQ2
B4
B9
VSSQ3
B12
VSSQ4
VSSQ5
D1
D4
VSSQ6
VSSQ7
D9
VSSQ8
D12
G2
VSSQ9
VSSQ10
G11
L2
VSSQ11
L11
VSSQ12
VSSQ13
P1
P4
VSSQ14
P9
VSSQ15
VSSQ16
P12
T1
VSSQ17
VSSQ18
T4
T9
T12
CRITICAL
OMIT
1%
1/16W
MF-LF
2 402
A1
R9098
B1
A0
VSSQ0
R9097
IO
IO
J1
J12
10%
2 16V
X5R
402
K10
IO
IO
VSSA1
VSSA0

(NONE)
V10
VDDQ21
K9
H11
IO
IN
V3
VSSQ19
FB_B_MA<0>
FB_B_MA<1>
FB_B_MA<2>
FB_B_MA<3>
FB_B_MA<4>
FB_B_MA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>
IO
IO
VSS6
VSS7

(NONE)
FB_B1_ZQ
FB_B1_MF
FB_B1_SEN
71 70 68
L1
L12
C9083
IO
68
G12
VSS4
VSS5
1%
1/16W
MF-LF
402 2
60.4
1%
1/16W
MF-LF
2 402
VSS3
60.4
1%
1/16W
MF-LF
402 2
R9093
A10
G1
R90961
121
A3
VSS1
VSS2
0.1uF
10%
2 16V
X5R
402
1%
1/16W
MF-LF
402 2
VSS0

- =PP1V8_S0_FB_VDD
- =PP1V8_S0_FB_VDDQ
H1 VREF0
H12 VREF1
R9083
1%
1/16W
MF-LF
402 2
1K
DM2
DM3
FB_B_BA<0>
FB_B_BA<1>
FB_B_BA<2>
0.1uF
121
R9091
DM1
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_B_WDQS<0>
C9072
1%
1/16W
MF-LF
402 2
R9081
DM0
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_B_RDQS<0>
10%
2 16V
X5R
402
A6
10%
2 16V
X5R
402
U9000.J12
FB_B1_VREF1
FBGA
K3
L4
C9065
0.1uF
10%
2 16V
X5R
402
U9000.J1
U9000
100
0.1uF
(1 OF 2)
H2
0.1uF
FB_B1_VREF0
A2
A3
R9049
C9071
(2 OF 2)
N4 VDDQ13
N9 VDDQ14
N12 VDDQ15
CRITICAL
OMIT
A4
A5
C9060
A1
VDDQ21
A0
1%
1/16W
MF-LF
402 2
22UF
VSSQ18 T9
VSSQ19 T12
K10
243
C9070 1
FBGA
M12 VDD5
V2 VDD6
V11 VDD7
=PP1V8_S0_FB_VDDQ
VSSQ15 P12
VSSQ16 T1
VSSQ17 T4
K9
H11
R9048
IN
VSSQ12 P1
VSSQ13 P4
VSSQ14 P9
FB_B_MA<0>
FB_B_MA<1>
FB_B_MA<2>
FB_B_MA<3>
FB_B_MA<4>
FB_B_MA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>
71 70 63
R9047
FB_DRAM_RST
M9
K4
10%
2 16V
X5R
402
U9050
K1 VDDA0
K12 VDDA1
VOLTAGE=1.8V
0402
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
0.1uF
10%
2 16V
X5R
402
121
FB_B0_ZQ
FB_B0_MF
FB_B0_SEN
71 70 68
R90901
121
C9054
VOLTAGE=1.8V
1%
1/16W
MF-LF
402 2
K4J52324QC-BC20
IN
60.4
1%
1/16W
MF-LF
2 402
10%
2 16V
X5R
402
FERR-220-OHM
1%
1/16W
MF-LF
402 2
MFHIGH
IN
71 68
121
0.1uF
L9065
VSSQ0 B1
VSSQ1 B4
VSSQ2 B9
10%
2 16V
X5R
402
16MX32-GDDR3-500MHZ
IN
71 68
R9043
C9053
0402
0.1uF
MFHIGH
IN
71 68
60.4
1%
1/16W
MF-LF
402 2
FERR-220-OHM
VSSA0 J1
VSSA1 J12
R90461
121
C9052
L9060
C9033
MFHIGH
71 68
R90441
1%
1/16W
MF-LF
402 2
10%
2 16V
X5R
402
1%
1/16W
MF-LF
402 2
121
1%
1/16W
MF-LF
402 2
C9031
0.1uF
5.49K
1%
1/16W
MF-LF
402 2
R90401
0.1uF
10%
2 16V
X5R
402
H1 VREF0
H12 VREF1
FB_B0_VREF1
VSS6 V3
VSS7 V10
VSSQ9 G11
VSSQ10 L2
VSSQ11 L11
J4 VDDQ10
J9 VDDQ11
N1 VDDQ12
0.1uF
20%
6.3V
CERM 2
805
VSSQ6 D9
VSSQ7 D12
VSSQ8 G2
R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20
VSS3 G12
VSS4 L1
VSS5 L12
C9051
22UF
VSSQ3 B12
VSSQ4 D1
VSSQ5 D4
N4 VDDQ13
N9 VDDQ14
N12 VDDQ15
C9050 1
A2 VDD0
A11 VDD1
F1 VDD2
F12 VDD3
M1 VDD4
K4J52324QC-BC20
K4J52324QC-BC20
C9002
0.1uF
10%
2 16V
X5R
402
20%
6.3V
CERM 2
805
VSS0 A3
VSS1 A10
VSS2 G1
MFHIGH
0.1uF
FBGA
Page Notes
CRITICAL
OMIT
=PP1V8_S0_FB_VDD
16MX32-GDDR3-500MHZ
C9001
22UF
U9000
IN
MFHIGH
C9000 1
A2 VDD0
A11 VDD1
F1 VDD2
F12 VDD3
M1 VDD4
71 70 63
16MX32-GDDR3-500MHZ
CRITICAL
OMIT
=PP1V8_S0_FB_VDD
K4J52324QC-BC20
IN
16MX32-GDDR3-500MHZ
71 70 63
MFHIGH
J3
68
68
68
68
68
68
68
68
68
68
68
68
68
FB_B_DQM_L<6>
FB_B_DQM_L<5>
FB_B_DQM_L<4>
FB_B_DQM_L<7>
FB_B_DQ<54>
FB_B_DQ<53>
FB_B_DQ<52>
FB_B_DQ<55>
FB_B_DQ<50>
FB_B_DQ<48>
FB_B_DQ<49>
FB_B_DQ<51>
FB_B_DQ<44>
FB_B_DQ<47>
FB_B_DQ<45>
FB_B_DQ<46>
FB_B_DQ<43>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<40>
FB_B_DQ<37>
FB_B_DQ<32>
FB_B_DQ<39>
FB_B_DQ<34>
FB_B_DQ<36>
FB_B_DQ<35>
FB_B_DQ<38>
FB_B_DQ<33>
FB_B_DQ<63>
FB_B_DQ<61>
FB_B_DQ<62>
FB_B_DQ<60>
FB_B_DQ<56>
FB_B_DQ<59>
FB_B_DQ<58>
FB_B_DQ<57>
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GDDR3 Frame Buffer B
IO
IO
IO
IO
IO

IO
IO

5%
1/16W
MF-LF
2 402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
SYNC_DATE=(MASTER)
90
OF
D
104
Page Notes
- =PP3V3_GPU_GPIOS
- =PP2V5_PVDD
- =PP1V8_GPU_LVDS_PLL
69 66 63

- =I2C_GPU_TMDS_SDA - I2C data line for
external TMDS transmitters
- =I2C_GPU_TMDS_SCL - I2C clock line for
external TMDS transmitters
69
69
69
69
69
69
69
69
69
69
69
69
69
1%
1/16W
MF-LF
2 402
=PP3V3_S0_GPU_VDDR3
C9100 1
22UF
20%
6.3V
CERM 2
805
63
Typically <50mA
1
C9101
1uF
C9102
1uF
10%
6.3V
2 CERM
402
10%
6.3V
2 CERM
402
=PP2V5_S0_GPU_VDD25
C9103
1uF
10%
6.3V
2 CERM
402
70mA total for VDD25
C9110
22UF
C9111
1uF
20%
6.3V 2
CERM
805
63
AE13
AF13
AF9
AG7
AE10
AE9
AF7
AF8
AH6
AF10
AG10
AH9
AJ8
AH8
AG9
AH7
AG8
10%
2 6.3V
CERM
402
C9112
0.1uF
10%
2 16V
X5R
402
AA9
AB9
AB10
AC19
AC20
AD18
AD19
AD20
K22
L10
AA10
AC13
AC16
AC18
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
22UF
C9116
1uF
20%
6.3V
CERM 2
805
VDD25
(2.5V)
10%
6.3V
2 CERM
402
VOLTAGE=3.3V
C9120
22UF
C9121
1uF
20%
6.3V
CERM 2
805
10%
6.3V
2 CERM
402
10%
6.3V
2 CERM
402
C9122
0.1uF
10%
16V
2 X5R
402
FERR-220-OHM Typically <50mA

1
2
PP1V8R3V3_S0_GPU_VDDR5_F
VOLTAGE=3.3V
0402
C9125
22UF
PP1V2_S0_GPU_VDDPLL
VOLTAGE=1.2V
0402
C9130 1
22UF
20%
6.3V 2
CERM
805
10%
6.3V
2 CERM
402
0.1uF
20mA
1
C9131
1uF
10%
2 6.3V
CERM
402
C9132
(PP2V5_S0_GPU_PVDD_F)
(GND_GPU_PVSS)
1uF
10%
2 6.3V
CERM
402
(PP1V0R1V2_S0_GPU_MPVDD)
(GND_GPU_MPVSS)
L9135
PP2V5_S0_GPU_PVDD_F
VOLTAGE=2.5V
0402
69
100mA
69
C9135 1
22UF
20%
6.3V
CERM 2
805
C9136
1uF
10%
6.3V
2 CERM
402
GPU_XTALIN
GPU_XTALOUT
C9137
NC
0.1uF
10%
16V
2 X5R
402
AE2
AE3
AE4
AE5
VDDR4
(1.8V/3.3V)
GPU_GENERICA
GPU_GENERICB
GPU_GENERICC
GPU_GENERICD
PANEL
DIGON
CONTROL VARY_BL
AE11
AD12
GPU_DIGON
GPU_VARY_BL
NC0
AB6
NC
NC_DVOVMODE_0
NC_DVOVMODE_1
AK4
AL4
NC
NC
DVPCLK
AG1
ATI_DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
AF2
AF1
AF3
ATI_DVPCNTL<0>
ATI_DVPCNTL<1>
ATI_DVPCNTL<2>
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
AG2
AG3
AH2
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AL3
AM3
ATI_DVPDATA<0>
ATI_DVPDATA<1>
ATI_DVPDATA<2>
ATI_DVPDATA<3>
ATI_DVPDATA<4>
ATI_DVPDATA<5>
ATI_DVPDATA<6>
ATI_DVPDATA<7>
ATI_DVPDATA<8>
ATI_DVPDATA<9>
ATI_DVPDATA<10>
ATI_DVPDATA<11>
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH5
AF6
AE7
AG6
ATI_DVPDATA<12>
ATI_DVPDATA<13>
ATI_DVPDATA<14>
ATI_DVPDATA<15>
ATI_DVPDATA<16>
ATI_DVPDATA<17>
ATI_DVPDATA<18>
ATI_DVPDATA<19>
ATI_DVPDATA<20>
ATI_DVPDATA<21>
ATI_DVPDATA<22>
ATI_DVPDATA<23>
DPLUS
DMINUS
AG12
AH12
ATI_TDIODE_P
ATI_TDIODE_N
ROM
ROMCS*
AC7
TP_ATI_ROMCS_L
TEST
TESTEN
AG22
ATI_TESTEN
VDDR5
(1.8V/3.3V)
AC15
VDDPLL (1.2V)
AJ14
AH14
PVDD
PVSS
(2.5V)
MPVDD
MPVSS
(2.5V)
A6
A5
FERR-220-OHM
2
0402
XTALIN
XTALOUT
AG14
PLLTEST
PPVCORE_S0_GPU_MPVDD
VOLTAGE=1.2V
THERMAL
DIODE
69
C9191 1
69
0.1uF
69
69
10%
16V
X5R 2
402
R9191
499
1%
1/16W
MF-LF
2 402
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
66
74
74
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
50
50
69
R9195
1K
VOLTAGE=0V
L9140
AL26
AM26
XW9135
SM
GND_GPU_PVSS
C9127
10%
16V
2 X5R
402
AJ5
AK5
AL5
AM5
FERR-220-OHM
1
=PPVCORE_S0_GPU
AK22
AF23
AE23
AD23
200-OHM-EMI
1
=PP2V5_S0_GPU_PVDD
C9126
1uF
20%
6.3V
CERM 2
805
L9130
=PP1V2_S0_GPU_VDDPLL
GENERICA
GENERICB
GENERICC
GENERICD
1uF
L9125
63
GPU_GPIO_0
GPU_GPIO_1
GPU_GPIO_2
GPU_GPIO_3
GPU_GPIO_4
GPU_GPIO_5
GPU_GPIO_6
GPU_GPIO_7
GPU_GPIO_8
GPU_GPIO_9
GPU_GPIO_10
GPU_GPIO_11
GPU_GPIO_12
GPU_GPIO_13
GPU_GPIO_14
GPU_GPIO_15
GPU_GPIO_16
GPU_GPIO_17
C9117
L9120
0402
ATI_VREFG
VDDR3
(3.3V)
FERR-220-OHM Typically <50mA

1
2
PP1V8R3V3_S0_GPU_VDDR4_F
AC8
AD4
AD2
AD1
AD3
AC1
AC2
AC3
AB2
AC6
AC5
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7
=PP2V5_S0_GPU_VDDC_CT
C9115
63
VREFG
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
VIP HOST / EXTERNAL TMDS
63
GPU_GPIO_18
GPU_GPIO_19
GPU_GPIO_20
GPU_GPIO_21
GPU_GPIO_22
GPU_GPIO_23
GPU_GPIO_24
GPU_GPIO_25
GPU_GPIO_26
GPU_GPIO_27
GPU_GPIO_28
GPU_GPIO_29
GPU_GPIO_30
GPU_GPIO_31
GPU_GPIO_32
GPU_GPIO_33
GPU_GPIO_34
GENERAL PURPOSE I/O
69
69
69
67 63 51
499
BGA
(6 OF 7)
69
63
R9190
M56P

(NONE)
63
U8400
PLL & XTAL
=PP3V3_S0_GPU
OMIT
5%
1/16W
MF-LF
2 402
ATI M56 GPIO/DVO/Misc
20mA
C9140 1
22UF
20%
6.3V 2
CERM
805
C9141
1uF
10%
2 6.3V
CERM
402
C9142
SYNC_DATE=(MASTER)
0.1uF
10%
2 16V
X5R
402
XW9140
SM
GND_GPU_MPVSS

VOLTAGE=0V

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
91
OF
D
104
Page Notes
- =PP2V5_S0_GPU
- =PP1V8R2V5_S0_GPU_LVDDR
(NONE)
(NONE)
L9300
FERR-220-OHM
0402
FERR-220-OHM
1
XW9310
SM
FERR-220-OHM
PP2V5_S0_GPU_VDD1DI
VOLTAGE=2.5V
C9315
22UF
20%
6.3V 2
CERM
805
C9316
10%
2 6.3V
CERM
402
C9317
22UF
20%
6.3V
CERM 2
805
VOLTAGE=0V
PP2V5_S0_GPU_AVDD
M56P
C9302
BGA
(5 OF 7)
1uF
10%
6.3V
2 CERM
402
AM8
AL8
C9306
10%
6.3V
402
2 X5R
1uF
2 CERM
AJ6
AK6
AL6
AM6
AJ7
AK7
AK8
AL7
AM7
C9307
0.1uF
10%
16V
402
65mA peak
C9310
22UF
20%
6.3V 2
CERM
805
C9311
1uF
10%
2 6.3V
CERM
402
0.1uF
AL25
AM25
10%
402
0402
C9326
1uF
10%
2 6.3V
CERM
402
C9327
0.1uF
10%
2 16V
X5R
22UF
20%
6.3V
CERM 2
805
73
C9321
1uF
10%
6.3V
2 CERM
402
ATI_RSET
C9322
10%
16V
2 X5R
402
VOLTAGE=0V
NC
GND_GPU_A2VSSQ
VOLTAGE=0V
20mA peak
L9330
73
XW9330
SM
1
PP2V5_S0_GPU_LPVDD
ATI_R2SET
20mA peak
VOLTAGE=2.5V
0402
C9330
20%
6.3V
CERM 2
805
VOLTAGE=0V
L9345
22UF
GND_GPU_LPVSS
C9331
10%
6.3V
402
2 CERM
1uF
2 CERM
C9332
1uF
10%
6.3V
402
FERR-220-OHM
1
PP2V5_S0_GPU_LVDDR
200mA peak
VOLTAGE=2.5V
0402
C9340 1
22UF
20%
6.3V
CERM 2
805
XW9345
SM
1
C9345 1
22UF
20%
6.3V
CERM 2
805
C9341
1uF
10%
6.3V
402
2 CERM
C9342
0.1uF
10%
16V
402
2 X5R
C9346
0.1uF
10%
16V
402
2 X5R
C9347
0.1uF
10%
16V
402
2 X5R
GND_GPU_LVSSR
VOLTAGE=0V
ATI_RSET
ATI_R2SET
1
R9350
499
1%
1/16W
MF-LF
2 402
TXVSSR
AVDD
(2.5V)
AVSS
AK23
AVSSQ
AM23
AL23
VDD1DI (2.5V)
VSS1DI
AL22
RSET
A2VDD
(2.5V)
AL17
AM17
A2VSS
AL14
AK13
NC_A2VDDQ
A2VSSQ
AJ16
AJ17
VDD2DI (2.5V)
VSS2DI
AK14
R2SET
AE19
AE18
LPVDD (2.5V)
LPVSS
FERR-220-OHM
402
TXVDDR
(2.5V)
AJ24
AK25
AL16
AM16
0.1uF
GND_GPU_A2VSSN
XW9324
SM
C9320 1
PP2V5_S0_GPU_A2VDD
VOLTAGE=2.5V
TPVDD (2.5V)
TPVSS
C9312
2 16V
X5R
130mA peak
FERR-220-OHM
10%
2 16V
X5R
402
VOLTAGE=2.5V
20%
6.3V 2
CERM
805
C9305 1
L9320
0.1uF
FERR-220-OHM
PP2V5_S0_GPU_VDD2DI
10%
6.3V
2 CERM
402
20mA peak
1uF
1uF
VOLTAGE=0V
0402
L9325
C9301
GND_GPU_AVSSQ
XW9320
SM
22UF
150mA peak
VOLTAGE=0V
0402
C9325
PP2V5_S0_GPU_TXVDDR
GND_GPU_AVSSN
XW9314
SM
L9315
VOLTAGE=0V
VOLTAGE=2.5V
0402
20%
6.3V
CERM 2
805
GND_GPU_TXVSSR
L9310
22UF
VOLTAGE=2.5V
XW9305
SM
1
C9300
AC21
AC22
AD21
AD22
AE20
AE21
AE22
AF19
AF20
AF17
AF18
AF21
AF22
AG17
AG19
AH17
AH19
AJ19
AK17
LVDDR
(2.5V)
LVSSR
73
73
R9351
75
715
INTEGRATED TMDS
L9305
FERR-220-OHM
1
U8400
GND_GPU_TPVSS
OMIT
20mA peak
IN
GPU_HPD
AF11
DAC (CRT)
XW9300
SM
1
PP2V5_S0_GPU_TPVDD
VOLTAGE=2.5V
DAC2 (TV/CRT2)
0402
LVDS
HPD1
MONITOR
IDENTIFICATION
=PP2V5_S0_GPU
63
Sum of peak currents on this page: 605mA
79 75
74
TXCP
TXCM
AM9
AL9
TX0P
TX0M
TX1P
TX1M
TX2P
TX2M
AL10
AK10
AM11
AL11
AM12
AL12
TX3P
TX3M
TX4P
TX4M
TX5P
TX5M
AJ9
AK9
AJ11
AK11
AJ12
AK12
R
G
B
AK24
AM24
AL24
69
HSYNC
VSYNC
AJ23
AJ22
69
R2
G2
B2
AK15
AM15
AL15
75
74
H2SYNC
V2SYNC
AF15
AG15
75
Y
C
AJ15
AJ13
69
COMP
AH15
TXCLK_UP
TXCLK_UN
AJ21
AK21
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
AG18
AH18
AK20
AJ20
AG20
AH20
AH21
AG21
TXCLK_LP
TXCLK_LN
AM18
AL18
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
AL19
AK19
AM20
AL20
AM21
AL21
AJ18
AK18
DDC1CLK
DDC1DATA
AH23
AH22
79 75
74
79 75
74
79 75
74
79 75
74
79 75
74
79 75
74
79 75
74
79 75
74
79 75
74
79 75
74
79 75
74
79 75
74
79 75
74
69
69
69
75
74
75
74
77
74
77
74
69
69
77
74
77
74
77
74
77
74
77
74
77
74
77
74
77
74
69
69
AF12
AE12
74
74
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
GPU_VGA_HSYNC
GPU_VGA_VSYNC
GPU_R2
GPU_G2
GPU_B2
OUT
OUT
OUT
OUT
OUT
GPU_TV_COMP
77
74
DDC3CLK
DDC3DATA
OUT
69
77
74
69
OUT
69
77
74
69
GPU_VGA_R
GPU_VGA_G
GPU_VGA_B
OUT
OUT
77
74
AG13
AH13
TMDS_DATA_P<3>
TMDS_DATA_N<3>
TMDS_DATA_P<4>
TMDS_DATA_N<4>
TMDS_DATA_P<5>
TMDS_DATA_N<5>
OUT
GPU_TV_Y
GPU_TV_C
77
74
DDC2CLK
DDC2DATA
OUT
TMDS_DATA_P<0>
TMDS_DATA_N<0>
TMDS_DATA_P<1>
TMDS_DATA_N<1>
TMDS_DATA_P<2>
TMDS_DATA_N<2>
OUT
77
74
75
OUT
GPU_H2SYNC
GPU_V2SYNC
75
75
TMDS_CLK_P
TMDS_CLK_N
Composite/S-Video
VGA
OUT
Y
C
G
R
Y
Pr
OUT
Comp
Pb
OUT
LVDS_U_CLK_P
LVDS_U_CLK_N
Component
OUT
OUT
LVDS_U_DATA_P<0>
LVDS_U_DATA_N<0>
LVDS_U_DATA_P<1>
LVDS_U_DATA_N<1>
LVDS_U_DATA_P<2>
LVDS_U_DATA_N<2>
LVDS_U_DATA_P<3>
LVDS_U_DATA_N<3>
LVDS_L_CLK_P
LVDS_L_CLK_N
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
LVDS_L_DATA_P<0>
LVDS_L_DATA_N<0>
LVDS_L_DATA_P<1>
LVDS_L_DATA_N<1>
LVDS_L_DATA_P<2>
LVDS_L_DATA_N<2>
LVDS_L_DATA_P<3>
LVDS_L_DATA_N<3>
GPU_DDC_A_CLK
GPU_DDC_A_DATA
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
ATI M56 Video Interfaces
IO
IO
GPU_DDC_B_CLK
GPU_DDC_B_DATA
IO
GPU_DDC_C_CLK
GPU_DDC_C_DATA
IO

IO
1%
1/16W
MF-LF
2 402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
SYNC_DATE=(MASTER)
IO
93
OF
D
104
NET_TYPE
SPACING PHYSICAL
LCD (LVDS) INTERFACE
VGA
VGA
VGA
VGA
VGA
VGA
GPU_R2
GPU_G2
GPU_B2
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_U_CLK_P
LVDS_U_CLK_N
LVDS_U_DATA_P<2..0>
LVDS_U_DATA_N<2..0>
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_L_CLK_P
LVDS_L_CLK_N
LVDS_L_DATA_P<2..0>
LVDS_L_DATA_N<2..0>
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_U_CLK_CONN_P
LVDS_U_CLK_CONN_N
LVDS_U_DATA_CONN_P<2..0>
LVDS_U_DATA_CONN_N<2..0>
73 75
63
=PP3V3_S0_LCD
73 75
73 75
C9400
73 77
5%
1/16W
MF-LF
402 2
73 77
73 77
73 77
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA_P<5..3>
TMDS_DATA_N<5..3>
TMDS_DATA_P<2..0>
TMDS_DATA_N<2..0>
R9401
LCD_PWREN_L_RC
L9400
FERR-250-OHM
6
5
2
1
5%
1/16W
MF-LF
402
73 77
LVDS_L_CLK_CONN_P
LVDS_L_CLK_CONN_N
LVDS_L_DATA_CONN_P<2..0>
LVDS_L_DATA_CONN_N<2..0>
10%
50V
CERM
402
100K
73 77
LVDS
LVDS
LVDS
LVDS
100K
73 77
LVDS
LVDS
LVDS
LVDS
0.0022uF
R94001
73 77
LCD_PWREN_L
PP3V3_LCD_SW
VOLTAGE=3.3V
0.001uF
TSOP-LF
20%
50V
CERM 2
402
SI3443DV
74 77
74 77
Q9400
74 77
Q9401
D
74 77
SM
C9401 1
=GND_CHASSIS_LCD2
=GND_CHASSIS_LCD1
CRITICAL
2N7002
74 77
72
GPU_DIGON
74 77
R94941
74 77
SOT23-LF
63
5%
1/16W
MF-LF
402 2
73 75 79
402 2
73 75 79
73 75 79
73
73 75 79
73
F-RT-SM
34
20%
50V
CERM 2
402
R9410
100K pull-ups are for
100K
no-panel case (development)
5%
1/16W
Panel has 2K pull-ups
MF-LF
73 75 79
MSC-RB30-5-FA
0.001uF
=PP3V3_S0_DDC_LCD
100K
74 77
73 75 79
J9400
C9420 1
R9411
100K
5%
1/16W
MF-LF
2 402
PP3V3_LCD_CONN
VOLTAGE=3.3V
NC
GPU_DDC_C_CLK
GPU_DDC_C_DATA
77 74
C9410 1
77 74
20%
50V
CERM 2
402
77 74
LVDS_L_DATA_CONN_N<0>
LVDS_L_DATA_CONN_P<0>
0.001uF
=GND_CHASSIS_LCD3
77 74
77 74
77 74
77 74
77 74
77 74
77 74
77 74
77 74
77 74
77 74
77 74
INVERTER INTERFACE
77 74
LVDS_L_CLK_CONN_N
LVDS_L_CLK_CONN_P
LVDS_U_DATA_CONN_N<0>
LVDS_U_DATA_CONN_P<0>
LVDS_U_CLK_CONN_N
LVDS_U_CLK_CONN_P
C9421
2
FERR-1K-OHM-EMI
=PPBUS_S0_INVERTER
Q9450
=PP5V_S0_INVERTER
FDG6332C_NL
L9452
SC70-6
R94501
VOLTAGE=5V
5%
1/16W
MF-LF
402 2
PP5V_INVERTER_SW_F
100K
C9450
20%
6.3V 2
X5R
603
PP5V_INVERTER_SW
N-CHN
R9489
FDG6332C_NL
SC70-6
400-OHM-EMI
10K
C9454 1
0.001uF
20%
50V
CERM 2
402
NC
20%
2 50V
CERM
402
SM-1
=PP3V3_S0_INVERTER
C9452
0.001uF
L9454
5%
1/16W
MF-LF
402 2
63
SM-2MT-LF
5
1
2
3
4
VOLTAGE=5V
Q9450
S
1
J9450
NC
2 G
=GND_CHASSIS_LCD4
CRITICAL
SM-1
GPU_BLON
518S0289
10UF
FP_PWR_EN_L
69
20%
2 50V
CERM
402
C9451 1
G
5
33
0.001uF
400-OHM-EMI
P-CHN
20%
50V
CERM
402
PPBUS_S0_INVERTER
VOLTAGE=12.8V
SM
63
0.001uF
L9450
63
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
518S0293
INVERTER_PWM
GND_INVERTER
VOLTAGE=0V
1
C9455
0.001uF
20%
2 50V
CERM
402
L9455
60-OHM-EMI
SM
=GND_CHASSIS_INVERTER
INVERTER_BUF
5
1
72
GPU_VARY_BL
INVERTER_BUF
MC74VHC1G08
SC70
INVERTER_PWM_F
U9453 4
2
INVERTER EXPECTS ACTIVE HIGH PWM SIGNAL
Internal Display Connectors

C9453 1
20%
10V
CERM 2
402

INVERTER_UNBUF
R9496
1

5%
1/16W
MF-LF
402
SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
SYNC_DATE=(MASTER)
0.1uF
94
OF
D
104
TMDS Filtering
VGA SYNC BUFFERS

75 63
Place series Rs and common-mode filtering close to GPU, common mode chokes near connector.
CRITICAL
R9760
79 74 73
TMDS_DATA_N<0>
182
1%
1/16W
MF-LF
402 2
79 74 73
TMDS_DATA_P<0>
75
TMDS_DATA_R_N<0>
5%
1/16W
MF-LF
402
R97621
=PP3V3_S0_VGASYNC
L9700
90-OHM-300mA
2012H
SYM_VER-1
TMDS_DATA_F_N<0>
73
GPU_V2SYNC
R9761
1
75
TMDS_DATA_F_P<0>
SC70
VGA_VSYNC_R
33
VGA_VSYNC
75
5%
1/16W
MF-LF
402
75 79
C9750
2
R9750
MC74VHC1G08
U9750 4
2
3
1
R97661
182
75
TMDS_DATA_R_N<1>
L9701
90-OHM-300mA
2012H
SYM_VER-1
75 63
TMDS_DATA_F_N<1>
75 79
TMDS_DATA_F_P<1>
75 79
TMDS_DATA_P<1>
R9765
1
75
79 74 73
TMDS_DATA_N<2>
73
GPU_H2SYNC
R9770
182
C
79 74 73
TMDS_DATA_P<2>
U9751
VGA_HSYNC_R
TMDS_DATA_R_N<2>
TMDS_DATA_F_N<2>
75 79
TMDS_DATA_F_P<2>
75 79
75
79 74 73
TMDS_CLK_N
3
1
TMDS_CLK_P
TMDS_CLK_F_N
75 79
TMDS_CLK_F_P
75 79
C9774
=PP5V_S0_DVI_DDC
VOLTAGE=5V
182
79 74 73
TMDS_DATA_P<3>
TMDS_DATA_R_N<3>
79 75
L9703
75
TMDS_DATA_F_N<3>
TMDS_DATA_N<4>
R9782
182
79 74 73
TMDS_DATA_P<4>
75
TMDS_DATA_R_N<4>
TMDS_DATA_F_P<3>
75
79 75
TMDS_DATA_F_N<5>
20
4
12
79 75
TMDS_DATA_F_P<5>
21
22
13
6
L9704
79 75
R9786
182
79 74 73
TMDS_DATA_P<5>
TMDS_CLK_F_N
7
15
24
8
16
TMDS_DATA_F_N<4>
TMDS_DATA_F_P<4>
75
VGA_B
75
VGA_HSYNC
75 79
TMDS_DATA_F_N<2>
TMDS_DATA_F_N<1>
TMDS_DATA_F_P<2>
TMDS_DATA_F_P<1>
75
VGA_R
1
C9742
3.3pF
0.25%
2 50V
CERM
402
TMDS_DATA_F_N<4>
TMDS_DATA_F_N<3>
TMDS_DATA_F_P<4>
TMDS_DATA_F_P<3>
DVI_DDC_CLK_R
(PP5V_S0_DDC)
DVI_DDC_DATA_R
VGA_VSYNC
DVI_HPD_R
2012H
SYM_VER-1
=GND_CHASSIS_DVI2
TMDS_DATA_F_P<5>
R9720
Q9711
2N7002DW-X-F
100
SOT-363
C9711
2N7002DW-X-F
75 79
75 79
100
SOT-363
DVI_DDC_DATA
VGA_G
75
34
32
5%
1/16W
MF-LF
402
75 79
0.01uF
R9730
0
=GND_CHASSIS_DVI4
Q9714
SOT-363
R9714
2
3 D
DVI_HPD
S 1
GPU_DDC_A_DATA
73
100K
5%
1/16W
MF-LF
2 402
C9714
G
S 4
GPU_HPD
73
R9715
20K
5%
1/16W
MF-LF
402 2
5%
2 50V
CERM
402
=GND_CHASSIS_DVI3
=GND_CHASSIS_DVI5
External Display Connector

SYNC_DATE=(MASTER)
PLACE NEAR 3, 11 & 19
75 79
6 D
100pF
20%
50V
CERM 2
603
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
R9722
5%
1/16W
MF-LF
402
C9710 1
2N7002DW-X-F
100
100pF
73
10K
5%
1/16W
MF-LF
402
C9713
5%
2 50V
CERM
402
75
GPU_DDC_A_CLK
R9721
R9713
1
S 4
Q9711
5%
2 50V
CERM
402
75 79
5%
1/16W
MF-LF
2 402
3 D
DVI_DDC_CLK
10K
5%
1/16W
MF-LF
402
100pF
C2
514-0278
5%
1/16W
MF-LF
2 402
C4
R9731
TMDS_DATA_F_N<5>
4.7K
75 79
75
R9712
75 79
75 79
=PP3V3_S0_DDC_DVI
75 79
63

TMDS_DATA_R_P<5>
5%
1/16W
MF-LF
402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7099
D
SCALE
75
3 4
75 79
L9705
90-OHM-300mA
1
SM-220MHZ-LF
1
R9711
VGA_R
CRITICAL
TMDS_DATA_R_N<5>
0.25%
2 50V
CERM
402
LCFILTER
VOLTAGE=5V
5%
1/16W
MF-LF
402 2
75 79
PLACE NEAR C5A & C5B
75
C9741
3.3pF
FL9742
PP5V_S0_DDC_PULLUPS
R97101
C1
C5A
C3
C5B
TMDS_DATA_R_P<4>
R9785
0
23
2012H
2
1
TMDS_CLK_F_P
90-OHM-300mA
CRITICAL
3V LEVEL SHIFTERS
B0530WXF
3
11
75 79
SYM_VER-1
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402 2
18
TMDS_DATA_F_P<0>
14
R9784
TMDS_DATA_N<5>
9
2
19
5%
1/16W
MF-LF
402
79 74 73
CRITICAL
R9781
1
17
TMDS_DATA_R_P<3>
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402 2
TMDS_DATA_F_N<0>
75 79
79 75
79 74 73
31
10
5%
1/16W
MF-LF
402
R9780
75
Isolation required for DVI power switch
4.7K
SYM_VER-1
VGA_G
1%
1/16W
MF-LF
402 2
=GND_CHASSIS_DVI1
2012H
79 75
90-OHM-300mA
R9777
1
2
3 4
GPU_R2
(DAC2 C)
J9700
CRITICAL
75
SM-220MHZ-LF
1
D9710
SOD-123
F-RT-TH-DVI
5%
1/16W
MF-LF
402
R97781
1%
1/16W
MF-LF
402 2
0.25%
2 50V
CERM
402
PP5V_S0_DDC
VOLTAGE=5V
QH11121-RIG02-4F
R9776
0
2
SM-1
CRITICAL
33
C9740
3.3pF
FL9741
LCFILTER
400-OHM-EMI
PP5V_S0_DDC_F
1%
1/16W
MF-LF
402 2
10%
50V
CERM
402
TMDS_DATA_N<3>
CRITICAL
L9710
F9710
0.5AMP-13.2V
TMDS_CLK_CMF
75
CRITICAL
63
90.9
1%
1/16W
MF-LF
2 402
VGA_B
(55mA requirement per DVI spec)
R97751
90.9
75 79
DVI DDC CURRENT LIMIT
SM-LF
R9774
R9741
TMDS_CLK_R_P
75 79
3 4
GPU_G2
(DAC2 Y)
DVI INTERFACE
L9706
370-OHM
1
75
75 79
75
TMDS_CLK_R_N
75
75 79
FL9740
74 73
SM
0.001uF
79 74 73
75
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
SYM_VER-1
5%
1/16W
MF-LF
402
75
74 73
CRITICAL
75
TMDS_DATA_F_P<5..0>
TMDS_DATA_F_N<5..0>
R9742
R9773
79 74 73
VGA_HSYNC
TMDS_DATA_R_P<2>
5%
1/16W
MF-LF
402
TMDSCONN
TMDSCONN
R9772
0
TMDSCONN
TMDSCONN
75
TMDS_CLK_F_P
TMDS_CLK_F_N
R97401
2012H
SYM_VER-1
TMDSCONN
TMDSCONN
GPU_B2
(DAC2 Comp)
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
33
20%
10V
CERM 2
402
L9702
90-OHM-300mA
R9769
0
SC70
4
R9751
MC74VHC1G08
0.1uF
CRITICAL
75
TMDSCONN
TMDSCONN
75
LCFILTER
C9751
2
TMDS_DATA_R_P<5..0>
TMDS_DATA_R_N<5..0>
SM-220MHZ-LF
TMDS_DATA_R_P<1>
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402 2
TMDS
TMDS
CRITICAL
=PP3V3_S0_VGASYNC
5%
1/16W
MF-LF
402
R9768
TMDS
TMDS
75
75
ANALOG FILTERING
PLACE CLOSE TO CONNECTOR
74 73
1%
1/16W
MF-LF
402 2
79 74 73
TMDS_CLK_R_P
TMDS_CLK_R_N
PLACE U9750 & U9751 CLOSE TO DVI CONNECTOR
CRITICAL
5%
1/16W
MF-LF
402
TMDS
TMDS
20%
10V
CERM 2
402
TMDS_DATA_R_P<0>
R9764
TMDS_DATA_N<1>
TMDS
TMDS
0.1uF
75 79
5%
1/16W
MF-LF
402
79 74 73
NET_TYPE
SPACING
PHYSICAL
97
OF
D
104
Left ALS Connector

CRITICAL
J6430
FH19-4S-0.5SH-48
F-RT-SM
5
NC
=PP3V3_S3_LTALS
5 63
1
47
6
5
2
3
ALS_GAIN
LTALS_OUT
IN
OUT
NC
518S0395
Bluetooth (M13P), IR & SATA HDD Flex Connector

63
63
63
=PP3V3_S3_BT
=PP5V_S3_IR
=PP5V_S0_HDD
PLACEMENT_NOTE=Place FL4960 close to J4960

CRITICAL
CRITICAL
J4960
FL4965
0.0047uF
SYM_VER-1
OUT 21
SATA_C_D2R_P
SATA_C_D2R_UF_P
C4966
OUT 21
SATA_C_D2R_N
0.0047uF
SATA_C_D2R_UF_N
SATA_C_D2R_C_P
SATA_C_D2R_C_N
10%
25V
CERM
402
10%
25V
CERM
402
0.0047uF
SYM_VER-1
IO
IO
=USB_BT_N
=USB_BT_P
SATA_C_R2D_N
SATA_C_R2D_P
10
11
12
13
14
15
16
17
18
19
20
48
=USB_IR_N
=USB_IR_P
SYS_LED_ANODE
C4961
90-OHM-300mA
2012H
M-ST-SM
C4965
90-OHM-300mA
2012H
FL4960
QT500206-L020
PLACEMENT_NOTE=Place FL4965 close to southbridge

CRITICAL
SATA_C_R2D_UF_N
SATA_C_R2D_UF_P
10%
25V
CERM
402
21
SATA_C_R2D_C_N
IN
SATA_C_R2D_C_P
IN
C4960
0.0047uF
1
21
IO
10%
25V
CERM
402
IO
IN
PLACEMENT_NOTE=Place C4960 close to southbridge

PLACEMENT_NOTE=Place C4961 next to C4960
PLACEMENT_NOTE=Place C4965 close to J4960

PLACEMENT_NOTE=Place C4966 next to C4965
516S0412
NOTE: _UF_ nets cross DDR2 signals and pick
up significant noise. Common-mode chokes
are to remove this noise from SATA signals.
M1 Specific Connectors
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
98
OF
D
104
NOTE: These parts are to counter an invalid state caused by the

M56 part. Bias voltage is present on LVDS interface pins even
when they should be tri-stated to meet panel power sequence
requirements. Resulting pump-up in LCD panel can cause startup
and long-term reliability issues. Pull-down resistors reduce
the pump-up in the panel, though some voltage will still be seen
on LVDS signals when they should be 0V.
LVDS_PD
RP9900
74 73
LVDS_L_DATA_P<0>
74
8.2K
MAKE_BASE=TRUE
LVDS_PD
5%
1/16W
SM-LF
74 73
LVDS_L_DATA_N<0>
74
RP9900
MAKE_BASE=TRUE
LVDS_PD
LVDS_L_DATA_P<1>
74
8.2K
MAKE_BASE=TRUE
LVDS_PD
5%
1/16W
SM-LF
74 73
LVDS_L_DATA_N<1>
74
RP9900
MAKE_BASE=TRUE
LVDS_PD
LVDS_L_DATA_P<2>
74
8.2K
LVDS_L_DATA_N<2>
74
MAKE_BASE=TRUE
LVDS_PD
5%
1/16W
SM-LF
74 73
8.2K
5%
1/16W
SM-LF
RP9901
74 73
5%
1/16W
SM-LF
RP9900
74 73
8.2K
RP9901
8.2K
MAKE_BASE=TRUE
5%
1/16W
SM-LF
LVDS_PD
RP9901
74 73
LVDS_L_CLK_P
74
LVDS_L_CLK_CONN_P
8.2K
MAKE_BASE=TRUE
LVDS_PD
5%
1/16W
SM-LF
74 73
LVDS_L_CLK_N
74
RP9901
LVDS_L_CLK_CONN_N
8.2K
MAKE_BASE=TRUE
5%
1/16W
SM-LF
LVDS_PD
RP9902
74 73
LVDS_U_DATA_P<0>
74
8.2K
MAKE_BASE=TRUE
LVDS_PD
5%
1/16W
SM-LF
74 73
LVDS_U_DATA_N<0>
74
RP9902
MAKE_BASE=TRUE
LVDS_PD
LVDS_U_DATA_P<1>
74
8.2K
MAKE_BASE=TRUE
LVDS_PD
5%
1/16W
SM-LF
74 73
LVDS_U_DATA_N<1>
74
RP9902
MAKE_BASE=TRUE
LVDS_PD
74 73
LVDS_U_DATA_P<2>
74
LVDS_U_DATA_N<2>
74
MAKE_BASE=TRUE
LVDS_PD
5%
1/16W
SM-LF
74 73
8.2K
5%
1/16W
SM-LF
RP9903
8.2K
2
5%
1/16W
SM-LF
RP9902
74 73
8.2K
RP9903
8.2K
MAKE_BASE=TRUE
5%
1/16W
SM-LF
LVDS_PD
RP9903
74 73
LVDS_U_CLK_P
74
LVDS_U_CLK_CONN_P
8.2K
MAKE_BASE=TRUE
5%
1/16W
SM-LF
74 73
LVDS_U_CLK_N
74
LVDS_U_CLK_CONN_N
LVDS_PD
RP9903
3
8.2K
MAKE_BASE=TRUE
5%
1/16W
SM-LF

SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7099
D
OF
99
104
8
Date
6
Date
DMS Checkin #07001
2005/08/11 - 4214109 - Changed J4931 to proper 518S0342 part.

2005/08/12 - 4231030 - Changed pinout of J4960, added placement notes.
2005/09/28
2005/09/28
2005/09/29
2005/09/30
2005/09/30
2005/09/30
2005/09/30
2005/09/30
2005/08/27
2005/08/27
2005/08/27
2005/08/27
4230219
4235208
4235213
4235401
Changed
Changed
Changed
Moved a
Y3301 to non-obsoleted part.

value of R7707 to fix 2.5V S3 supply.
R8305, R8310, R8315 to slow down FET RCs.
few pins at LIO BTB connector.
2005/08/27
2005/08/27
2005/08/27
2005/08/28
2005/08/28
2005/08/28
2005/08/28
2005/08/28
2005/08/28
2005/08/28
2005/08/28
2005/08/28
2005/08/28
2005/08/28
2005/08/28
2005/08/28
2005/08/28
2005/08/28
4227325
4227369
4225433
4217535
4232563
4235203
4217524
4217535
4221973
4225369
4225433
4227322
4235179
4235179
4232715
4235217
4225369
4227323
Removed S0 option for camera, now S3-only.

Removed SMC options for display/backlight, now GPU-only.
Changed PBUS voltage sense circuit.
Added Left ALS FFC connector.
Changed analog video from Y/C/Comp to G2/R2/B2.
Changed BOM settings to stuff R2251.
Added LEFT ALS connector (J6430).
OMITs and tables to change 4-pin WTB connector parts.
Added pull-up for SB GPIO22 (REQ4#).
Changed ISL6269 PVCC aliases, added RC for 3.3V S5.
Changed PBUS Voltage Sense circuit.
Changed FW323 PCI_VIOS pin from 3.3V S0 to 3.3V S3.
OMIT and table to change 8-pin DC-In connector to 6-pin.
Changed PBUS net names to merge PBUS A & PBUS B.
Added FireWire ISense resistor, changed INA193 to INA194.
Added RC on Q3820 gate to slow down ODD FET turn-on.
OMITs and tables for staged LeMenu BOM approach.
Repinned Top-Case Flex connector.
4235179
4232826
4217524
4237119
4225369
4227336
4227309
4227310
4227312
4227322
4227332
4227335
2005/10/04
2005/10/04
2005/10/04
2005/10/06
2005/10/07
2005/10/07
2005/10/07
4225433
4217535
4214109
4227328
4223808
4227315
4237025
2005/10/08
2005/10/08
2005/10/08
2005/10/08
2005/10/09
2005/10/09
2005/10/09
4240157
4240150
4232563
4227306
4240300
4240486
4240257
2005/10/10
2005/10/10
2005/10/10
2005/10/10
2005/10/10
4241087
4243269
4244019
4240486
2005/10/11
2005/10/11
2005/10/11
2005/10/12
2005/10/12
2005/10/12
2005/10/12
2005/10/12
2005/10/12
2005/10/12
2005/10/12
2005/10/12
2005/10/12
2005/10/12
4232534
4244484
4244539
4227315
4232534
Fixed voltage divider values in PBUS VSense circuit.

Removed BOM tables and OMITs for new 4-pin WTB connector.
Reversed pinout of J4931 to match updated PCB footprint.
Added ESD protection diode on right USB port.
Various power supply R/C updates, plus some R/C adds.
Changed BSA bus pull-ups from 2K to 10K.
Added R8824 and R8827 for GPU memory configuration straps.
Corrected pinout at SATA/BT conn (J4960) to match flex.

Swapped PCIE Mini Card R2D/D2R connections at J5500.
Corrected net properties on R2/G2/B2 nets.
Swapped primary & alt part numbers for CPU VCore caps.
Changed C6455 to a smaller part for cost & MCO.
Power line width & neck reductions at PCB request.
Swapped some top & bottom EMC connections at DVI connector.
4214493
4293072
4286729
4290735
4235898
4214494
4272237
Simplified FireWire port power circuit for BOM consolidation.

Various BOM / connection changes at IMVP6 (CPU VCore).
Changed value of TPM Xtal caps.
Swapped trackpad & PCIe Mini Card USB connections.
(11.10.0)
Part moves & refdes changes to support sync with M9.
Changed GPU VCore supply enable to use 1.2V/2.5V S3 PGOODs.
Changed 2.5V S0 FET RC to 100K to slow down turn-on.
4229560
4214493
4214847
4248911
4295280
Removed Physical Security circuitry.

Cost reductions to GPU power supply circuitry.
Changed 0-ohm resistor to solder jumper.
Sync with M38 & M42.
Changed sleep LED connection per new SMC ERS.
4261313
4227308
4229560
4248911
4298899
4297684
4223808
4227320
4244539
4247941
4214493
4298905
4298943
4214494
Fixed pinout of USB D+/D- at camera connector to match FHB.

Inverted GPU VCore control, adjusted supply R values.
Moved GPU-related power alias from PP3V3_S0 to PP3V3_S0_GPU.
Adjusted line/neck widths, changed J4931 to 518S0371.
2005/10/13
2005/10/13
2005/10/14
2005/10/17
2005/10/17
4351196
4343202
4350840
4352020
4347845
4227340
4331670
4343864
4351181
4351196
4358831
4362404
4352020
4227340
4362566
4347845
Added 1K pull-down on IDE_RESET_L.

Changed RC value and net name for USB OC.
Swapped TMDS termination components for placement.
Changed 2.5V S3 supply inductor & compensation values.
Added pull-down resistors on LVDS interface.
Removed CPU VCore current sense input RC.
Added CRITICAL flags to some more parts.
Added EMI/ESD parts at camera connector.
Changed ITP connector BOM option.
Changed IDE_RESET_L pull-down from 1K to 15K.
Added pull-downs on two SB-to-SMC signals.
Changed TMDS diff term from 100-ohm to 180-ohm.
Changed 2.5V supply inductor to RoHS-compliant part.
Changed supply for 1.8V S3 current sense amp.
Restructured BOM for thick/thin PCB versions.
RPAK pinswaps to LVDS pull-downs for PCB layout.
2005/12/02
2005/12/02
2005/12/02
2005/12/02
4256256
4363848
4363870
4217524
Added BOMOPTION to R8801 to allow per-project control.

Removed M56 GPU die rev B13 support from BOM.
Removed M1a support from BOM.
Updated part number for J6430.
DMS Release #12000-13000 (DVT releases)

-
4375840
4235898
4362451
4375840
4290282
4347845
4391436
4362451
4362451
4362566
4394079
4362451
4362451
4402184
4362451
4362451
Synced 4 pages from mlb_dvt branch back to trunk.

Changes to LVDS net names to support mux option.
Added MAKE_BASE=TRUE to SMC 32KHz SUSCLK net.
Synced 1 page from mlb_dvt branch back to trunk.
Removed BOM table, changed L9455 to 155S0002.
Changed LVDS pull-downs from 10K to 8.2K.
Swapped N/P signal names on one portion of SATA_R2D.
Changed SCH/PCB/BOM part descriptions for Rev A.
Removed power jumpers and 0-ohm resistor.
Removed 920- number for thin PCB option.
Added BOMOPTION to SYS_ONEWIRE pull-up.
Removed power jumpers and 0-ohm resistor.
Restructured BOM tables to eliminate LeMenu.
Changed R7540 value for IMVP6 load-line improvement.
Added System Block Diagram, updated Power Diagram.
Changed BOM options for production SMC, BootROM.
4247941
4247941
4247941
4292633
4304248
Removed NO_TEST properties from CPU FSB strobe signals.

Spacing/Physical rule updates to match latest board database.
Restored NO_TEST properties, added EXPOSED_VIA properties.
Changed remaining 10K NTCs to new 5% part.
Updated GPU VCore / BBP voltages for B13/B24 support.
4310267
4310267
4235898
4310267
4310267
4310267
4298899
4322537
4345498
4235898
4235898
4227333
4345921
4346006
4343202
4346184
DMS Release #C000 (Ramp BOM Update)

2006/03/03
2006/03/03
2006/03/03
2006/03/03
2006/03/03
(D.0.0)
4457745
4457801
4466770
4399085
4424175
Added 128S0094 & 128S0095 as alternates for 128S0060.

Added 128S0081 as alternate for 128S0061.
Changed R7920 from 5% to 1% to reduce variation.
Changed C7532 from 10nF to 15nF to slow CPU slew rate.
Changed 8 VRAM strap resistors to enable ICT testing.
(11.1.0)
(11.2.0)
(11.3.0)
2005/11/16
2005/11/16
2005/11/16
2005/11/18
2005/11/18
2005/11/19
2005/11/19
2005/11/19
2005/11/19
2005/11/19
2005/11/19
2005/11/19
4235898
4298899
4227333
4235898
4235898
4346184
4347717
4350840
4229560
4350849
4340256
4292165
DMS Release #D000 (Ramp BOM Update)

Fixed ethernet reset net name on page 26.
Fixed single-pin nets caused by SMC net name updates.
Changed R4210 package size per M9 request.
Changed C9710 GND connection per M9 request.
Fixed location of SATA R2D common-mode choke.
Changed SMS self-test pull-up to pull-down.
Simplified TMDS filtering to allow movement of filter.
Changed FW chip back to REQ/GNT3.
Added option to connect SB_GPIO30 to ENET_LOM_DIS_L.
Changed topcase flex trackpad power from 3.3V to 5V.
Refreshed schematic symbol for U3750 (library update).
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
REV.
051-7099
SHT
NONE
Synced 4 pages from mlb_evt branch back to trunk.

Synced 2 pages from m9/mlb.
Removed unused platform reset gate.
Updated thru-hole SO-DIMM connector part number.
Updated Ethernet & FireWire crystal part numbers.
Aliased connection to ALS_GAIN to support M9 request.
Changed Yukon power rail neck widths per M9 request.
Updated SMC net names per ERS v1.2.1.
FUNC_TEST updates per test team request.
Updated J5500 pinout to match updated LIO board pinout.
Changed USB overcurrent switch to TPS2051B, added OC* RC.
Inserted common-mode chokes on SATA R2D/D2R pairs.
SCALE
DMS Release #B000 (PVT BOM Roll-In)
DMS Checkin #11001
(11.4.0)
2006/02/17 - 4449123 - Changed C7537: 4.7nF -> 47pF, R7537: 3.57K -> 4.42K.
(C.0.0)
DMS Release #08000-11000 (EVT releases)

2005/10/20
2005/10/21
2005/10/21
2005/10/26
2005/11/03
2005/11/15
2005/11/15
2005/11/15
2005/11/16
2005/11/16
2005/11/16
2005/11/16
2005/11/16
2005/11/16
2005/11/16
2005/11/16
Fixed documentation of battery address on I2C page.

Changed P1V5S0_RUNSS circuit to work properly in G3Hot.
Added GPUVCORE_PGOOD to 1.2V, 1.8V, & 2.5V S0 sequence.
Changed SMBus pull-ups to 4.7K.
Added notes for power supplies and connectors.
Net property & name changes to support PCB/ICT requests.

Combined RTC coin cell diodes into dual-diode package.
First implementation of Physical Security Guidelines.
Updated FUNC_TEST property for merged PBUS.
Changed FW PCI REQ/GNT pair for Physical Security.
GND line/neck/voltage properties updated per PCB request.
Moved signal alias to improve schematic reuse.
Updated L1970 (old part no longer exists in library).
Changed CPU VCore caps to proper production part number.
Replaced FDG6324L parts with FDG6332C for cost & supply.
Updated J4200 (old part no longer exists in library).
Thermal sensor BOM updates from Proto 2 MLB branch.
U6301 part number updated to M1 development BootROM.
DMS Checkin #11003
2005/12/07
2005/12/12
2005/12/12
2006/01/03
2006/01/03
2006/01/03
2006/01/03
2006/01/03
(13.1.0) 2006/01/03
2006/01/05
2006/01/05
2006/01/05
2006/01/05
2006/01/06
2006/01/06
2006/01/06
(B.0.0)
DMS Checkin #07009
DMS Release #05000-07000 (Proto 2 releases)

4247941
4248911
4214493
4229560
4256660
4229560
4247941
4235898
4214847
4227306
4234952
4239505
4274915
4274915
(11.9.0)
2005/10/13 - 4247941 - Unswapped pins at trackpad ESD protection diode.
2005/09/06 - 4240486 - Removed NO_TEST property from GPU HSYNC and VSYNC.
2005/09/06 - 4246683 - Removed NO STUFF option from R8805 per ATI request.
2005/09/06 - 4232534 - Fixed label BOM tables to call out proper EEE #s.
DMS Checkin #07008
DMS Checkin #04007
2005/09/08
2005/09/08
2005/09/08
2005/09/08
2005/09/16
2005/09/16
2005/09/19
2005/09/19
2005/09/20
2005/09/21
2005/09/21
2005/09/26
2005/09/26
2005/09/26
2005/11/21
(11.5.0) 2005/11/21
2005/11/22
(11.6.0) 2005/11/22
(11.7.0) 2005/11/28
2005/11/30
2005/11/30
2005/11/30
2005/11/30
2005/11/30
(11.8.0) 2005/11/30
2005/12/01
2005/12/01
2005/12/01
2005/12/01
2005/12/01
Updated SATA connector pinout to match latest flex.

Deleted unnecessary MCH TVDAC filtering.
(13.2.0) DMS Release #A000 (PVT Release)
Changed SB GNT3#/GNT4# back to test points.
2006/01/21 - 4412882 - Changed R7623 from 1.33K to 931 ohms.
Changed stuffing option to disable PLT_RST gating.
(A.1.0) 2006/01/21 - 4414757 - Changed 138S0552 to 138S0580 & 138S0553 to 138S0581.
Split FW323 VSSA from VSS to reduce noise.
2006/01/26 - 4420815 - Changed 2x 128S0077 to 128S0068.
Power supply changes per vendor feedback.
(B.0.0) DMS Release #B000 (PVT BOM Update)
Updated SB pin name for GPIO 5 (ODD_PWR_EN_L).
Retasked FET to control 3.3V S0 FET from GPU VCore PGOOD.
2006/02/09 - 4440116 - Pulled new schematic part number (051-7099).
Added properties to resolve a PCB constraint issue.
2006/02/09 - 4440116 - Restructured BOM for 3 CPU configs.
Consolidated 0.22uF caps in design.
2006/02/09 - 4440116 - Updated BootROM / SMC part numbers.
Changed ethernet VMAIN_AVLBL connection.
(A.0.0) DMS Release #A000 (Ramp Config Update)
Replaced last remaining non-RoHS compliant connector.
Implemented circuit to power down ethernet in S3 on battery.
2006/02/13 - 4420815 - Changed remaining 128S0077 to 128S0086.
2006/02/13 - 4420815 - Added 128S0077 as alternate for 128S0086.
DMS Checkin #07007
2006/02/13 - 4437189 - Changed R7757 to 1Mohm & R7770 to 100K.
2005/10/13 - 4247941 - Swapped pins at trackpad ESD protection diode.
(A.1.0) 2006/02/13 - 4431947 - Removed NO STUFF option from C3309.
DMS Checkin #04006

2005/09/03
2005/09/03
2005/09/03
2005/09/03
2005/09/03
Changed fan CTL series Rs to 2N7002 level-shifter.

Deleted placeholder connector, grew HDD connector for IR.
BOM option change to stuff right USB ESD protection part.
Added ESD protection on top-case USB port.
BOM restructuring per EVT build plan.
Changed IMVP6 10K NTC from 10% to 5% part.
DMS Checkin #07006
DMS Checkin #04005

-
DMS Checkin #07005
2005/08/31 - 4227328 - Changed EMI caps from 50V to 16V to fid in ESD protection.
2005/09/02
2005/09/02
2005/09/02
2005/09/02
4256409
4261313
4281394
4227330
4286888
4292633
4248911
2005/10/10 - 4232826 - Swapped Vtt RPAK functions to optimize layout.

2005/10/10 - 4247941 - Net property updates found via back-annotation.
DMS Checkin #04004
- Radar # - Description
DMS Checkin #11002
Added 2.2uF caps on SO-DIMM VREF pins.

Adjusted P5VS5_PGOOD Rs, added cap on PM_RSMRST_L.
Swapped Vtt RPAK functions to free up unnecessary part.
Added placeholder connector for IR FFC connector.
Changed GPU BBN supply to MAX1673.
Added CRITICAL flags to parts identified in scrub.
C1001 stuffing change from Proto 2 MLB branch.
DMS Checkin #07004
Changed J8200 to proper 6-pin part.

Changed MEM_ODT* from RPAKs to discrete Rs.
Changed R6430 from 4.5K to 3.5K.
Changed LIO 5V S3 to 5V S5.
Changed 3.3V S5 sequence to follow 5V S5 PGOOD.
Changed Y5920 to 197S0169.
Resolved sync issues with M38 (SB page 21).
Sync page 44 with M42 to fix FW power net S-states.
Resolved sync issues with M38 (SMC page 58).
Changed U5900 to resolve ROHS issue.
DMS Checkin #04003

2005/08/31
2005/08/31
2005/08/31
2005/08/31
2005/08/31
2005/08/31
2005/08/31
DMS Checkin #07003
DMS Checkin #04002

2005/08/30
2005/08/30
2005/08/31
2005/08/31
2005/08/31
2005/08/31
2005/08/31
4221965
4278828
4232826
4261313
4282162
4248911
4282349
4274915
Date
DMS Checkin #07002
DMS Checkin #04001

2005/08/29
2005/08/29
2005/08/29
2005/08/29
2005/08/29
2005/08/29
2005/08/29
2005/08/29
2005/08/29
2005/08/29
2005/08/29
2005/08/29
DMS Release #03000 (RFA #394758)

Changes from Proto Branch (DMS Release #04000):
100
OF
D
104
8
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
FSB_BREQ0_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DPWR_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_RS_L<2..0>
FSB_TRDY_L
FSB_CPURST_L
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB
FSB_D_L<63..0>
FSB_DINV_L<3..0>
FSB_DSTBP_L<3..0>
FSB_DSTBN_L<3..0>
FSB_55S
FSB_55S
FSB_55S
FSB_ADDR
FSB_ADDR
FSB_ADSTB
FSB_A_L<31..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<3..0>
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_27P4S
CPU_55S
CPU_27P4S
CPU_2TO1
CPU_2TO1
CPU_2TO1
CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
FSB_IERR_L
FSB_FERR_L
CPU_PWRGD
CPU_INTR
CPU_NMI
CPU_A20M_L
CPU_DPSLP_L
CPU_IGNNE_L
CPU_INIT_L
CPU_SMI_L
CPU_STPCLK_L
CPU_THERMTRIP_L
PM_DPRSLPVR
IMVP_DPRSLPVR
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
CPU_55S
CLK_FSB_100D
CLK_FSB_100D
CPU_55S
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
XDP_BPM_L<5..0>
CPU_XDP_CLK_P
CPU_XDP_CLK_N
ITPRESET_L
CPU_55S
CPU_55S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_2TO1
CPU_2TO1
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VID<6..0>
CPU_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
THERM
THERM
7
5 7 12
5 7 12
7 12
5 7 12
NET_TYPE
SPACING
PHYSICAL
MEM_CLK
MEM_CTRL
MEM_CMD
MEM_DATA
MEM_DQS
MEM_70D
MEM_45S
MEM_55S
MEM_55S
MEM_85D
FB_CLK
FB_ADCTRL
FB_ADCTRL
FB_DATA
FB_75D
FB_35S_TO_55S
FB_55S
FB_40S
LVDS
TMDS
VGA
LVDS_100D
TMDS_100D
VGA_75S
PCIE
DMI
PCIE_100D
DMI_100D
SATA
IDE
SATA_100D
IDE_55S
USB2
ENET
FW
USB2_90D
ENET_100D
FW_110D
SMB
SPI
SMB_55S
SPI_55S
CLK_FSB
CLK_PCIE
CLK_MED
CLK_SLOW
CLK_FSB_100D
CLK_PCIE_100D
CLK_MED_55S
CLK_SLOW_55S
5 7 12
7 12
7 12
5 7 12
5 7 12
5 7 12
5 7 12
7 12
7 12
7 11 12
5 7 12
5 7 12
5 7 12
5 7 12
5 7 12
5 7 12
5 7 12
7 21
7 21
7 21
7 21
7 21
7 21
7 21
7 21
7 21
14 23 57
57
7
7
7
7
7
7 11
11 34
11 34
11
8 9 79
8 9 79
8 57
8 57
57
57
I70
I71
I72
I73
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
SB_ACZ_BITCLK
ACZ_BITCLK
SB_ACZ_SYNC
ACZ_SYNC
SB_ACZ_RST_L
ACZ_RST_L
ACZ_SDATAIN<0>
SB_ACZ_SDATAOUT
ACZ_SDATAOUT
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA_P<5..3>
TMDS_DATA_N<5..3>
TMDS_DATA_P<2..0>
TMDS_DATA_N<2..0>
TMDS_CLK_F_P
TMDS_CLK_F_N
TMDS_DATA_F_P<5..3>
TMDS_DATA_F_N<5..3>
TMDS_DATA_F_P<2..0>
TMDS_DATA_F_N<2..0>
21
5 21 45
21
5 21 45
21
5 21 45
5 21 45
21
5 21 45
73 74 75
73 74 75
73 74 75
73 74 75
73 74 75
73 74 75
75
75
75
75
75
75
M1 Net Properties
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7099
104
OF
D
104

051-7099 M1

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051-7099 M1

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8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

428208PRODUCTION RELEASED 03/04/06

DIMENSIONS ARE IN MILLIMETERS

Apple Computer Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

Left I/O &

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

APPLE COMPUTER INC.

ODD_PWR_EN_L (SB GPIO14)

Power Block Diagram

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE COMPUTER INC.

NOTICE OF PROPRIETARY PROPERTY

Bar Code Label / EEE #s

IC,EFI,BOOTROM DEVELOPMENT (NEW),M1

IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

IC, TPM, 28-PIN TSSOP

IC,CPU VOLTAGE REGULATOR,IMVP,TWO PHASE

IC,CY28445-5,CLOCK GEN,68PIN QFN

7mOhm alt for 8mOhm

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

Functional Test Points

Left ALS Connector

Misc EXPOSED_VIA Nets

Thermal Diode Connectors

Left I/O Data Connector

LPC+ Debug Connector

EXPOSED_VIA property indicates that the net

FUNC_TEST property removed

CPU FSB NO_TESTs

Battery Digital Connector

Left I/O Power Connector

Other Func Test Points

Request for at least 10 GND test points

NOTE: 10 additional GND test points are

Current Sense Calibration

Functional / ICT Test

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

APPLE COMPUTER INC.

USB Port "A" (Debug Port) = Right USB 2.0 Port

USB Port "C" = Left USB 2.0 Port

USB Port "D" = Camera

USB Port "E" = ExpressCard

USB Port "F" = IR Receiver

Ethernet Power Management Support

USB Port "B" = Trackpad (Geyser)

NOTE: NB_CFG<13..12> require test access

USB Port "G" = Bluetooth (M13P)