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Chapter 6:
D
R
A0
D
R
A1
I2
D R
A2
I3 CLK Reset
A3
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Registers
CLK
I3 I2 I1 I1 I0
D
R
A0
D
R
A1
I0
A3 A2 A1 I2
D R
A2
I3 CLK Reset
A3
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Registers with Parallel Load Control Loading the Register with New Data
D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
R E G I S T E R LD
LD 0 1
Q(t+1) Q(t) D
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Registers with Parallel Load Should we block the Clock to keep the Data?
D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 I0 I1 I2
Delays the Clock
R E G I S T E R LD
D D D
Q Q Q
A0 A1 A2 A3
I3
Load CLK
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I0 I1
I0 MUX Y I1 S
A0
I0 MUX Y I1 S
I0 MUX Y I1 S
A1 A2
I2
I3
I0 MUX Y I1 S
A3
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Load
CLK
Serial SI Input
SO Serial Output
CLK
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Shift Registers
SI Q3 D Q D Q Q2 D Q Q1 D Q Q0 SO
CLK CLK
SI
Q3 Q2 Q1 Q0
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Serial Transfer
SI Clock Shift Control Clock SO SI
Shift Control
CLK
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Serial Addition
Shift Control SI Shift Register A x y FA S C z Q D
CLK
Shift Register B
CLR Clear
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Serial-in Serial-out
Serial-in Parallel-out Parallel-in Serial-out
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Q
CLR CLK S1 S0
Q D
Q D
Y S1 S0 MUX I3 I2 I1 I0
Q D
SI for SR
D3
D2
D1
D0
SI for SL
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Mode Control S1 S0 0 0 0 1 1 0 1 1
T 1
T 1
T 1
CLK
CLR CLR
CLR
CLR
CLR
CLK
Q0 Q1 Q2
Q3
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Ripple Counters
Q3 Q2 Q1 Q0
Q Q CLK
Q Q
Q Q
Q Q
D CLK
Q0
Q1 Q2 Q3
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1001
1000
0111
0110
0101
Q3
Q Q J K 1
Q2
Q Q J 1
Q1
Q Q J K 1
Q0
Q Q J 1 CLK
K 1
K 1
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Decades Counter
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
Count (CLK)
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Q3
Q2
Q1
Q0
Enable
Q Q
J K
Q Q
J K
Q Q
J K
Q Q
J K
To Next Stage
CLK
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Up
Down
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BCD Counter
0 0000 1 1 0 0001 1 0 0010 1 0 0011 1 0 0100 1
1001
0
1000
0
0111
0
0110
0
0101
0
Q3 Q2 Q1 Q0 E
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BCD Counter
0 0000 / 0 1 1 0 0001 / 0 1 0 0010 / 0 1 0 0011 / 0 1 0 0100 / 0 1
1001 / 1
0
1000 / 0
0
0111 / 0
0
0110 / 0
0
0101 / 0
0
Q3 Q2 Q1 Q0 y E
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CLR 0 1 1 1
LD x 0 0 1
Count x 0 1 x
I3 I2 I1
Q3 Q2 Q1
I0
LD Count CLR
Q0
LD 0 0 0 0 Count
I3
I2 I1 I0
Q3
Q2 Q1 Q0
A3 A2 A1
A0
Count
CLR 1
CLK
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Ring Counter
0001 0010 0100 1000
T3 T2 T1 T0
CLK T0
2-to-4 Decoder
T1
T2
2-bit counter
T3
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Johnson Counter
0000 0001 0011 0111
1000
1100
1110
1111
Q3 Q Q D
Q2 Q Q D
Q1 Q Q D
Q0 Q Q D
CLK
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Homework Mano
Chapter 6
6-2 6-3 6-4 6-13 6-14 6-16 6-18
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Homework
6-2 Include a synchronous clear input to the Register with Parallel Load. The modified register will have a parallel load capability and a synchronous clear capability. The register is cleared synchronously when the clock goes through a positive transition and the clear input is equal to 1. What is the difference between serial and parallel transfer? Explain how to convert serial data to parallel and parallel data to serial. What type of register is needed?
6-3
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Homework
6-4 The content of a 4-bit register is initially 1101. The register is shifted six times to the right with the serial input being 101101. What is the content of the register after each shift?
6-13 Show that a BCD ripple counter can be constructed using a 4-bit binary ripple counter with asynchronous clear and a NAND gate that detects the occurrence of count 1010.
6-14 How many flip-flop will be complemented in a 10-bit binary ripple counter to reach the next count after the following count: (a) 1001100111 (b) 0011111111 (c) 1111111111
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Homework
6-16 The BCD ripple counter has four flip-flops and 16 states, of which only 10 are used. Analyze the circuit and determine the next state for each of the other six unused states. What will happen if a noise signal sends the circuit to one of the unused states? 6-18 What operation is performed in the up-down counter when both the up and down inputs are enabled? Modify the circuit so that when both inputs are equal to 1, the counter does not change state, but remains in the same count.
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