Total No.

of Pages: 2 Register Number: Name of the Candidate:

7046

P.G. DIPLOMA EXAMINATION - 2010

(VLSI DESIGN)
(PAPER II)

120. ASIC DESIGN

December) Maximum: 100 Marks Answer any FIVE questions. 1. (a) Discuss the difference between LSI and MSI Elements. (b) Explain the design of Decorders and Demultiplexes. 2. (a) Implement a Full adder using appropriate Multiplexer. (b) Explain the usage of mixed logic as a design tool. 3. (a) Design a Mod-6 counter using state table reduction method. (b) Differentiate Algorithmic State Machine and Mealy & Moore models. 4. Convert the Moore state diagram given below into an equivalent ASM chart. (Input x1x2, output z1z2) (5 20 = 100) (5) (15) (8) (12) (16) (4) (20) (Time: 3 Hours

5. Explain the architecture and operation of different types of ROM.

(20)

6. (a) Give the general Architecture of FPGA. (5) (b) Explain how a logic function can be implemented using gate array with an example. (15) 7. What is meant by Process in VHDL? Explain process. (i) using Variables; (ii) using Signals. (20)

8. (a) Design a full subtractor and write the VHDL code for a full substrater using logic equations. (14) (b) Write the VHDL description to design a D Flip Flop. (6) 9. (a) Explain the significance of timing simulation in the ASIC design flow. (b) Explain the Hazards and the method to eliminate it in the digital logic circuits. (10) (10)

10. Explain how the micro timing diagram is produced for the logic circuits with an examples. (20) %%%%%%