CAD tools from Cadence for top-down and bottom-up design methodologies: 1. VHDL/Verilog (Design capture) 2.

NC-VHDL/NC-Verilog (Simulation) 3. BuildGates (Logic Synthesis) 4. Design Planner and P ! (Floor planning) ". !ili#on $nse%&le ( lacement and !outing) '. Design (or testa&ilit). *. Design (or signal integrit). +. Pearl ("iming closure) ,. $n-isia (Cloc# tree generation)
1..

H)/er$0tra#t ( arasitic e$traction)

11. Dra#ula (D!C) Standard-cell library from Artisan A %&'(-micron C)*S process from "S)C