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9

 (Workshop on Layout Technology)

Digital Chip Testing with Agilent 93000 SOC Series ()


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Digital Chip Testing with Agilent 93000

SOC Series ()
TUVW$ J
jbchen@cic.org.tw

p
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CIC @   Agilent 93000 SOC Series
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IC  T U DUT boarde DUT interfacee testhead & channel board
j + manipulator testhead&   support
rack  M
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- 3-

Manipulator
DUT Board
DUT Interface

Support Rack
Testhead

1 Agilent 93000 SOC Series

D
K Agilent 93000 SOC Series

} Test Development Flow

1. < w

&  1  n ! IC & w 2 y % test plan

design a DUT board pin configuration level setup timing setup vector
setup testflow setup testing the devicex  result analysis   +
 A{ . c  M
+  nIC  @ test plan7 8 D c p &
' functional & scan pattern& power dissipation
} design a DUT board &  T U DUT board k
ICx testhead &pogo pin j + m c  nIC CIC
@ d e &8IC package (DIP48PLCC68PLCC84CQFP100CQFP128
CQFP144 CQFP160 CQFP208) ' % & DUT board x & 
&1&45 n
& <  pin configuration T k IC signal pin&
x  signal pin j test channel ' & device power
supply& $ e % k IC
level setup T power supply&voltage current limit&
 & drive voltage (VIL VIH) compare& voltage
threshold (VOL VOH) ; timing setup o p T
& x  system cycle&
S  (period time)  vector
setup  p &   T Uwaveform & T  % + &

- 4-

vector

testflow setup p & T % w

testing the device  n  1 .   @ \  M & T
 d k IC ?   .  k IC  d &response e
S
& responseM 3 3 ? <  U (PASS) # ? <  ' 
 (FAIL)  result analysis  & & timing
diagram & error map _  '   & shmoo plot
k IC& + 1
Device Under Test (DUT)
PASS

Test
Plan

Choose
or
Design
a DUT
Board

Pin
Configuration

Level
Setup

Timing
Setup

Vector
Setup

Testflow
Setup

Testing
the
Device

FAIL

Result Analysis Tool

-Timing Diagram
-Error Map
-Shmoo Plot

<w

 Design a DUT Board

1. CICd e &DUT Board
CICd e8IC  I '  1 &digital channel   Z320 ! m d e

& DUT boardy ' 

D x  j testhead&  K 3
DIP48CQFP128eCQFP144 packageM + ? KDUT boardPLCC68
PLCC84e CQFP160M + ? K DUT board CQFP100e CQFP208M + ?
K DUT board DUT board (loadboard)  ' package& pin count 
# .  U320 m x  DUT board& 2 I '  d p
& IC power pin&  ! #  ! m + DUT board T U j
IC& power pin j  1 & device power supply j & ! +
DUT board& 
\ 4

SB48, CQFP128, CQFP144

LCC68, LCC84,CQFP160

CQFP100, CQFP208

3 DUT board

- 5-

4 DUT boardj

Software Overview
1. Software Overview

 1 & 4 5 q SmarTest 5  ' & T

pin configuration level setup timing setup vector setup testflow setup
testing the devicex  result analysis  + SmarTestA  n T  %
 1   T &  d e k IC  3 k
IC  d & response  SmarTest &  q offline modee
online mode online mode ' j  1 x  n offline mode c
  n T # c  n  q offline mode&  q unix%>
HPSmarTest o &  qonline mode&  qunix%> HPSmarTest &
Test Plan &
Design a DUTLoadboard

SmarTest
Pin Config

ASCII
data

ASCI
I Interf
ace

Design
Translation
STIL, WGL

ScanConverter

Levels
Timing
Testflow

Vectors
Testfunction

Pass/Fail
Analysis

5 SmarTest Overview

- 6-

 q SmarTest x  X .  main toolbar report

windowx  operation control window 6 main toolbaro p & '
 & M \ report window r  ' &logx 
operation control window T &    ?   M  
+ report windowA r  & logx 
A tester
state @   ' j  1 tester operation @  1 J +  n
&  M  SmarTest &  q +main toolbar File Quit x 
+   @ 7 Q p  M & T pin configurationlevel setup
!

6 SmarTest Start-up Screen

+main toolbar (7 )'8tabs tabs( ' # ? &buttons & M # ?

& T main toolbar& " # ' 4 $ & buttons .  connect
disconnect breakx  change device connect & j  1 & AC
relay disconnect & f %  1 & AC relay break & & ' IC&
change device & f #? &IC s( k &IC

Tabs
Buttons

Change
Device
Break
Disconnect
Connect

7 SmarTest Main Toolbar

- 7-

)pn<cs( *+
change device . + 8& \ +Device, ! A - q
Create . + " . & X + PPU tester model, !  P600
create device . +  (  d device directory + device
directory( . ' / [ & 
configuration/ levels/ timing/ vectors/
+ # ? &  A # ? & T 0 1 pin configuration& T
0 1 <  + configuration/  power supply& voltage &
T 0 1 <  +levels/  (  kdevice x  n
pin configuration

8 Create Device

 ' & T x T U data manager  n ] main toolbarA

& data manager2 3 . + data manager4 \ 9 data managery
%  4 \ Program pageSetup page x Result page p f 4 \
>  Select Programf Program page Select Setupf Setup
pageSelect Resultf Result page  nIC   p M & T
+Setup page M

9 Date Manager Setup Page

- 8-

2. Pin Configuration

p  n pin configuration + data manager& setup page

Config Icon 10 j File Load  IC & &  
template0 1 I ' CIC d e & DUT board package & 
pin j  1 & test channel 3 $ ! m CIC x D c d e
 & template0 1 m  d  5 6 & x  &
2  7 q  7 + # & 8 9 : m  j  1 & test
channel

10 Defining the Pins

 %  x main toolbarA pin configuration& button +

data managerA ; Config Icon . + pin configuration X

11 pin configuration X % } MONITOR Modee

EDITOR Mode  ' + EDITOR Mode x  n f &  
Mode editor x  q EDITOR Mode  q EDITOR Mode x
5 6 p 5 6 & < pin name, ! 6 q &
(= & = > ? 5 16 x ) }  type, !    7 q k
IC typeq i k IC d & 7 + response typeq o q bi-directional&
I/O typeq io   pin numberq @ ' & & pin x  VDD
VSS& pinA A &  q B +  p A & C  Edit delete
line... . + :  p A D n & X - q n  delete2 3
A p 5 6 & E device power supply d e & T
  DUT board & T  & & - q pin
configuration&test channel, !  %  "  &Download2 3 F
x data manager&Config Icon. % G ' H I J 8 T
' 6 ! m p data manager"  & Save2 3  n ! ( 12

- 9-

Config

11 Pin Configuration

12 Pin Configuration

+pin configurationA p M & T  K & L $

K L $  M T (levelstimingvector)& N ? p O & + # ? &
J'TqL$P+MTAxjL$
# & . K L $ &  +pin configurationX
A  Select groups.... + Pin Group Definition& X ( 13)
new atomar definition2 3 . + Digital Pin Group Definition& X (
14) + J X A x  p T + ? L $ & k
copy2 3 + X & "  x @ p T L $ & '

- 10-

  & MSB (  & LSB   +groupname, ! q L $ (  &save2 3 . Q Pin Group Definition& X

} x & L $   & ? &   n K  ' p T &group 
%  + Pin Group Definition& X (  & done2 3 m  data
manager&Config Icon. % G ' H I J 8 T ' 6 ! m p
data manager" &Save2 3  n!

13 Pin Group Definition Window

14 Digital Pin Group Definition Window

3. Defining the Levels

Level Setup T &drive voltage (VILVIH)
compare& voltage threshold (VOL VOH)

- 11-

15
16 x  power

supply& voltage current limit&    power& setup timeT

' R power& T 17 T &   + data manager&

setup page Level Icon 18 + Level Icon(  - q ! & 0
j ; data managerALevel Icon. + Level Setup& X x
 n T T &  19 x &Level equation editor
T Level equation set level equation setA x & SPECSx 
EQUATIONS K x  N S T DPSPINS & K &
 w  LEVELSET  & K & VIH VIL VOH VOL
+ SPECSA  K &  & Level Spec Tool N  [

20 level equation set& U & J U V / 19& 

<x78&K+JUAKr}
COREPWe IOPW . 8 core power& x  io pad power&
EQUATIONS S T +VIHVILVOHx VOL & N F
+ LEVELSET 1F A T all_insJ pin groupx  clkJ pin& vile vihT
N q VILe VIHJ } & N (! q + pin configurationA ' D c T L
$ ! m + level setup x j L $ ) 
io_pinsJ
pin groupT vil vih vol voh& T N all_outsJ pin groupT
vohevoh&T N

High Level vih

Drive
Levels
Low Level vil

15 Drive Levels

Logic 1
voh
Intermediate
vol
Compare Levels
(Thresholds)
16 Compare Levels

- 12-

Logic 0

Internal
Setup
settling time Time

t_ms
Power Supply Voltage
vout
Connect Current Limit
ilimit
Disconnect Stage:
offcurr =min, act

17 DPS Voltage and Current Limit

18 Level Setup Window

Level Equation Editor

Level Spec Tool

LEVEL EQN SET n

LEVEL EQN SET 2
LEVEL EQN SET 1

SPECS
<spec1>
<spec2>

<speck>

LEVEL SPEC SET 1

SPECS
<spec1> = 4.5 V

<speck> = 0. 5V

LEVEL SPEC SET 2

SPECS
<spec1> = 4.8 V

<speck> = 0. 2V

EQUATIONS

DPSPINS

LEVELSET 1

...
LEVELSET k

19 Level Setup Architecture

- 13-

EQNSET 1 "levels equation set"

SPECS
COREPW [V]
IOPW
[V]
EQUATIONS
VIL =
VIH =
VOL =
VOH =

0
IOPW
0.2*IOPW
0.8*IOPW

DPSPINS
corevdd
vout = COREPW
ilimit = 1000
t_ms = 4
offcurr = act
DPSPINS
iovdd
vout = IOPW
ilimit = 1000
t_ms = 4
offcurr = act
LEVELSET 1 "no termination"
PINS all_ins clk
vil=VIL
vih=VIH
PINS io_pins
vil= VIL
vih= VIH
vol= VOL
voh= VOH
PINS all_outs
vol=VOL
voh=VOH
20 Level Equation Set Example

20 U A & J T + Level Equation EditorA  n z

Level Equation Editor&   + Level SetupX A  Select Edit
Equations W X W   T & viM 6 CIC 3 6 % & nEdit
21 + nEditA keyword.  % # ? & Y   %  + nEditA 
Shell LEVEL Download Equations download + data managerA
Level Icon. % G ' H I J 8 T ' 6 ! m p data
manager"  &Save2 3  n !

- 14-

*21 Level Equation Editor

 level equation set    

 SPECS      
        Spec Tool    Spec Tool      Level
Setup ! " #Select Edit Specifications %  & ' ( ) *22 

*22 Select Level Equation Set

" #level equation set  + "create, - & ' (Create level spec set 
) * 23  Create level spec set 
" # Set number 
Description. / 0 1 2 3 %  + "create, - 4 & ' (Spec Tool 
(* 24)  Spec Tool 
! 4 & ' (
  SPECS  5 6 
Actual . / 0 1     7 1 8 9   " # File Download
download   data manager! Level Icon& 9 : ;  < = > ? @ A B

  C D E F + " data managerG H   Save, -    I J 6
? L M N  O P 5 6 Q ( R S  T U V L SPECS  W X Y A core

- 15-

power
    io pad power
    Spec Tool

     
1.8 V3.3 V   
vil=0 Vvih=3.3 Vvol=0.66 Vvoh=2.64 V

    CIC    
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'  (

) * +
CIC eNews , - .   / .
$ % &  0 1 timingvector
34 5   6 7 + 8

3
1

4
2

923 Create Level Spec Set

924 Spec Tool

- 16-



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- 17-

95~U18<j C D (k } 94~922)
CD
_ CIC D ~ (95~ ) < j UMC 0.18um Mixed Signal/RF CMOS
1.8V/3.3V Process(' U18)) v w , 95~5  , [
<jfg>7)vnow<jrno&
a 95~5  q N O ) v ) v } j 95~ : ; < =
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s UMC Mixed Signal/RF CMOS 1.8V/3.3V process TSMC 0.18um CMOS
Mixed Signal/RF General Purpose MiM Al 1P6M 1.8V/3.3V process(' T18)
[ T18n o & Artisan Cell Library _
U18X  t < j T18< = s  & t
X  TSMC 0.13um CMOS Mixed Signal General Purpose MiM Cu FSG 1P8M
1.2V/2.5V process
3q 7  )
 
U18 n o 7    
ycchen@cic.org.tw 03-5773693ext.201 
T18 n o 7  ' 
thchien@cic.org.tw 03-5773693ext.202 
T18 Cell Library 7   
saho@cic.org.tw 03-5773693ext.193  
U18 Cell Librar y 7    
cplin@cic.org.tw 03-5773693ext.163  

:;TSMC 0.18um) v ? B(k } 94~610)

CD
1. DRC Error
CIC   Calibre v2004.1_2.15    d    qCalibre d

/       [ !Design Rule`  " " # $Layout % h

Error Free 7  CICn o & j ' ( ) j * 3 + , [ D -  " "
DRC Error7  )j * . / 7 0 15 2 ] 3! !
DRC Command file versionT18_Calibre_DRC_13A25C_Modify
TSMC 0.18um Calibre DRC False-error
Rule name

Cause

OD.C.1
OD.C.2_OD.C.3
I/O PAD ERROR STC18io_18T
OD.C.5
RPO.S.1

- 18-

RPO.C.3
RPO.C.6
NW.S.1
NWR.E.1
NWR.C.3
OD.C.1
OD.C.2_OD.C.3
OD.C.5
I/O PAD ERROR STC18io_33T

RPO.S.1
RPO.C.3
RPO.C.6
ESD.GUIDE.4
ESD.5E
ESD.5F
ESD.5G
ESD.5E

TSMC I/O PAD ERROR

PO.W.1.MM
CTM.R.2
M6T.E.2
M6T.C.1
M6T.E.3
M6T. I .1
M1.A.1
PO.R.1
mos.01.LAT.3

CTM density is not enough

for capacitor
Min extension of M6T region beyond VIA5 at the end of M6T is 0.45um
for mimcap5
INDDMY  Meyal 6 567 50um
for inductor
No Via and metal layers inside INDDMY region
for 3D-inductor
Minimum area of M1 region < 0.202um*um 8
for resistor
P-cell(moscap_g3, moscap_g6)9:8
for varactor
(; SNominal Vt MOS <q= Body >
for mos

- 19-

2. Hierarchical vs. Flat

Hierarchical
 % d 9
AM.W.1.M5!
* J   } Hierarchical 5   sCICK L \Flat
  
` } 7 Flat  5 / ! !

H MEMS Interferometer Measurement SystemA B> 7

(k } 94~919)

CD
1 9 19 ? CIC  @
MEMS Interferometer Measurement SystemA B >
7MEMS Interferometer Measurement System0 1  DU V
:
1. White light Interferometer(Optical profiler)
2. MEMS Motion Analyzer

no>7  F B  7 )" Q R dG:

http://www2.cic.org.tw/chip_test/mems/index.htm

- 20-