Documente Academic
Documente Profesional
Documente Cultură
9
(Workshop on Layout Technology)
Digital Chip Testing with Agilent 93000 SOC Series ()
(94830)
!"#$
% (9495)
'P15-94B()
(9499)
*95+U18
,-./01 (94922)
234 56TSMC 0.18um78(94610)
9
9 f $/
915-
11! " # $ % & ' 9 15 ( )
+,-.,/0123456780-9$:;<$=>?(@
ABCDEFGHIJKLM$NOP$=QRS=TUVW$
XYZ[$=\]^_`a5bcde9f$ghi[$= ?h
jkmnopHqrs1t,@u-99vwx
yz{ , ^ | +SoCT U } ~ <
c"#@.I9f$bcd
M&O5AB %
P$
W e j & " # ICT U w e
JKLM eABo
"#+AB?h( CDr
Cn+"#ABo/
(&
"#O5
"#eAB "#CDAB
ov
- 1-
(Workshop on Layout Technology)
9 f $/
IABe-9
./,
v&
9 ^ . (Workshop on Layout
Technology) ' 9 24 ,
v
e,.n
FGrog[oe
[o o .
JKLM$
S=x9TUy
q<8+.e #
n
I ' + ICT U A
& ? ICT U % &
!"E+#?$&%&}~
'(&9p)*
<&+,
-9^.+./0123T
U RFT U e 9 (MEMS) 4 5
6 TFT/LCD DRAM7 8 @ f 9 :
;%&}~<TUe9=
> L M 3 ? @ & | A (i Y - 9 -N
B C D = E - F S = G H
-I J K 3 ] ) e | L O ( A B -
S =
e v -M N O P ) M B Q R e
vwxSTUVfW&XYZ
TU}~ [
\ ]
Ce9^. #
[
A B J K L M $-
S =
' 9 ^ . (Workshop on
Layout Technology) x
9TUy q<
8
^B_`abI9^.
n c d e e . # f g h i S=e # <9
n
j&Fk.?S*|LO+lmn
o
,cq^<pqrs&t
uvEdK{,@u9wxy?z
{ 1 | % q } ~ s &
- 2-
p
I ' A B ' J K o IMS ATS200 & Z 10-
*|deFkVWqrd,|TUAB(
J K x < A B '
2004- Agilent
93000 SOC Series /
T 1 + q $ 6 T U
# ? 2 . &IC # ? & $ Z + 1 < x *
* &IC r !IC / ICeSoC o J K + m T
AB
s&JKde*|VFkJK
5AB&/
Tcx
&mT
n ! J K M
CIC @ Agilent 93000 SOC Series
T
D
1 A testhead q ' channel board ! k &
IC T U DUT boarde DUT interfacee testhead & channel board
j + manipulator testhead& support
rack M
6 CIC @ & $ c
( + ! $ A & data channel Z 320 E channel&
data rate V Z 660Mbps ' vector memory& channel '
28MVectors M qscan & I 'scan pattern&waveform 6
! m channel& scan memory& 84MVectors ' 2
3 & Instrument y ' 4$ } $ q Arbitrary Waveform Generator (AWG)
xd23&/23&JK}$q
Digitizer x / 2 3 J K d & 2 3 n
E Q p & AWG& . q 16bits resolution
30Msps sampling ratex 12bits resolution 500Msps sampling rate
Digitizer& . q 16bits resolution 3MHz bandwidthx 12bits
resolution 100MHz bandwidth d e k IC & $ y ' 8$
? d 8 # ? & k IC $ & q 7V&
x 6A& w 1 & c R M ! m 5 c
& m 1 !IC n n +
Mm 1 n!IC
- 3-
Manipulator
DUT Board
DUT Interface
Support Rack
Testhead
- 4-
vector
Test
Plan
Choose
or
Design
a DUT
Board
Pin
Configuration
Level
Setup
Timing
Setup
Vector
Setup
Testflow
Setup
Testing
the
Device
FAIL
<w
LCC68, LCC84,CQFP160
CQFP100, CQFP208
3 DUT board
- 5-
4 DUT boardj
Software Overview
1. Software Overview
SmarTest
Pin Config
ASCII
data
ASCI
I Interf
ace
Design
Translation
STIL, WGL
ScanConverter
Levels
Timing
Testflow
Vectors
Testfunction
Pass/Fail
Analysis
5 SmarTest Overview
- 6-
Tabs
Buttons
Change
Device
Break
Disconnect
Connect
- 7-
)pn<cs(
*+
change device . + 8& \ +Device, ! A - q
Create . + " . & X + PPU tester model, ! P600
create device . + ( d device directory + device
directory( . ' / [ &
configuration/ levels/ timing/ vectors/
+ # ? & A # ? & T 0 1 pin configuration& T
0 1 < + configuration/ power supply& voltage &
T 0 1 < +levels/ (
kdevice x n
pin configuration
8 Create Device
- 8-
2. Pin Configuration
- 9-
Config
11 Pin Configuration
12 Pin Configuration
- 10-
- 11-
15
16 x power
15 Drive Levels
Logic 1
voh
Intermediate
vol
Compare Levels
(Thresholds)
16 Compare Levels
- 12-
Logic 0
Internal
Setup
settling time Time
t_ms
Power Supply Voltage
vout
Connect Current Limit
ilimit
Disconnect Stage:
offcurr =min, act
SPECS
<spec1>
<spec2>
<speck>
SPECS
<spec1> = 4.5 V
<speck> = 0. 5V
SPECS
<spec1> = 4.8 V
<speck> = 0. 2V
EQUATIONS
DPSPINS
LEVELSET 1
...
LEVELSET k
- 13-
0
IOPW
0.2*IOPW
0.8*IOPW
DPSPINS
corevdd
vout = COREPW
ilimit = 1000
t_ms = 4
offcurr = act
DPSPINS
iovdd
vout = IOPW
ilimit = 1000
t_ms = 4
offcurr = act
LEVELSET 1 "no termination"
PINS all_ins clk
vil=VIL
vih=VIH
PINS io_pins
vil= VIL
vih= VIH
vol= VOL
voh= VOH
PINS all_outs
vol=VOL
voh=VOH
20 Level Equation Set Example
- 14-
" #level equation set + "create, - & ' (Create level spec set
) * 23 Create level spec set
" # Set number
Description. / 0 1 2 3 % + "create, - 4 & ' (Spec Tool
(* 24) Spec Tool
! 4 & ' (
SPECS
5 6
Actual . / 0 1
7 1 8 9 " # File Download
download data manager! Level Icon&
9 : ; < = > ? @ A B
C
D E F + " data managerG H Save, - I J 6
? L M N O P 5 6 Q ( R S T U V L SPECS
W X Y A core
- 15-
3
1
4
2
- 16-
* :;<=>7?@A ? B C D (k } 94~830)
CD
1. :; < = > 7 ? @ A ? B C D
(Q R http://www2.cic.org.tw/~kangchu/layout/note/0429-handout.ppt) S T 1
:;>7UV&WX>7YZ[\]^_`abcde
/fghi<jklmno"p@A?Bqrs>7tu>
7:; ) v 7 w x y z
2. S T | } F G 94~ 7 25 k G T1894E(F)N O(> 7 9/5) 7 W
3.:; < = > 7 ? @ A ? B C D n o k
(1) CICQ G (Q R http://www.cic.org.tw/cic_v13/main.jsp )
(2) CIC Enews
(3) email > 7 t (CICQ z e ( ) qemail address
7 q email address,
y7Z : ; < = > 7 ? @ A ? B C D
) Q R http://www.cic.org.tw/cic_v13/fab_services/index.jsp B ) v
- (4)
MP15-94BNO:;<=> 7 C D (k } 94~99)
CD
_P15-94B c d e ) v +(2005.10.28)} s N O
cd>7t,`hi}7>7t(&ac
- 17-
95~U18<j C D (k } 94~922)
CD
_ CIC D ~ (95~ ) < j UMC 0.18um Mixed Signal/RF CMOS
1.8V/3.3V Process(' U18)) v w , 95~5 , [
<jfg>7)vnow<jrno&
a 95~5 q N O ) v ) v } j 95~ : ; < =
}jK ( s94~10 k l)
s UMC Mixed Signal/RF CMOS 1.8V/3.3V process TSMC 0.18um CMOS
Mixed Signal/RF General Purpose MiM Al 1P6M 1.8V/3.3V process(' T18)
[
T18n o & Artisan Cell Library _
U18X t < j T18< = s & t
X TSMC 0.13um CMOS Mixed Signal General Purpose MiM Cu FSG 1P8M
1.2V/2.5V process
3q 7 )
U18 n o 7
ycchen@cic.org.tw 03-5773693ext.201
T18 n o 7 '
thchien@cic.org.tw 03-5773693ext.202
T18 Cell Library 7
saho@cic.org.tw 03-5773693ext.193
U18 Cell Librar y 7
cplin@cic.org.tw 03-5773693ext.163
Cause
OD.C.1
OD.C.2_OD.C.3
I/O PAD ERROR STC18io_18T
OD.C.5
RPO.S.1
- 18-
RPO.C.3
RPO.C.6
NW.S.1
NWR.E.1
NWR.C.3
OD.C.1
OD.C.2_OD.C.3
OD.C.5
I/O PAD ERROR STC18io_33T
RPO.S.1
RPO.C.3
RPO.C.6
ESD.GUIDE.4
ESD.5E
ESD.5F
ESD.5G
ESD.5E
- 19-
Hierarchical % d 9 AM.W.1.M5!
* J } Hierarchical 5 sCICK L \Flat
` } 7 Flat 5 / ! !
CD
1 9 19 ? CIC @ MEMS Interferometer Measurement SystemA B >
7MEMS Interferometer Measurement System0 1 DU V
:
1. White light Interferometer(Optical profiler)
2. MEMS Motion Analyzer
- 20-