ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

ONES COMPLEMENT VHDL CODE USING STRUCTURAL MODELING

Library declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

Std_logic_1164. package for std_logic (predefined data types).

-----------------------------------------------------------------entity ones_comp is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
e: in std_logic;
y : out STD_LOGIC_VECTOR (3 downto 0));
end ones_comp;
------------------------------------------------------------------

Entity declaration.
a: - input port bits.
e: - enable pin. If e=1 circuit will produce ones
complement otherwise it will act as a buffer.
y: - output port bits.(1s complement of input).

architecture Behavioral_1scomp of ones_comp is

---------------------------------------------component xor_1 is
Port ( o,p : in STD_LOGIC;
q : out STD_LOGIC);
end component;
----------------------------------------------begin
x1: xor_1 port map (a(0),e,y(0));
x2: xor_1 port map (a(1),e,y(1));
x3: xor_1 port map (a(2),e,y(2));
x4: xor_1 port map (a(3),e,y(3));
----------------------------------------------

end Behavioral_1scomp;

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Component (Ex-or) declaration

These components are describing the structural
view of half adder.

Architecture statements part (Architecture

body).
Components are port mapped to perform the
circuit (1s complement) operation.