ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

DEMUX VHDL CODE USING BEHAVIOURAL MODELING

Library declaration
library IEEE;
Std_logic_1164; package for std_logic (predefined data type).
use IEEE.STD_LOGIC_1164.ALL;
------------------------------------------------------------------------

entity dmux_1 is
Port ( i: in std_logic;
sel: in std_logic_vector (1 downto 0);
y: out std_logic_vector (3 downto 0);
end dmux_1;
----------------------------------------------------------------------architecture Behavioral_dmux of dmux_1 is
begin
-------------------------------------------------------process (sel, i)
begin
case sel is
when "00" =>
y(0)<=i;y(1)<='0';y(2)<='0';y(3)<='0';
when "01" =>
y(0)<='0';y(1)<=i;y(2)<='0';y(3)<='0';
when "10" =>
y(0)<='0';y(1)<='0';y(2)<=i;y(3)<='0';
when others =>
y(0)<='0';y(1)<='0';y(2)<='0';y(3)<=i;
end case;
end process;
------------------------------------------------------end Behavioral_dmux;

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Entity declaration.
i :- input port bit.
Sel: select lines for selecting a particular
input in mux.
y: - output port bits.

This is the process statement. In

process statement all the
statements are executed in
sequence.
Here we are using case
statements. where, we want to
assign same value to different
outputs, we have used case
statement
According to the select line
status, case statement assigns
the input value to desire out.