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A

Tang/TangBTO Schematics Document


uFCBGA/uFCPGA Coppermine-T or Tualatin

2001-11-16
3

REV: 2.0

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC.
D CONTAINS
AN
CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF MPETENT
THE CO DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE
RMATION
INFO CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OFALCOMP
ELECTRONICS,INC.
Date:
A

Cover Sheet
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

of

41

Block Diagram

Compal confidential
Model Name :ADY11(Tang)
File Name : LA-1181
Coppermine-T or
Tualatin
uFCBGA/uFCPGA CPU

CPU Bypass
& CPUVID
1

page 6

Thermal Sensor

page 4,5

ITP Connector

Fan Control

HA#(3..31)

page 7

page 7

W320-04

page 5

page 14

HD#(0..63)

PSB

133MHz

CRT Connector

Almador-M
GMCH-M

page 15

DVO Link

Memory BUS
3.3V 133MHz

SO-DIMM X2

BANK 0, 1, 2, 3 page 12,13

625 BGA

VCH Conn

VCH
Board

Clock Generator

MAX6654

page 8,9,10

page 15

HUB Link

1.8V 66MHz

PCI debug
port
page 27

PCI BUS
IDSEL:AD20
(PIRQA/B#,GN T#2,REQ#2)

IDSEL:AD17
(PIRQA#,GNT# 3,REQ#3)

3.3V 48MHz

421 BGA

3.3V 24.576MHz

USB conn
page 30

CardBus Controller

LAN
3COM -3C920

AC-LINK

MDC

3.3V ATA100

page 25

page 16,17

OZ 6912

page 20

page 21

RJ45

ICH3-M

3.3V 33MHz

LPC BUS

Slot 0

page 20

IDE Connector
(HDD/CR-ROM)

3.3V 33MHz

page 22

page 19

Power On/Off
Reset & RTC
page 30

LPC to X-BUS
& Super I/O

page 31

page 24

SIO

page 27

page 27

Touch Pad

page 27

BIOS

FDD

Int.KBD

page 29

page 29

Power Circuit
DC/DC
page
32,33,34,35,36,37

PIO

page 28

EC I/O Buffer
4

page 23

AMP& Phone
Jack

page 26

EC 87570

DC/DC Interface
Suspend

page 19

PS/2 conn

page 29

page 27

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:

NS PC87393

X BUS
14M_5V

AC97
Codec
STAC9700

Block Diagram
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

of

41

Note:"@" means all model depop


"#" means Tang depop

CHIPS Rev

CHIPS Rev

3C920-ST06

FW82830MG

FW82801CAM

SST-Build

QB88

QB63

Lot:M28010
DC:C0117

SST2-Build

QC34

QB62

QC34

QB62

QC34

QC42

Model
Function

M2P3

YES

FDD

Tang

NO

PS/2

YES

YES

Series port

NO

NO

Parallel port

YES

YES

RJ45

YES

NO

3Com Lan
chipset(3C920)

YES

NO

PT-Build
ST-Build

Lot:M28010
DC:C0117

Lot:M28010
DC:C0117
Lot:M28010
DC:C0117

Note:"@" means all model depop


"&" means M2P3 depop
"#" means Tang depop

Compal Electronics, Inc.


Title

Note & Revision


Size

Document Number

Rev
2

ADY11 LA-1181
Date:
5

Friday, November 16, 2001

Sheet
1

of

41

<8> HREQ#[0..4]

HREQ#[0..4]
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

<8> HADS#

+1.5VS
3

R108
1

1.5K
2

R121
1

10_0402
2

R1
L3
T1
U1
L1
T4
AA3
W2
AB3
P3
C14
AF23
AF4

<8> HBPRI#
<8> HBNR#
<8> HLOCK#

A7
C4
C22
AD23
R2
L2
V3

<8> HIT#
<8> HITM#
<8> HDEFER#

AA2
U2
T3

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

VCC

Address
Lines

Mobile
Tualatin

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
RP#
ADS#
AERR#
AP#0
AP#1
BERR#
BINIT#
IERR#
BREQ0#
NC
NC
NC
BPRI#
BNR#
LOCK#
HIT#
HITM#
DEFER#

TUALATIN

Data
Signals

Request
Signals

Error
Interface

Arbitration
Signals
Snoop
Signals

VSS

VCC

VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VCC_73

K1
J1
G2
K3
J2
H3
G1
A3
J3
H1
D3
F3
G3
C2
B5
B11
C6
B9
B7
C8
A8
A10
B3
A13
A9
C3
C12
C10
A6
A15
A14
B13
A12

HD#[0..63]

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

A16
B17
A17
D23
B19
C20
C16
A20
A22
A19
A23
A24
C18
D24
B24
A18
E23
B21
B23
E26
C24
F24
D25
E24
B25
G24
H24
F26
L24
H25
C26
K24
G26
K25
J24
K26
F25
N26
J26
M24
U26
P25
L26
R24
R26
M25
V25
T24
M26
P24
AA26
T26
U24
Y25
W26
V26
AB25
T25
Y24
W24
Y26
AB24
AA24
V24

HD#[0..63] <8>

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

P6
M6
AC5
AA5
AB6
W5
Y6
U5

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72

U5A

HA#[3..31]

E16 VSS_0
R4 VSS_1
E25 VSS_2
G25 VSS_3
J25 VSS_4
L25 VSS_5
N25 VSS_6
R25 VSS_7
U25 VSS_8
W25 VSS_9
AA25VSS_10
AC25VSS_11
AF25VSS_12
AE26VSS_13
C23 VSS_14
F23 VSS_15
H23 VSS_16
K23 VSS_17
M23 VSS_18
P23 VSS_19
T23 VSS_20
V23 VSS_21
Y23 VSS_22
AB23VSS_23
AE23VSS_24
B22 VSS_25
D21 VSS_26
F21 VSS_27
E22 VSS_28
H21 VSS_29
G22 VSS_30
K21 VSS_31
J22 VSS_32
M21 VSS_33
L22 VSS_34
P21 VSS_35
N22 VSS_36
T21 VSS_37
R22 VSS_38
V21 VSS_39
U22 VSS_40
Y21 VSS_41
W22 VSS_42
AB21VSS_43
AA22VSS_44
AC22VSS_45
AE21VSS_46
B20 VSS_47
D19 VSS_48
AB19VSS_49
AA20VSS_50
AC20VSS_51
AE19VSS_52
B18 VSS_53
D17 VSS_54
F17 VSS_55
E18 VSS_56
AB17VSS_57

<8> HA#[3..31]

D22
F22
E21
H22
G21
K22
J21
M22
L21
P22
N21
T22
R21
V22
U21
Y22
W21
AB22
AA21
AC21
D20
F20
E19
AB20
AA19
AC19
D18
F18
E17
AB18
AA17
AC17
D16
F16
E15
AB16
AA15
AC15
D14
F14
E13
AB14
AA13
AC13
D12
F12
E11
AB12
AA11
AC11
D10
F10
E9
AB10
AA9
AC9
D8
F8
E7
AB8
AA7
AC7
D6
F6
E5
H6
G5
K6
J5
N5
T6
V6

+CPU_CORE

+CPU_CORE

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

Mobile Tualatin uFCPGA


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

of

41

VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129

<8> H_RESET#

W3
Y1

<8> H_DBSY#
<8> H_DRDY#

+1.5VS

H_THERMDA
H_THERMDC

<14> H_BSEL0
<14> H_BSEL1

AE12
AF10
2 AF16
110_1%
AD19
AD17
AF20

<14> CLK_CPU_APIC

8
7
6
5

8P4R_1.5K
ITP_TDI
ITP_TMS
ITP_TRST#
ITP_TCK

+VTT
1.5K
1
1

R38

56.2_1%

C38
R35 2
1
@33_0402
@10PF_0402

ITP_PREQ#
ITP_PRDY#

AF22
AE20
AD22
AD21

ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_PREQ#
ITP_PRDY#

<7> ITP_TCK
<7> ITP_TDI
<7> ITP_TDO
<7> ITP_TMS
<7> ITP_TRST#
<7> ITP_PREQ#
<7> ITP_PRDY#

+VS_CMOSREF
R136
2
2

Mobile
Tualatin

SELFSB0
SELFSB1
EDGECTRLP

1
R34

<16> PICD0
<16> PICD1

1
2
3
4

THERMDA
THERMDC

1
R30

AD10
AD7
AD11
AF7
AF15
AF19
AE22
AF12
AD5
AE16

2
56.2_1%

L5

<16> PM_CPUPERF#

APIC

RP2#
RP3#
BPM0#
BPM1#

Debug
Break
Point

TCK
TDI
TDO
TMS
TRST#
PREQ#
PRDY#

R9
2

1K_0402
1

+CPU_CORE

R15

0_0402

TESTLO1
+VTT_PLL

1
L22

2
FLM-201209-4R7K

C22
33UF_D2_16V

CLK_HCLK
CLK_HCLK#
TESTLO2

CLK_HCLK <14>
CLK_HCLK# <14>

Test
Access
PORT

VCCT

VID

TESTHI1

TESTHI2

AD4
A5
D1
AD13
B1
P26
A11
VTT_PWRGD

E3

VTTPWRGOOD

D26

NC

GHI#

14_1%
2

P4

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7

( ITP )

R134
1

AF18
AD16
AF11
AE8
N24
AE10
E2

NC
NCHCTRLP
TESTHI
NC
NC
NC
TESTHI

CMOSREF_1
CMOSREF_0
RTTIMPDEP

+VTT

TESTLO2

+VTT

AC1
AD1
M1

CLK0
CLK0#
TESTLO

NC

1K_0402
1

+VTT

PICD0
PICD1
PICCLK

Note :
GHI# Pull-Up internally

If used ITP port mu st depop

TESTLO1

+V_AGTLREF

Y4
R5
N3
N2
P1
P5
E1
F1

TESTLO
VCC
PLL1
PLL2
NC
NC
NC
NC

Analog

1
R37
150

R36
150

RP6

AF13
AF14

DBSY#
DRDY#

1K_0402
1

R7
2

+1.5VS

VTT Ref

R10
2

VSS_142
VSS_141
VSS_140
VSS_139
VSS_138
VSS_137
VSS_136
VSS_135
VSS_134
VSS_133
VSS_132
VSS_131
VSS_130

H_INTR
H_NMI

TESTHI2

AF21
AB26
H26
A21
AF9
A4
N1
AA1

VREF_1
VREF_2
VREF_3
VREF_4
VREF_5
VREF_6
VREF_7
VREF_8

F19
E20
C25
A25
AE1
AD2
AB2
Y2
V2
T2
P2
M2
K2

<16> H_STPCLK#
<16,32> H_DPSLP#
<16> H_INTR
<16> H_NMI
<16> H_INIT#

C1 NC
AF17NC
N4 NC

<16> H_PWRGD

Data
Signals

A20M#
FERR#
FLUSH#
IGNNE#
SMI#
PWRGOOD
STPCLK#
DPSLP# Compatibility
INTR/LINT0
NMI/LINT1
INIT#
RESET#

B26 VSS
M4 VSS
AF26VSS

H_IGNNE#

<16> H_IGNNE#
<16> H_SMI#

AC3
AF6
AF5
AD9
AD3
AB4
AE4
AF8
AD15
AE14
AE6
B15

AE24
AD25
AE25
AC24
AF24
AD26
AC26
AD24

DEP#0
DEP#1
DEP#2
DEP#3
DEP#4
DEP#5
DEP#6
DEP#7

GND

VID0
VID1
VID2
VID3
VID4

H_A20M#

<16> H_A20M#
<16> H_FERR#

Request
Signals

<8> H_TRDY#

RS#0
RS#1
RS#2
RSP#
TRDY#

1K_0402
1

+VTT_C

Y3
V1
U3
M5
W1

<8> H_RS#0
<8> H_RS#1
<8> H_RS#2

R24
1.5K

AB1
AC2
AE2
AF3
R3

R19
3K

R18
1.5K

A26 VCCT_1
G23 VCCT_2
J23 VCCT_3
L23 VCCT_4
N23 VCCT_5
R23 VCCT_6
U23 VCCT_7
W23 VCCT_8
AA23VCCT_9
C21 VCCT_10
C19 VCCT_11
AD20VCCT_12
C17 VCCT_13
AD18VCCT_14
C15 VCCT_15
C13 VCCT_16
AD14VCCT_17
C11 VCCT_18
AD12VCCT_19
C9 VCCT_20
C7 VCCT_21
AD8 VCCT_22
C5 VCCT_23
AD6 VCCT_24
AC23VCCT_25
AA4 VCCT_26
E4 VCCT_27
G4 VCCT_28
J4 VCCT_29
L4 VCCT_30
AC4 VCCT_31
V4 VCCT_32
AE3 VCCT_33
AF2 VCCT_34
AF1 VCCT_35
AE18VCCT_36
D5 VCCT_37
E6 VCCT_38

R28
56.2_1%

Place
R_K<0.1"
from CPU

R_K
1

+1.5VS

R25
2

U5B
+1.5VS

TESTHI1

+VTT_PLLIN

+1.8VS

AA18
AC18
AE17
B16
D15
F15
AB15
AA16
AC16
AE15
B14
D13
F13
E14
AB13
AA14
AC14
AE13
B12
D11
F11
E12
AB11
AA12
AC12
AE11
B10
D9
F9
E10
AB9
AA10
AC10
AE9
B8
D7
F7
E8
AB7
AA8
AC8
AE7
B6
F5
H5
G6
K5
J6
N6
L6
T5
R6
V5
U6
Y5
W6
AB5
AA6
AC6
AE5
B4
D4
F4
H4
K4
M3
U4
W4
B2
D2
F2
H2

+VTT
+VTT

TUALATIN

+3VS
1

+VTT

R6
10K_0402
2

R11
1K_0402

VTT_PWRGD# <14,28>
2

W=15mil

<6>
<6>
<6>
<6>
<6>

CPU_VR_VID4
CPU_VR_VID3
CPU_VR_VID2
CPU_VR_VID1
CPU_VR_VID0

+5VALW

2
C35

10K_0402

Q2
3 3904

C25
.1UF_0402

1. Place R_A and R_B between and GMCH and CPU.


2. Place decoupling caps near CPU.(Within 500mils)
+V_AGTLREF

C30
.1UF_0402

C41
.1UF_0402

C36
.1UF_0402

C26
.1UF_0402

R_B

R21
2K_1%

C31
.1UF_0402

C33
.1UF_0402

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.

+5VALW

Date:
A

Layout note :

10K_0402

1K_0402

Address :1001_110X

R22
1K_1%

1
R27

GTL Reference Voltage

+VS_CMOSREF

R_F
R23

R_A

R31
1K_1%

1
2
SMB_EC_DA1 <15,28,29,33>
THRM# <29>

1K_0402
1

Layout note :
1. Place R_E1 and R_F near CPU.
2. Place decoupling caps near CPU.

SMB_EC_CK1 <15,28,29,33>

+5VALW

R29
2

R_E

R20
499_1%

2
4

NC
NC
VCC
STBY
DXP
SMBCLK
DXN
NC
NC
SMBDATA
ADD1
ALERT
GND
ADD0
GND
NC
MAX6654MEE

16
15
14
13
12
11
10
9

H_THERMDA
H_THERMDC

C34
2200PF

1
2
3
4
5
6
7
8

+VTT

1
2

CMOS Reference Voltage

+1.5VS

U6

R14
1
19.6K

R26

.1UF_0402

Thermal Sensor
MAX6654MEE

VTT_PWRGD

<32> VTT_PWRGD

Mobile Tualatin uFCPGA & Thermal sensor


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

of

41

Layout note :

Layout note :

Place close to CPU, Use 2~3 vias per PAD.


Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

Place close to CPU,


Use 2 vias per PAD.

+VTT
+CPU_CORE

C129
1UF
2

C227
1UF
2

C248
1UF

1
C199
1UF
2

C249
1UF
2

C135
1UF
2

C130
1UF

C182
10UF_10V_1206
2

C201
10UF_10V_1206
2

Pls used X7R(uFCPGA EMTS Rev0.7)

+3VS

C260
220UF_D2_4V

3
7
11
17
21

<17>
<17>
<17>
<17>
<17>

4
8
14
18
22

AC_VID0
AC_VID1
AC_VID2
AC_VID3
AC_VID4

PM_GMUXSEL = 0 : for low Voltage A-C


1 : for high Voltage B-C

+CPU_CORE

U24

CPU_VR_VID0
CPU_VR_VID1
CPU_VR_VID2
CPU_VR_VID3
CPU_VR_VID4

1
13

<16,32> PM_GMUXSEL

A0
A1
A2
A3
A4

C0
C1
C2
C3
C4

B0
B1
B2
B3
B4

D0
D1
D2
D3
D4

BE#

VCC

BX

GND

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4

<32>
<32>
<32>
<32>
<32>

+5VS

24
12

C455
.01UF_0402

1
C210
+
@220UF_D2_4V

5
9
15
19
23

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4

C153
220UF_D2_4V

C119
220UF_D2_4V

C293
+
@220UF_D2_4V

SN74CBT3383

2
6
10
16
20

2
1
C292
220UF_D2_4V

C126
@220UF_D2_4V

1
2

C29
220UF_D2_4V

RP7
8P4R_1K

R257
1K_0402

<5>
<5>
<5>
<5>
<5>

+CPU_CORE

1
2
3
4

C184
10UF_10V_1206
2

C24
10UF_10V_1206
2

C191
10UF_10V_1206
2

C151
10UF_10V_1206

1
2

C183
10UF_10V_1206

8
7
6
5

C28
10UF_10V_1206

CPU Voltage ID

C152
1UF

1
2

C202
10UF_10V_1206

+CPU_CORE

C123
1UF
2

C222
1UF

C165
.22UF_X7R

C188
.22UF_X7R

Pls used X7R(uFCPGA EMTS Rev0.7)

C200
10UF_10V_1206

C118
@220UF_D2_4V

C228
.22UF_X7R

1
C231
.22UF_X7R

C235
.22UF_X7R

C212
.22UF_X7R

C192
.22UF_X7R

C174
.22UF_X7R

C141
.22UF_X7R

1
+CPU_CORE

C143
.22UF_X7R

C145
.22UF_X7R

1
2

C194
.22UF_X7R

+VTT

Pls used X7R(uFCPGA EMTS Rev0.7)

+CPU_CORE

C37
220UF_D2_4V

C146
.22UF_X7R

1
C173
.22UF_X7R
2

1
C229
.22UF_X7R
2

C216
.22UF_X7R
2

C230
.22UF_X7R

C234
.22UF_X7R

C196
.22UF_X7R

C233
.22UF_X7R

C164
.22UF_X7R

C142
.22UF_X7R

C144
.22UF_X7R

C205
.22UF_X7R

Pls used X7R(uFCPGA EMTS Rev0.7)

Tualatin

Coppermine-T

+CPU_CORE

C32
220UF_D2_4V

D4 D3 D2 D1 D0
CPU_Core(V) ES(before
MP)
------------------------------------------------------C289
220UF_D2_4V

C283
220UF_D2_4V

1.50V

0 0 0 0 1

1.70V

0 1 1 0 0

1.15V

0 1 0 0 0

1.35V

------------------------------------------------------

------------------------------------------------------2

D4 D3 D2 D1 D0
CPU_Core(V) ES(before
MP)
------------------------------------------------------

0 0 1 0 1

D4 D3 D2 D1 D0

CPU_Core(V)

QS

( MP)

-------------------------------------------------------

0 0 1 1 1

1.40V

0 1 1 0 0

1.15V

-------------------------------------------------------

D4 D3 D2 D1 D0

CPU_Core(V)

QS

( MP)

------------------------------------------------------

0 0 0 0 1

1.70V

0 1 0 0 0

1.35V

------------------------------------------------------

EMI Clip PAD for CPU


PAD2

PAD6
1

PAD7
1

PAD8
1

Compal Electronics, Inc.


PAD-2.5X3

PAD-2.5X3

PAD-2.5X3

PAD-2.5X3

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:

CPU Bypass & CPU VID


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

of

41

ITP PORT
+1.5VS
+VTT

+VTT

+1.5VS

+VTT

+3VS

R94

R96
@56_1%
R95

<8> H_RESETX#

R91
@39

240

R87
@10K_0402

R89
@1.5K

R86
@200

R92
@200

R85
@56.2_1%

JP18

@240

<5> ITP_TCK
<5> ITP_TMS

R90
@150

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

ITP_TCK
ITP_TMS

R93
@39

<14> CLK_ITPP

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

ITP_TDI
ITP_TDO
ITP_TRST#
ITP_PREQ#
ITP_PRDY#
R84

@240

ITP_TDI <5>
ITP_TDO <5>
ITP_TRST# <5>
ITP_PREQ#
ITP_PRDY#

<5>
<5>

CLK_ITPP#

<14>

R88
@510

@AMP104078-4
U26C
9
8

1
R415

<16,30> ITP_PWROK

2
5.6K_0402

PM_PWROK

<16>

10
74HCT08

R245
10K_0402

+5VS POWER

R249

@0_0402
1
R416

2
100_0402

EC_HPOWON

Fan Control circuit

+12VALW

<28>

R235
3.48K_1%

+5VALW

Q4
FMMT619
2

+5VFAN

C420
2.2UF_16V_0805

<28> EN_DFAN

D2
1SS355

3
D8
1N4148

JP17

D1

C99

Q10
1 2SA1036K

1N4148

@1000PF_0402

1
2
3

53398-0310

+3V

R375
10K_0402

FAN1_TACH

<28>

COMPAL Electronics,Inc
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL
ECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THECUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SH
EET NOR THE INFORMATION CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN ONSENT
C
OF COMPAL ELECTRONICS,INC.
Date:
5

ITP PORT & Fan control


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
1

of

41

2 470PF

VSS_H0
VSS_H1
VSS_H2
VSS_H3
VSS_H4
VSS_H5
VSS_H6
VSS_H7
VSS_H8
VSS_H9
VSS_H10
VSS_H11
VSS_H12
VSS_H13
VSS_H14
VSS_H15
VSS_H16

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36

CLK_HT
CLK_HT#
CLK_DREF
CLK_GBIN
CLK_GBOUT

2
@0_0402

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

1
R116

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

H6
H4
G6

H_RS#0
H_RS#1
H_RS#2

H_RS#[0..2]

H_RS#[0..2] <5>

AJ4
AH5
AC19
AG26
AD24

CLKGBOUT

CLK_DREF <14>
CLK_GBIN <14>
1
2 1
2
CLK_GBOUT <14>
R156 47_0402
C277
.01UF_0402
R151
@33_0402

R168
33_0402
C259
@10PF_0402

C297
5PF_0402

2
80.6_1%

CLK_GBIN

C185
.1UF_0402

R167
@240K
2

C263
.1UF_0402

<16> HUB_PD[0..10]
<16> HUB_PSTRB
<16> HUB_PSTRB#

CLK_GHT <14>
CLK_GHT# <14>

+V_AGTLREF
1

+VS_HUBREF

H_RESETX# <7>
H_RESET# <5>
HADS# <4>
HBNR# <4>
HBPRI# <4>
H_DBSY# <5>
HDEFER# <4>
H_DRDY# <5>
HIT# <4>
HITM# <4>
HLOCK# <4>
H_TRDY# <5>
HREQ#[0..4] <4>

HREQ#[0..4]
K6
M4
K5
K4
L6

ALMADOR-M

H_RS#0
H_RS#1
H_RS#2

Close to Ball R6.

C270 1

1
R133

R6
C1
E1
L4
G5
J4
F4
D3
D1
J6
G4

HA#[3..31] <4>

R147
82.5_1%
2

R141
1K_1%

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

H2
E3
G3
N4
M6
F1
F2
J3
F3
P6
G1
N5
H1
P4
T4
M2
J2
L2
R4
K1
L3
L1
J1
N1
T5
H3
M3
M1
K3

VGAREF

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

G8 VSSA_CPLL
AD7 VSSA_HPLL

R143
82.5_1%

AH26VSSA_DAC

2 470PF

C261 1
R142
1K_1%

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_CPURST#
H_ADS#
H_BNR#
H_BPRI#
H_DBSY#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

AH24VSSP_DVO0
AF25VSSP_DVO1
AF27VSSP_DVO2

+1.5VS

Almador-M
GMCH

AC26VSSP_IO0
AD22VSSP_IO1
AE28VSSP_IO2

Place Reference Circuit near GMCH

Host
Interface
Host
Interface

G28 VSSP_HUB0
H25 VSSP_HUB1

C176
.1UF_0402

AH19VSSPCMOS_LM0
AH20VSSPCMOS_LM1
AF5 VSSPCMOS_LM2

R_D
2

+VS_HUBREF
R124
301_1%

H_GTLRCOMP

1. Place R_C and R_D in middle of Bus.


2. Place capacitors near GMCH.

AB23VSS
AC23VSS

Layout note :

HA#[3..31]

VSS

C2

R_C

R125
301_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

AC22DVO_RCOMP
F6 SM_RCOMP
J23 HUB_RCOMP
J25 AGP_REF
K24 AGP_RCOMP/DVOBC_RCOMP
AB24RESET#
AA7 H_GTLREF1
J7 H_GTLREF0

HUB Interface Reference

U4
P1
W6
U2
U6
R1
N3
W5
V4
P3
R3
U1
V6
W4
T3
P2
V3
R2
T1
W3
U3
Y4
AA3
W1
V1
Y1
Y6
AD3
AB4
AB5
V2
Y3
Y2
AA4
AA1
AA6
AB1
AC4
AA2
AB3
AD2
AD1
AC2
AB6
AC6
AC1
AF3
AD4
AD6
AC3
AH3
AE5
AE3
AG2
AF4
AF2
AJ3
AE4
AG1
AE1
AG4
AH4
AG3
AF1

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10
HUB_PSTRB
HUB_PSTRB#
HUB_REF

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

+1.8VS

U7A

HD#[0..63]

G26
H28
H29
H27
F29
F27
E29
E28
G25
G27
H26
G29
F28
H24

<4> HD#[0..63]

AJ5
D2
AC5
Y5
U5
P5
L5
H5
AH2
AE2
AB2
W2
T2
N2
K2
G2
AC7

M12
M13
M17
M18
N12
N13
N14
N15
N16
N17
N18
P13
P14
P15
P16
P17
R13
R14
R15
R16
R17
T13
T14
T15
T16
T17
U12
U13
U14
U15
U16
U17
U18
V12
V13
V17
V18

R138 1
R126 1
R127 1

2
R128

2 54.9_1%
2 27.4_1%
2 54.9_1%

C178
.01UF_0402

1
54.9_1%

PCIRST# <15,16,20,21,26,27,28>

C190
.1UF_0402

10 mils wide,length <=500 mils.

VGAREF

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

Almador-M GMCH(1/3)
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

of

41

SM_MA[0..12] <12,13>
VSSA_DPLL0 <10>

RP5

AE20
G24

K28
N28
T28
W28
AB28
L25
P25
U25
Y25

VSSA_DPLL0
VSSA_DPLL1

Almador-M
GMCH

SDRAM
System
Memory

SDRAM
System
Memory

SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7
SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3
VCCQ_SM
VSS
SM_CLK0
SM_CLK1
SM_CLK2
SM_CLK3
VSS
VSS

8
7
6
5

SM_MA0
SM_MA1
SM_MA2
SM_MA3

MMA4
MMA5
MMA6
MMA7

1
2
3
4

8P4R_10
RP4
8
7
6
5

SM_MA4
SM_MA5
SM_MA6
SM_MA7

1
2
3
4

8P4R_10
RP3
8
7
6
5

SM_MA8
SM_MA9
SM_MA10
SM_MA11

MMA8
MMA9
MMA10
MMA11

F20
E20
F12
E11
C21
F19
E12
A12

MMA12

+3V

C132 1
B16 SM_D_BA0 R114 1
C16 SM_D_BA1 R115 1
F18
D18
D13
D12
E18
F17
F14
F13

SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7

E17
F16
D16
D15
E15
E14

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

A15
B2
B14
A3
A14
C3

SM_D_CLK0
SM_D_CLK1
SM_D_CLK2
SM_D_CLK3

A13
C9
C13
A9
B13
A8

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

1
R112

SM_MA12
2
10_0402

2
2

10_0402
10_0402

near pin A12

SM_BA0 <12,13>
SM_BA1 <12,13>
SM_DQM[0..7] <12,13>

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

<12>
<12>
<13>
<13>

Layout note :
Place resistors near GMCH

R110
R113
R119
R109

1
1
1
1

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

2
2
2
2

10_0402
10_0402
10_0402
10_0402

SMD_CLK0
SMD_CLK1
SMD_CLK2
SMD_CLK3

+3V
C131

Layout note
Cap near pin A8

2
1

SM_OCLK_RCLK
C134

R118 1
R120 1
R111 1

2
2
2

10_0402
10_0402
10_0402

SM_RAS# <12,13>
SM_CAS# <12,13>
SM_WE# <12,13>

System Memory Reference

Layout note
SM_OCLK_RCLK trace length 150
mil +-50mil

R122
249_1%
2

+V_SMREF
C157

@22PF_0402

+V_SMREF

.1UF_0402

.1UF_0402

<12>
<12>
<13>
<13>

<12>
<12>
<13>
<13>

+3V

Place resistors near GMCH

Cap

2 .1UF_0402

+3V

.1UF_0402

SM_D_RAS#
SM_D_CAS#
SM_D_WE#

C160

Layout note :

8P4R_10

SM_DQ[0..63] <12,13>

+VTT

Layout Note:
F20,E 20,F12,E11
ADD Testpoint
for Factory

Power

MMA0
MMA1
MMA2
MMA3
MMA4
MMA5
MMA6
MMA7
MMA8
MMA9
MMA10
MMA11
MMA12

1
2
3
4

XOR

A21 SM_WE#
D19 SM_CAS#
C20 SM_RAS#

VSS

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
VSS
VCC_SM

A20
B20
B19
C19
A18
A19
C17
C18
B17
A17
A16
C15
C14

MMA0
MMA1
MMA2
MMA3

SM_DQ[0..63]

SM_BA0
SM_BA1

C24 SM_RCLK
A24 SM_OCLK

ALMADOR-M

NC
NC
NC
NC
VSS
VSS
VCC_SM
VCC_SM

F24 SM_VREF1
E5 SM_VREF0

SM_MA0
SM_MA1
SM_MA2
SM_MA3
SM_MA4
SM_MA5
SM_MA6
SM_MA7
SM_MA8
SM_MA9
SM_MA10
SM_MA11
SM_MA12

VSS

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

SM_DQ0
SM_DQ1
SM_DQ2
SM_DQ3
SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7
SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11
SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15
SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19
SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27
SM_DQ28
SM_DQ29
SM_DQ30
SM_DQ31
SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35
SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39
SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47
SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51
SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55
SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59
SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

H7
H23
K7
K23
L7
N6
T6
W7
Y7
AB7
M24
P24
T24
V24
Y23
M14
M15
M16
P12
R12
T12
P18
R18
T18

D29
C29
D27
C27
A27
B26
E24
C25
E23
B25
C23
F22
B23
C22
E21
B22
C12
D10
C11
A10
C10
C8
A7
E9
C7
E8
A5
F8
C5
D6
B4
C4
E27
C28
B28
E26
C26
D25
A26
D24
F23
A25
G22
D22
A23
F21
D21
A22
F11
A11
B11
F10
B10
B8
D9
B7
F9
A6
C6
D7
B5
E6
A4
D4

VSSP_SM0
VSSP_SM1
VSSP_SM2
VSSP_SM3
VSSP_SM4
VSSP_SM5
VSSP_SM6
VSSP_SM7
VSSP_SM8
VSSP_SM9
VSSP_SM10
VSSP_SM11
VSSP_SM12
VSSP_SM13
VSSP_SM14
VSSP_SM15
VSSP_SM16
VSSP_SM17
VSSP_SM18
VSSP_SM19

SM_DQ0
SM_DQ1
SM_DQ2
SM_DQ3
SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7
SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11
SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15
SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19
SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27
SM_DQ28
SM_DQ29
SM_DQ30
SM_DQ31
SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35
SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39
SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47
SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51
SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55
SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59
SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

B3
B6
B9
B12
B15
B18
B21
B24
B27
E7
E10
E13
E16
E19
E22
E25
G9
G21
E4
D28

VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM

U7B

VSSP_AGP0
VSSP_AGP1
VSSP_AGP2
VSSP_AGP3
VSSP_AGP4
VSSP_AGP5
VSSP_AGP6
VSSP_AGP7
VSSP_AGP8

AD8
AD9
AD10
AJ21
AE8
AE9
AE10
AE11
AE12
AE13
AE17
AE19
AH21
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AG7
AG15
AG16
AG21
AH6
AH8
AH9
AH11
AH12
AH14
AH17
AH18

VSSA_DPLL1 <10>

R123
49.9_1%

Close to Ball E5 and F24

Layout note :
near pin A24

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

Almador-M GMCH(2/3)
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

of

41

+1.5VS
+1.5VS
+1.5VS

R432
1

@8.2K_0402
AGP_STOP#
2

2 AGP_IRDY#
8.2K_0402

1
R417

@8.2K_0402
AGP_ST0
2

R163
1

@8.2K_0402
AGP_ST1
2

R149
1

@8.2K_0402
AGP_ST2
2

L49
FBM-11-201209-601T
R176 0_0402
1
2 VCCA_DPLL0 1
2
1

8.2K_0402
AGP_TRDY#
2

R155
1

+1.8VS

C294

Low

DVOA_D1

IOQD=1

IOQD=8

DVOA_D5

Desktop

Mobile

High

DVOA_D6

Dual Ended Term

Single Ended Term

C302
100UF_D2_6.3V

.1UF_0402
2

R431
1

2 AGP_DEVSEL#
8.2K_0402

1
R137

Strap Name

+1.5VS

8.2K_0402
AGP_FRAME#
2

R430
1

+VTT

+VTT

AGP_PIPE#
AGP_WBF#
AGP_RBF#

ALMADOR-M

AGP_BUSY#

1
AE29
AD28
AF28
AG28
AH27
AF29
AG29
AH28
AE27
AD27
AJ27

R172 1

CRT_R <15>
CRT_G <15>
CRT_B <15>
3VDDCCL <15>
3VDDCDA <15>

2 255_1%

DVOA_CLKIN

AD20
AD21
AF23
AF22
AD25
AC25
AG24
AJ24

2 10K_0402

R162 1

+3VS
GMBSCL <15>
GMBSDA <15>

2 10K_0402

R153 1

+3VS

+1.5VS

AJ22
AH22
AG22
AJ23
AH23
AG23
AE23
AE24
AJ25
AH25
AG25
AJ26

DVOA_D1
DVOA_CLKIN
DVOA_INTR#
DVOA_D5
DVOA_D6
1
T52
1
T53

2
10K_0402

R160 1

1
R132

2
330

R170 1
R169 1

10K_0402
2
2

LTVDA <15>
LTVCK <15>
+3VS

+1.8VS

R_I

1. Place R_I and R_J near GMCH.


+VS_RIMMREF

AJ11
AH10
AJ10
AG10
AJ9
AG9
AJ8
AG8

R154
2K_1%

R_J

AC24

AGP_BUSY# <16>
2 10K_0402

+3VS

37.4_1% resistors and cap


must be placed after RGB
pi filter near CRT
connector.

+1.8VS

C627
CRT_R#

+VS_RIMMREF

CRT_B#

@.1UF_0402

2
37.4_1%
2

1
R419
C629

10K_0402

1
R418
C628

@.1UF_0402

2
37.4_1%
4

2 @.1UF_0402

1
R420

2
37.4_1%

Compal Electronics, Inc.

AGP_PAR
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:

100K_0402

+3VS

2 10K_0402

C266
68PF

AGP_PAR : Strapping option for SW detection of


AGP or DVO device.
0 -> DVO B/C device
1 -> AGP device

100K_0402

R159
576_1%

R152 1

+3V

R164

AG17
AJ17
AG18
AJ18
AG19
AJ19
AG20
AJ20

R157

Layout Note:
AE24,AJ25
ADD Testpoint
for Factory
1
R161

DVOA_INTR#
1
2
R166
10K_0402

XOR

AD26
AE26
AE21
AE22

CRT_VSYNC <15>
CRT_HSYNC <15>

CRT_R#
CRT_G#
CRT_B#

CRT_G#
4

C180
100UF_D2_6.3V

10K_0402

R422
604_1%

AC10VCC_LM
AC11VCC_LM
AD11VCC_LM
AD12VCC_LM
AD13VCC_LM
AE18VCC_LM
AD17VCC_LM
AD18VCC_LM
AD19VCC_LM

DPMS_CLK
2

VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM

1
R145

Local Memory
Interface

D5
D8
D11
D14
D17
D20
D23
D26
F7
F15
G11
G19
G23

1
732_1%

LM_DQB0
LM_DQB1
LM_DQB2
LM_DQB3
LM_DQB4
LM_DQB5
LM_DQB6
LM_DQB7
AJ16 LM_CFM
AH16LM_CFM#

4
2
R421

TC7SH14

LM_DQA0
LM_DQA1
LM_DQA2
LM_DQA3
LM_DQA4
Local Memory LM_DQA5
Interface
LM_DQA6
LM_DQA7

AH15LM_CTM
AJ15 LM_CTM#

Y
GND

DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8
DVO_D9
DVO_D10
DVO_D11

IO_DDC2DATA
IO_DDC2CLK
DVO_INTR#
DVO_FIELD

AD14LM_RAMREF0
AE14LM_RAMREF1

Almador-M
GMCH

(DVOB/DVOC & ZV port)


AGP_AD0/DVOB_HSYNC
AGP_AD1/DVOB_VSYNC
AGP_AD2/DVOB_D1
AGP_AD3/DVOB_D0
AGP_AD4/DVOB_D3
AGP_AD5/DVOB_D2
AGP_AD6/DVOB_D5
AGP_AD7/DVOB_D4
AGP_AD8/DVOB_D6
AGP_AD9/DVOB_D9
AGP_AD10/DVOB_D8
AGP_AD11/DVOB_D11
AGP_AD12/DVOB_D10
AGP_AD13/DVOBC_CLKINT#
AGP_AD14/DVOB_FLD/STL
AGP_AD15
AGP_AD16/DVOC_VSYNC
AGP_AD17/DVOC_HSYNC
AGP_AD18/DVOC_BLANK#
AGP_AD19/DVOC_D0
AGP_AD20/DVOC_D1
AGP_AD21/DVOC_D2
AGP_AD22/DVOC_D3
AGP_AD23/DVOC_D4
AGP_AD24/DVOC_D7
AGP_AD25/DVOC_D6
AGP_AD26/DVOC_D9
AGP_AD27/DVOC_D8
AGP_AD28/DVOC_D11
AGP_AD29/DVOC_D10
AGP_AD30/DVOC_INT#/DPMS_CLK
AGP_AD31/DVOC_FLD/STL

AJ6 LM_RCLK
AG6 LM_GCLK

VCC

<16> RTCCLK

1.5V level clock

NC

(DVOA port)

AGP
Interface

AG11LM_RQ0
AJ12 LM_RQ1
AG12LM_RQ2
AH13LM_RQ3
AG13LM_RQ4
AJ13 LM_RQ5
AG14LM_RQ6
AJ14 LM_RQ7

+3VS

U47
1

Display
Interface

AH7 LM_CMD
AF7 LM_SCK
AJ7 LM_SIO

<15> DVO_STALL

2 @2.2K DVOA_D1

DVO_CLKIN
DVO_BLANK#
DVO_VSYNC
DVO_HSYNC
IO_I2CCLK
IO_I2CDATA
DVO_CLK#
DVO_CLK

AC28AGP_ST0/ZV_D14
AC29AGP_ST1/ZV_D13
AB27AGP_ST2/ZV_D12

DVO_INT#
DVO_STALL

J29
J28
K26
K25
L26
J27
K29
K27
M29
M28
L24
M27
N29
M25
N26
N27
R25
R24
T29
T27
T26
U27
V27
V28
U26
V29
W29
V25
W26
W25
W27
Y29

AGP_ADSTB0/DVOB_CLK
AGP_ADSTB#0/DVOB_CLK#
AGP_ADSTB1/DVOC_CLK
AGP_ADSTB#1/DVOC_CLK#
AGP_SBSTB/ZV_D4
AGP_SBSTB#/ZV_D3
AGP_FRAME#/M_DDC2_DATA
AGP_IRDY#/M_I2C_CLK
AGP_TRDY#/M_DDC2_CLK
AGP_STOP#
AGP_DEVSEL#/M_I2C_DATA
AGP_REQ#/ZV_CLK
AGP_GNT#/ZV_D15
AGP_PAR

DAC_VSYNC
DAC_HSYNC
DAC_RED#
DAC_GREEN#
DAC_BLUE#
DAC_RED
DAC_GREEN
DAC_BLUE
IO_DDC1CLK
IO_DDC1DATA
DAC_REFSET

AGP_ST0
AGP_ST1
AGP_ST2

<15> DVO_HSYNC
<15> DVO_VSYNC
<15> DVO_D1
<15> DVO_D0
<15> DVO_D3
<15> DVO_D2
<15> DVO_D5
<15> DVO_D4
<15> DVO_D6
<15> DVO_D9
<15> DVO_D8
<15> DVO_D11
<15> DVO_D10

2 @2.2K DVOA_D6
2 2.2K DVOA_D5

R173 1

AGP_CBE#0/DVOB_D7
AGP_CBE#1/DVOB_BLANK#
AGP_CBE#2/ZV_VSYNC
AGP_CBE#3/DVOC_D5

AB26AGP_PIPE#/ZV_D10
AB29AGP_WBF#/ZV_D9
AB25AGP_RBF#/ZV_D11

L29
L28
U29
U28
AA27
AA28
AGP_FRAME#
R29
AGP_IRDY#
P26
AGP_TRDY#
P27
AGP_STOP#
N25
AGP_DEVSEL# R28
AGP_REQ#
AC27
AGP_GNT#
AD29
AGP_PAR
P28

R146 1
R144 1

AC21
AF21
AF24

AF26
AG27

F5
J5
M5
R5
V5
AA5
AD5
AG5
E2
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H

VCCA_DAC
VCCA_DAC

AF6
AE7
AC9
AC8
VCCPCMOS_LM
VCCPCMOS_LM
VCCPCMOS_LM
VCCPCMOS_LM

G10
G20
VCCQ_SM
VCCQ_SM

AE6
G7
VCCA_HPLL
VCCA_CPLL

N24
W23

J26
M26
R26
V26
AA26
L23
AA23
U24
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP

J24
F26

Power
Interface

<15> DVO_CLK
<15> DVO_CLK#

L27
P29
R27
T25

<15> DVO_D7
<15> DVO_BL#

AGP_SBA0/ZV_D8
AGP_SBA1/ZV_D7
AGP_SBA2/ZV_D6
AGP_SBA3/ZV_D5
AGP_SBA4/ZV_D2
AGP_SBA5/ZV_D1
AGP_SBA6/ZV_D0
AGP_SBA7/ZV_HREF

VCCQ_AGP
VCCQ_AGP

AA29
AA24
AA25
Y24
Y27
Y26
W24
Y28

VCCP_HUB
VCCP_HUB

2 DVO_STALL
@100K_0402

AE25
AD23

2 DVO_INT#
100K_0402

1
R129

U7C

VCCP_IO
VCCP_IO

1
R131

C167
.1UF_0402

+1.5VS

+VTT

VSSA_DPLL1 <9>

C278
68PF

V14
V15
V16
AE16
AE15
AD15
AD16

@8.2K_0402
2 AGP_RBF#

R150
1

VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM

@8P4R_8.2K
+1.5VS

0_0402
2

2
1
C170
.1UF_0402

+3V

L45
FBM-11-201209-601T
R117
1
2 VCCA_DPLL1 1

C290

.1UF_0402

+VTT

Place close to AE16,


AE15 of GMCH

.01UF_0402

VCCP_DVO
VCCP_DVO
VCCP_DVO

AGP_REQ#
AGP_GNT#
AGP_PIPE#
AGP_WBF#

C632

+1.8VS

+3V

.1UF_0402
2
1

AC20
F25

8
7
6
5

C281

VCCA_DPLL0
VCCA_DPLL1

1
2
3
4

Layout note :

VCCADPLL
VCCA_DPL L

+1.8VS
RP9

+VTT

+1.5VS

VSSA_DPLL0 <9>
+1.5VS

Almador-M GMCH(3/3)
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

10

of

41

Layout note :

Layout note :

Distribute as close as possible


to VCCPCMOS_LM. (GMCH pin
AF6, AE7, AC9, AC8)

Distribute as close as possible


to GMCH Processor Quadrant .
+VTT

+1.8VS

C288

C269

@.01UF_0402

C268
.01UF_0402

.1UF_0402 @.1UF_0402

C282

C238
.1UF_0402
2

C224
.1UF_0402

1
C220
.1UF_0402
2

C206
.1UF_0402
2

C207
.1UF_0402
2

C208
.1UF_0402

1
C198
.1UF_0402
2

C193
.1UF_0402
2

C177
.1UF_0402
2

C169
.1UF_0402

Layout note :

1
2

C225
.1UF_0402

C239
.1UF_0402

Distribute as close as possible


to GMCH Local Memory Quadrant .

1
C256
.1UF_0402
2

C286
.1UF_0402
2

C291
.1UF_0402
2

C247
.1UF_0402

1
C237
.1UF_0402
2

C219
.1UF_0402
2

C203
.1UF_0402
2

C158
.1UF_0402

+VTT

+1.8VS

C254

C186

.1UF_0402

+
C304
22UF_10V_1206

.01UF_0402
2

.1UF_0402

C275

82PF

C258

.1UF_0402

C156

.1UF_0402

2
C

C279

82PF

C252

1
C23
220UF_D2_4V

C27
220UF_D2_4V

+VTT

+VTT

Layout note :
Distribute as close as possible
to GMCH AGP/DVO Quadrant .

C271
.1UF_0402
+1.5VS

C274
.1UF_0402
2

C246
.1UF_0402
2

C236
.1UF_0402
2

C223
.1UF_0402

1
C213
.1UF_0402
2

C204
.1UF_0402
2

C187
.1UF_0402
2

C163
.1UF_0402

1
C303
220UF_D2_4V

+VTT
+

C251
.1UF_0402

C242
.1UF_0402
2

C285
82PF
2

C232
.1UF_0402
2

C209
.1UF_0402
2

C272
82PF
2

C262
.1UF_0402
2

C240
.1UF_0402
2

C299
82PF
2

C250
.1UF_0402
2

C287
.1UF_0402
2

C296
82PF
2

C255
.1UF_0402
2

C214
.1UF_0402

22UF_10V_1206

C276
.1UF_0402
2

C295
.1UF_0402
2

C265
.1UF_0402
2

C257
.1UF_0402

1
C245
.1UF_0402
2

C243
.1UF_0402
2

C244
.1UF_0402
2

C221
.1UF_0402

C273

C122
@220UF_D2_4V

Layout note :

+VTT

+3V

C197
.1UF_0402

.1UF Cap Used X7R

C181
.1UF_0402
2

C264
.1UF_0402

1
C267
.1UF_0402
2

C127
@220UF_D2_4V

+
B

Distribute as close as possible


to GMCH System Memory Quadrant .

+
C148
.1UF_0402
2

C166
82PF
2

C150
.1UF_0402
2

C147
.1UF_0402
2

C179
82PF
2

C139
.1UF_0402
2

C154
.1UF_0402
2

C284
82PF
2

C168
.1UF_0402
2

C162
.1UF_0402
2

C171
82PF
2

C140
.1UF_0402
2

C159
.1UF_0402
2

C133
22UF_10V_1206

+VTT

1
C138
.1UF_0402

C149
.1UF_0402

C280
.1UF_0402
2

C300
10UF_10V_1206

+3V
C306
10UF_10V_1206

Layout note :
Distribute as close as possible
to IO Quadrant .
+3V

1
C155
.1UF_0402

C137
.1UF_0402
2

C125
22UF_10V_1206

Compal Electronics, Inc.

Title

GMCH-M Decoupling
Size

Document Number

Rev
2

ADY11 LA-1181
Date:
5

Friday, November 16, 2001

Sheet
1

11

of

41

Layout note :
One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 0) pin .

+3V

C70
.1UF_0402

C66
.1UF_0402

C333
.1UF_0402
2

1
2

C67
.1UF_0402

C332
.1UF_0402

C65
.1UF_0402

C327
.1UF_0402

C347
.1UF_0402

C334
.1UF_0402

C69
.1UF_0402

1
C328
.1UF_0402
2

C71
.1UF_0402

C68
.1UF_0402

C331
.1UF_0402

C335
.1UF_0402

C329
.1UF_0402

C72
.1UF_0402

C330
.1UF_0402

+3V

C316
22UF_10V_1206

SM_DQ[0..63] <9,13>

+3V

+3V
JP21

SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47

System S MBus Select


SM_SEL#
0=SODIMM0 ;
1=SODIMM1

SMD_CLK0

<9> SMD_CLK0
<9,13>
<9,13>
<9>
<9>

SM_RAS#
SM_WE#
SM_CS#0
SM_CS#1

SM_RAS#
SM_WE#
SM_CS#0
SM_CS#1

+3VS
1

SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51

R268
10K_0402

<16> SM_SEL#

SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55

SM_SEL
D
Q17

SM_SEL# 2
G

SM_MA6
SM_MA8

<9,13> SM_MA6
<9,13> SM_MA8

2N7002

SM_MA9
SM_MA10

<9,13> SM_MA9
<9,13> SM_MA10

SM_DQM6
SM_DQM7

<9,13> SM_DQM6
<9,13> SM_DQM7

SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59

SM_SEL

R184
10K_0402

R48
10K_0402
2

SODIMM0_SMDAT0

3
S

R183
10K_0402

SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

SM_SEL#

+3V

Q16
2N7002

Q19

CKE0/RFU
VCC
CAS#/RFU
CKE1/RFU
A12/RFU
A13/RFU
CLK1/RFU
VSS
DQ70/RFU
DQ71/RFU
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
BA0
VSS
BA1
A11
VCC
DQMB6/CE6#
DQMB7/CE7#
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

SM_DQM0
SM_DQM1
SM_MA3
SM_MA4
SM_MA5

SM_DQM0 <9,13>
SM_DQM1 <9,13>
2

SM_MA3 <9,13>
SM_MA4 <9,13>
SM_MA5 <9,13>

SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11
SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15

SM_CKE0
SM_CAS#
SM_CKE1
SM_MA12
1
2
R50
0_0402

SM_CKE0 <9>
SM_CAS# <9,13>
SM_CKE1 <9>
SM_MA12 <9,13>
SMD_CLK1

SMD_CLK1 <9>

SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19

SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_MA7
SM_BA0
SM_BA1
SM_MA11
SM_DQM2
SM_DQM3

SM_MA7 <9,13>
SM_BA0 <9,13>
SM_BA1 <9,13>
SM_MA11 <9,13>
SM_DQM2 <9,13>
SM_DQM3 <9,13>

SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27

Place closely to DIMM0


SM_DQ28
SM_DQ29
SM_DQ30
SM_DQ31

SMD_CLK0

@10

@10

C326
@15PF

C73
4

@15PF

SODIMM1_SMDAT1 <13>

+5VS
G

2N7002
3

1 Q18
2N7002

SODIMM_SMCLK

<14,16,18> SMB_CLK

Compal Electronics, Inc.

SODIMM_SMCLK <13>
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.

SO-DIMM SLOT0 /Decoupling & DIMM Select


Document Number

Rev
2

ADY11 LA-1181

Date:
A

R49

SODIMM_SMCLK

DIMM0

SMD_CLK1

R185

RFU/CLK0
VCC
RFU/RAS#
WE#
RE0#/S0#
RE1#/S1#
RFU/EDO_OE#
VSS
RFU/DQ66
RFU/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/DQMB2
CE3#/DQMB3
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC

SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7

SO-DIMM144-Reverse

<14,16,18> SMB_DATA

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

SM_DQ0
SM_DQ1
SM_DQ2
SM_DQ3

<9,13> SM_MA0
<9,13> SM_MA1
<9,13> SM_MA2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

12

SM_MA0
SM_MA1
SM_MA2

VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
DQMB4/CE4#
DQMB5/CE5#
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
DQ68/RFU
DQ69/RFU

SM_DQM4
SM_DQM5

<9,13> SM_DQM4
<9,13> SM_DQM5
2

VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CKE0#DQMB0
CKE1#/DQMB1
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RFU/DQ64
RFU/DQ65

SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

12

SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35

Friday, November 16, 2001


G

Sheet

12
H

of

41

Layout note :
One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 1) pin .

1
C52
.1UF_0402

C51
.1UF_0402

C63
.1UF_0402

C57
.1UF_0402

C56
.1UF_0402

C48
.1UF_0402

C54
.1UF_0402

C55
.1UF_0402

C49
.1UF_0402

C46
.1UF_0402

C47
.1UF_0402

C50
.1UF_0402

C62
.1UF_0402

C53
.1UF_0402

C58
.1UF_0402

C61
.1UF_0402

1
C60
.1UF_0402

C59
.1UF_0402

+3V

+3V

C44
22UF_10V_1206

SM_DQ[0..63] <9,12>
+3V

+3V
JP13

SMD_CLK2

<9> SMD_CLK2
<9,12>
<9,12>
<9>
<9>

SM_RAS#
SM_WE#
SM_CS#2
SM_CS#3

SM_RAS#
SM_WE#
SM_CS#2
SM_CS#3

SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19
SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_MA6
SM_MA8

<9,12> SM_MA6
<9,12> SM_MA8

SM_MA9
SM_MA10

<9,12> SM_MA9
<9,12> SM_MA10

SM_DQM2
SM_DQM3

<9,12> SM_DQM2
<9,12> SM_DQM3

SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27
SM_DQ28
SM_DQ29
SM_DQ30
SM_DQ31
SODIMM1_SMDAT1

<12> SODIMM1_SMDAT1

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

RFU/CLK0
VCC
RFU/RAS#
WE#
RE0#/S0#
RE1#/S1#
RFU/EDO_OE#
VSS
RFU/DQ66
RFU/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/DQMB2
CE3#/DQMB3
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC

CKE0/RFU
VCC
CAS#/RFU
CKE1/RFU
A12/RFU
A13/RFU
CLK1/RFU
VSS
DQ70/RFU
DQ71/RFU
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
BA0
VSS
BA1
A11
VCC
DQMB6/CE6#
DQMB7/CE7#
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

SM_DQM4
SM_DQM5

SM_DQM4 <9,12>
SM_DQM5 <9,12>

SM_MA3
SM_MA4
SM_MA5

SM_MA3 <9,12>
SM_MA4 <9,12>
SM_MA5 <9,12>

SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47

SM_CKE2
SM_CAS#
SM_CKE3
SM_MA12
1
2
R46
0_0402

SM_CKE2 <9>
SM_CAS# <9,12>
SM_CKE3 <9>
SM_MA12 <9,12>
SMD_CLK3

SMD_CLK3 <9>
3

SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51
SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55
SM_MA7
SM_BA0

SM_MA7 <9,12>
SM_BA0 <9,12>

SM_BA1
SM_MA11

SM_BA1 <9,12>
SM_MA11 <9,12>

SM_DQM6
SM_DQM7

Place closely to DIMM1

SM_DQM6 <9,12>
SM_DQM7 <9,12>

SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59

SMD_CLK2

SMD_CLK3

SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15

SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39

R47

R44

@10

@10
12

SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11

SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35

C64
@15PF

SODIMM_SMCLK

C45
@15PF

SM_MA0
SM_MA1
SM_MA2

<9,12> SM_MA0
<9,12> SM_MA1
<9,12> SM_MA2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

SM_DQM0
SM_DQM1

<9,12> SM_DQM0
<9,12> SM_DQM1

VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
DQMB4/CE4#
DQMB5/CE5#
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
DQ68/RFU
DQ69/RFU

12

SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7

VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CKE0#DQMB0
CKE1#/DQMB1
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RFU/DQ64
RFU/DQ65

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

SM_DQ0
SM_DQ1
SM_DQ2
SM_DQ3

SODIMM_SMCLK <12>

SO-DIMM144-Normal

DIMM1

EMI Clip PAD for Memory Door


PAD10

PAD11
1

PAD12
1

PAD-2.5X3

PAD-2.5X3

PAD19
1

PAD-2.5X3

PAD14

PAD16

1
PAD-2.5X3

1
PAD-2.5X3

PAD18
1

PAD-2.5X3

Compal Electronics, Inc.


1

PAD-2.5X3

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:

SO-DIMM SLOT1 & Decoupling


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

13

of

41

+3V_CLK
L24
FBM-11-201209-601T
Width=40 mils
1
2
1

L64
FBM-11-201209-601T
1
2

+
C77
.1UF_0402

C78
.1UF_0402

C82
.1UF_0402
2

C76
.1UF_0402

C88
.1UF_0402

C87
.1UF_0402

C89
.1UF_0402

C95
22UF_10V_1206

+3VS

+3VS_VDD48M
1

L25
1

10_0805
2

+3VS

XTAL_OUT

GND_CORE

R61

CPUCLKT2

CLK_BCLK

45

SEL2
SEL1
SEL0

R56

2 0_0402

25
34
53

2
2 33_1%
61.9_1%

R8 1
CLK_BCLK# R12 1

2 61.9_1%
2 33_1%

CPU_CLKC2

PWR_DWN#
PCI_STOP#
CPU_STOP#

CPUCLKT1

44
49

CLK_HT

2
2 33_1%
61.9_1%

R57

2 10K_0402 43

CPUCLKC1
MULT0

CLKOSC_VCH

33
35

R53

2 33_0402

R70
240K

SDATA
SCLK

R51

2 221_1%

R52

2 22_0402
* 33

CLK_ICH48M

39

R59

2 10_0402

CLKDREF

38

R64

1
1

2 33_0402
2
33_0402

CLK_ICH14M

56

CPUCLKC0
3V66_0/DRCG
3V66_1/VCH_CLK

Please clos ely pin42

<8> CLK_DREF

<16> CLK_ICH14
<26> CLK_14M_SIO

R63

66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2

IREF

48MHZ_USB

PCICLK_F2
PCICLK_F1
PCICLK_F0

48MHZ_DOT

REF
GND_REF
GND_PCI
GND_PCI
GND_3V66
GND_3V66
GND_48MHZ
GND_IREF
GND_CPU

<16> CLK_ICH48

42

66MHZ_IN/3V66_5

CLK_GHT <8>
2

Place all these Block's


Components near
GMCH

R83 1
CLK_ITP# R82 1

2 61.9_1%
2 @33_1%

51

CLK_GHT# <8>
CLK_ITPP <7>

Place all these Block's


Components near ITP
port

R78
475_1%

CLK_ITPP# <7>

24
23
22
21
7
6
5
18
17
16
13
12
11
10

CLK_GBOUT <8>

CLKGBIN
R65
CLKICHHUB R71
CLKPCI_F2
CLKPCI_F1
CLKPCI_F0

R72
R67
R66

CLKPCI_LPC
CLKPCI_SIO
CLKPCI_PCM
CLKPCI_LAN

1
1

2 33_0402
2 33_0402

1
1
1

2 33_0402
2 33_0402 PCIF1
2 33_0402 PCIF0

R75
R74
R68
R73

1
1
1
1

2
2
2
2

R433 1

2 0_0402

R69
2
33_0402

CLK_GBIN <8>
CLK_ICHHUB <16>

C92
1
10PF_0402

CLK_ICHPCI <16>

33_0402
33_0402
33_0402
33_0402

4
9
15
20
31
36
41
47

W320-04

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

2
2 33_1%
61.9_1%

CLK_ITP

52

Close to CLKGEN
<15> CLK_OSC_VCH

2 61.9_1%
2 33_1%

1
R81 1
R80

CLK_HT#

48

1
29
30

R41 1
R43 1

VTT_PWRGD#

CPUCLKT0
<12,16,18> SMB_DATA
<12,16,18> SMB_CLK

CLK_HCLK# <5>

R45
475_1%

28

<5,28> VTT_PWRGD#

CLK_HCLK <5>

Place all these Block's


Components near CPU

1
R42 1
R40

<16,28> SLP_S1#
<16> PM_STPPCI#
<16> PM_STPCPU#

1
R16 1
R17

R13
475_1%

R54
@0_0402

@0_0402
2

C94
10UF_10V_1206

27

40
55
54

2
C86
.1UF_0402

1
R55
@0_0402

+3VS
L23
FBM-11-201209-601T
1
2

26

2
1
@10PF_0402

2
C93

H_BSEL1
H_BSEL0

<5> H_BSEL1
<5> H_BSEL0

VDD_CORE

Y1
14.318MHZ

R60

1K_0402 1K_0402

10K_0402

XTAL_IN

R62

caps are internal


to CK_TITAN

1
R58

1
@10PF_0402

2
C90

+3VS

+3VS_CLKVDD

VDD_REF
VDD_PCI
VDD_PCI
VDD_3V66
VDD_3V66
VDD_48MHZ
VDD_CPU
VDD_CPU

Place Crystal within 500 mils of CK_Titan


+3VS

U9

+3VS

C98
10UF_10V_1206
2

1
8
14
19
32
37
46
50

*BLM21A601SPT

C75
.1UF_0402

CLK_PCI_LPC <27>
CLK_PCI_SIO <26>
CLK_PCI_PCM <21>
CLK_PCI_LAN <20>

Place near CPU

or IC S 9508-05

R33
PCIF1

CLK_CPU_APIC <5>
1

Note:
CPU_CLK[2:0] needs to be running in C3, C4.

26.7_1%
2

R32
137_1%

Place near ICH

R354
1

51.1_1%
2

CLK_ICHAPIC <16>
1

PCIF0

R355
348_1%

0 Ohm resistor for ICH3 d oesn't


need to support APIC fu nction

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.

Clock Generator
Document Number

Rev
2

ADY11 LA-1181

Date:

Friday, November 16, 2001


G

Sheet

14
H

of

41

+3VS
JP9
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

Please closely to VCH Conn. power pin

<10> DVO_VSYNC
<10> DVO_HSYNC

B+

+12VALW

C161

.1UF_25V

<10>
<10>
<10>
<10>
<10>

.1UF_0402

<10> DVO_D2
<10> DVO_D0
<10> DVO_D1

C172

DVO_D4
DVO_D5
DVO_D8
DVO_D3
DVO_D7

<10> DVO_CLK
<10> DVO_CLK#
+1.5VS

<10>
<10>
<10>
<10>
<10>

C241
.1UF_0402

C217
.1UF_0402

<10> DVO_STALL

+1.8VS

C218
.1UF_0402

C211
.1UF_0402

C195
.1UF_0402

+3VS

+5VS

+5VALW

DVO_D11
DVO_D9
DVO_D6
DVO_D10
DVO_BL#

<14> CLK_OSC_VCH

G1
G2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G21 G22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
G39 G40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
G59 G60

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

+12VALW
B+

+5VALW
+5VS
+5VS

+1.8VS
LTVCK <10>
LTVDA <10>
DAC_BRIG <28>

DISPOFF#

SMB_EC_CK1 <5,28,29,33>
SMB_EC_DA1 <5,28,29,33>
INVT_PWM <28>
ENABKL <29>

M_SEN#

<28> BKOFF#

5
2

<29> ENABKL

DISPOFF#

4
U12
TC7ST08FU

VCH_RST#
+1.5VS
GMBSDA <10>
GMBSCL <10>

VCH Conn.

R135
1

0_0402
2

R139
1

@0_0402
2

PCIRST# <8,16,20,21,26,27,28>

EC_VCHRST# <29>

CRTVCC
CRTVCC
+3VS

3VDDCDA <10>

Q5
2N7002

C623
@3.3PF
2

C622

C621

@3.3PF @3.3PF

3
S

C106
.1UF_0402

D5 @DAN217

D4 @DAN217

2
G

Q6
2N7002

1
1

D3 @DAN217

R98
4.7K_0402

2
G

R101
4.7K_0402
1

R103
0_0402

CRTVCC

R97
10K_0402

1
R1
10K_0402
2

C110
.1UF_0402

+3VS

3VDDCCL <10>

+1.8VS
JP2

<10> CRT_G

CRTB
C8

3.3PF

C6

3.3PF

3.3PF
5

C7

R4
75_1%

R5
75_1%

R3
75_1%

CRTG

<10> CRT_B
CRTVCC

CRTR

1
2
L14 FCM2012C-800(0805)
L15
1
2
FCM2012C-800(0805)
L13
1
2
FCM2012C-800(0805)

+12VALW

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

M_SEN#

DDC_MONID0
<10> CRT_R

CRT Connector

CRT CONN.
1

<10> CRT_HSYNC

C2

C105

C104 C103

27PF
2

2
<10> CRT_VSYNC

C4

27PF

.1UF_0402
2

+5VS

C3
1

2
D

1
2
FBM-11-160808-121

C9

Q1
SI2302DS
5

2
G
Q15
2N7002

<28> CRT_ON#

L5

CRTVCC

2
G
1

2
100K_0402

47K_0402
1
R264

L4
1
2
FBM-11-160808-121

4
74AHCT1G125GW
U2

R261

100PF_0402 100PF_0402
100PF_0402
100PF_0402

74AHCT1G125GW
U10
4

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

VCH Conn. & CRT


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

15

of

41

D25
+3VALW

RB751V

D13

33_0402

Place closely to
ICH3-M

CLK_ICH48
1

R336

R369

@10

10_0402
12

12

CLK_ICH14

C554

K2
K5
N1
R2

<18>
<18>
<18,21>
<18,20>
<18>

GNT#0
GNT#1
GNT#2
GNT#3
GNT#4

A4
E3
D2
D5
B4

<18>
<18>
<18,21>
<18,20>
<18>

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

D3
F4
A3
R4
E4

C574

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

VSS

ICH3-M

R446
@2.4M_1%

C477
1UF

32.768KHZ

R265
1K_0402

PIRQA#
PIRQB#
PIRQC#
PIRQD#
GPIO2
GPIO3
GPIO4
GPIO5

HubLink
Interface

1
12
2
1
12
2

ICH_WAKE_UP#
2 R298
1 33_0402
PCIRST# <8,15,20,21,26,27,28>
SERR# <18,20,21>
STOP# <18,20,21>
TRDY# <18,20,21,27>

GATEA20 <28>
H_A20M# <5>

+1.5VS

Y22
V23
AB22
J22
AA21
AB23
AA23
Y21
W23
U22
W21
Y23
U23

R287
@10K_0402
2

SM_INTRUDER# <18>
SMLINK0 <18>
SMLINK1 <18>
SMB_CLK <12,14,18>
SMB_DATA <12,14,18>
SMB_ALERT# <18>

R288 1

H_FERR# <5>
H_IGNNE# <5>
H_INIT# <5>
H_INTR <5>
H_NMI <5>
H_PWRGD <5>
KBRST# <28>

2 0_0402

<5,32> H_DPSLP#
(for use if CPU unable
to support DPSLP#)

H_SMI# <5>
H_STPCLK# <5>
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

HUB_PD[0..10]

HUB_PD[0..10] <8>
CLK_ICHHUB

+VS_HUBREF
+VS_HUBVSWING

CLK_ICHHUB
R440

15PF

IRDY# <18,20,21>
PAR <20,21>
PERR# <18,20,21>
PLOCK# <18,21>

Y6
AC3
AB2
AC4
AB5
AC5

L22
M21
M23
N20
P21
R22
R20
T23
M19
P19
N19

CLK_ICHHUB <14>
HUB_PSTRB <8>
HUB_PSTRB# <8>

HUB_ICH_RCOMP

C518

R306
33_0402

1
R335

C514
5PF_0402

2
36.5_1%

C539
.01UF_0402

Layout note:
Locate J1 and R265 on bottom side and
easy access through memo ry door

C534
.01UF_0402

Close to ICH3-M.

with

1. Place R_G and R_H in middle of Bus.

R_G

EEPROM
Interface

J1
JOPEN

C460
12PF
2

R280 15K

X2

C465
12PF

R319
301_1%

RTC_X1
RTC_X2

2
10M

LAN
Interface

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

CLK_ICHPCI <14>
DEVSEL# <18,20,21>
FRAME# <18,20,21,27>
PCI_REQA# <18>
PCI_REQB# <18>

@1K_0402

1
R282

R_H

+VS_HUBVSWING
R318
301_1%

C532
.1UF_0402

<29> VLBA#

2
D9

BATTLOW#

1
2
R266 10K_0402

+3VALW

1SS355

2
10M

CLK_ICH14
CLK_ICH48

<14> CLK_ICH14
<14> CLK_ICH48
+RTCVCC

HUB Interface VSwing Voltage

1
R281

2
@22M

+1.8VS

RTC_VBIAS

1
R445

CLK_ICHAPIC

Clocks

+RTCVCC

2 +R_VBAIS C482 1
1K_0402
.047UF

J19
J20
J21
B1
C1
B2
A2
A6
B5
C5
A5
AB14
W19
H22

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4

PT Change la yout pad

1
R273

CPU_A20GATE
CPU_A20M#
CPU_DPSLP#
CPU_FERR#
CPU_IGNNE#
CPU_INIT#
CPU
CPU_INTR
Interface
CPU_NMI
CPU_PWRGOOD
CPU_RCIN#
CPU_SLP#
CPU_SMI#
STPCLK#

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

5PF_0402

@15PF

C/BE#0
C/BE#1
C/BE#2
C/BE#3

<20,21,27>
<20,21,27>
<20,21,27>
<20,21,27>

SMB_ALERT#/GPIO11

ICH3-M (1/2)

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

R438

PCI
Interface

CLK_ICHPCI

2 AC_RST#

<23,25> AC97_RST#

@27PF
2

@27PF

C607

CLK_ICHPCI
R311

C606

22_0402
IAC_SYNC

<23,25> IAC_SYNC

SM_INTRUDER#
SMLINK0

System
SMLINK1
Managment SMB_CLK
Interface SMB_DATA

T5
M3
F1
C4
D4
B6
B3
N3
G5
M2
M1
W1
Y1
L5
H2
H1

PIRQA#
PIRQB#
PIRQC#
PIRQD#

Interrupt
Interface

C559
10PF_0402

+3VS

10_0402

PCI_CLK
PCI_DEVSEL#
PCI_FRAME#
PCI_GPIO0/REQA#
PCI_GPIO1/REQB#/REQ5#
PCI_GPIO16/GNTA#
PCI_GPIO17/GNTB#/GNT5#
PCI_IRDY#
PCI_PAR
PCI_PERR#
PCI_LOCK#
PCI
PCI_PME#
Interface
PCI_RST#
PCI_SERR#
STOP#
PCI_TRDY#

HUB_VSWING
HUB_VREF
HUB_RCOMP
HUB_PSTRB#
HUB_PSTRB
HUB_PAR
HUB_CLK

R393
IAC_SDATAO

<23,25> IAC_SDATAO

unMUX
GPIO

2
10K_0402
2
10K_0402
2
10K_0402
2
10K_0402

PIRQA#
PIRQB#
PIRQC#
PIRQD#

L19
L20
K19
P23
N22
R19
T19

1
2
R409 @10K_0402

+3VS

<18,21>
<18,20>
<18>
<18>

SDATAO

SDATA_IN1

<25> SDATA_IN1

LPC
Interface

1
R424
GPIO3 1
R425
GPIO4 1
R426
GPIO5 1
R427

Place closely to
ICH3-M

2
10K_0402

AC'97
Interface

EEP_SHCLK
EEP_DOUT
EEP_DIN
EEP_CS

1
R411

Geyserville

D10
E8
D8
E9

SDATA_IN0

<23> SDATA_IN0

Power Management

LAN_RSTSYNC
LAN_JCLK
LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_RXD2
LAN_RXD1
LAN_RXD0

2
@10K_0402

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

A1
A13
A16
A17
A20
A23
B8
B10
B13
B14
B15
B18
B19
B20
B22
C3
C6
F19
C14
C15
C16
C17
C18
C19
C20
C21
C22
D9
D13
D16
D17
D20
D21
D22
E5

1
R396

J2
K1
J4
K3
H5
K4
H3
L1
L2
G2
L4
H4
M4
J3
M5
J1
F5
N2
G4
P2
G1
P1
F2
P3
F3
R1
E2
N4
D1
P4
E1
P5

D7
C9
A10
C10
B9
A9
A8
C8

IAC_BITCLK

<23,25> IAC_BITCLK

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

EC_SMI#

<26,28> EC_SMI#

GPIO2

<20,21,27> AD[0..31]

10_0402
2 ICH_RI#

1
RB751V

IRQ14 <18,19>
IRQ15 <18,19>
SIRQ <18,21,26>

INT_APICCLK
INT_APICD0
INT_APICD1
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#/GPIO2
INT_PIRQF#/GPIO3
INT_PIRQG#/GPIO4
INT_PIRQH#/GPIO5
INT_IRQ14
INT_IRQ15
INT_SERIRQ

U37A

IDE_PATADET
EC_SMI#
ICH_SCI#
ICH_L_OUT#
PIDEPWR

+3VS

33_0402

1 2

2
10K_0402

U20
Y20
V19

1
R285

R392

B7
D11
B11
C11
C7
A7

<10> AGP_BUSY#

0_0402
IDE_PATADET

BATTLOW#

V2
W2
Y4
Y2
W3
W4
Y3

<32> PM_DPRSLPVR
<18,20,21,26> PM_CLKRUN#
PM_C3_STAT#
R277
PM_PWROK 1
2

RB751V

R352

CLK_ICHAPIC <14>
PICD0 <5>
PICD1 <5>

GPIO_7
GPIO_8
GPIO_12
GPIO_13
GPIO_25
GPIO_27
GPIO_28

2 PBTN_OUT#

<29> PWRBTN_OUT#

PBTN_OUT#

CLK_ICHAPIC

+3VALW

D26
<29> SWI#

V1
U3
T3
U2
T2
U4
U1

D11

ICH_RI#

1
2
R423 10K_0402

SM_SEL# <12>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
LPC_DRQ#1
LPC_FRAME#

RB751V

R391
@22_0402

PM_GMUXSEL/GPIO23
PM_CPUPREF#/GPIO22
PM_VGATE/VRMPWRGD

ICH_THRM# 1
2
R308 10K_0402

CLK_14
CLK_48
CLK_RTEST#
CLK_RTCX1
CLK_RTCX2
CLK_VBIAS

D14
1

<28> EC_THRM#

R408
10K_0402

RB751V

Place closely to
ICH3-M

LAD0 <26>
LAD1 <26>
LAD2 <26>
LAD3 <26>
LDRQ#0 <26>
LDRQ#1
LFRAME# <26>
PIDEPWR <19>

ICH_THRM#

<26> SUS_STAT#
<10> RTCCLK
<14> PM_STPPCI#
<14> PM_STPCPU#
<28> SLP_S5#
<28> SLP_S3#
+3VS <14,28> SLP_S1#
<30> RSMRST#
<18> ICH_RI#
<7> PM_PWROK

2
10K_0402

V4
Y5
AB3
V5
AC2
AB21
AB1
AA6
AA1
AA7
W20
AA5
AA2
V21
U21
AA4
AB4
U5

<29> LID_OUT#

1
R300

2 ICH_L_OUT#

@33PF_0402
2

J23
F20
RTC_RST# Y7
AC7
RTC_X1
AC6
RTC_X2
RTC_VBIAS AB7

D12
1

C595
1

<7,30> ICH_VGATE
<5> PM_CPUPERF#
<6,32> PM_GMUXSEL

1
IAC_BITCLK
AC_RST#
SDATA_IN0
1
SDATA_IN1
SDATAO
1
2 IAC_SYNC

1
2
R304 10K_0402

AC_BITCLK
AC_RST#
AC_SDATAIN0
AC_SDATAIN1
AC_SDATAOUT
AC_SYNC

ICH_SCI#

2
RB751V

PM_AGPBUSY#/GPIO6
PM_AUXPWROK
PM_BATLOW#
PM_C3_STAT#/GPIO21
PM_CLKRUN#/GPIO24
PM_DPRSLPVR
PM_PWRBTN#
PM_PWROK
PM_RI#
PM_RSMRST#
PM_SLP_S1#/GPIO19
PM_SLP_S3#
PM_SLP_S5#
PM_STPCPU#/GPIO20
PM_STPPCI#/GPIO18
PM_SUS_CLK
PM_SUS_STAT#
PM_THRM#

<28> SCI#

2 ICH_WAKE_UP#

<29> EC_WAKEUP#

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:

Intel ICH3-M
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001
D

Sheet

16

of

41

+3VS
+5VS

+3VS

+RTCVCC

+VCC_RTC

+3V

+3VALW
1

0_0402

100K_0402
2

1K_0402
C631
.1UF_0402

1
D23

<28,33,35> ACIN

Close ly Pin AB6

2
RB751V

ICH_ACIN

8P4R_10K

R451
R397

D10
1SS355
1

R248
1K_0402

8
7
6
5

1
2
3
4

R370
RP22
OVCUR#5
OVCUR#4
OVCUR#3
OVCUR#1

1K_0402
2

USBP0AV_VID4
USBP2-

0=I2C CTRL CPUVID select


1=Bus switch CPUVID select
OVCUR#0
OVCUR#1
OVCUR#2
OVCUR#3
OVCUR#4
OVCUR#5

<30> OVCUR#0
<30> OVCUR#2

U25

R453
1

<19> PIDERST#
+5VS

ICH_IDE_SRST#
<6>
<6>
<6>
<6>
<6>

@74AHCT1G125GW
5

<19> SIDERST#

0_0402
2
AC_VID0
AC_VID1
AC_VID2
AC_VID3
AC_VID4

AV_VID4
MB_ID0
MB_ID1

2
<28> EC_FLASH#

ICH_ACIN

<18> ICH_M_SEN#

E12
D12
C12
B12
A12
A11
H20
G22
F21
G19
E22
E21
H21
G23
F23
G21
D23
E23
B21

0_0402
2

R376
18.2_1%

+3VS

+3VALW

R395

0_0805

VCCPSUS

@10K_0402

10K_0402
2

R442

R441

H23
U19

+1.8VS

M/B ID

ICH_SPKR

<24> ICH_SPKR

R254
1

F17
F18
K14
E10
V8
V9

VCCA

Note:
R376=22.6_1% for B0(QB63 part)
R376=18.2_1% for B0(QB62 & SL5LF pa

E11
K6
K18
P6
P18
V10
V14
VCCCORE0
VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE5
VCCCORE6

P12
V15
V16
V17
V18

J18
M14
R18
T18
VCCPHL0
VCCPHL1
VCCPHL2
VCCPHL3

VCCP0
VCCP1

VCCPIDE0
VCCPIDE1
VCCPIDE2
VCCPIDE3
VCCPIDE4

G18
H18

F6
G6
H6
J6
M10
R6
T6
U6

A21
A22
VSS102
VSS103

VCCPPCI0
VCCPPCI1
VCCPPCI2
VCCPPCI3
VCCPPCI4
VCCPPCI5
VCCPPCI6
VCCPPCI7

B23

C23

E7
T21
D6
T1
C2
N/C0
N/C1
N/C2
N/C3
N/C4

VCCPCPU0
VCCPCPU1
VCCPCPU2

P14
U18
V22

VCCPAU 2
F9
F10

C13
W5
VCC5REFSUS1
VCC5REFSUS2

E6
W8

AB6
VCC_RTC

VCC5REF1
VCC5REF2

VCC1.8SUS 2

IDE
Interface

Power

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
IDE_PDDACK#
IDE_SDDACK#
IDE_PDDREQ
IDE_SDDREQ
IDE_PDIOR#
IDE_SDIOR#
IDE_PDIOW#
IDE_SDIOW#
IDE_PIORDY
IDE_SIORDY

VCCPSUS3/VCCPUSB0
VCCPSUS4/VCCPUSB1
VCCPSUS5/VCCPUSB2

VSS
VCCPSUS0
VCCPSUS1
VCCPSUS2

1
2

@10K_0402

ICH3-M (2/2)

Misc

SPKR

IDE_PDCS1#
IDE_PDCS3#
IDE_SDCS1#
IDE_SDCS3#
IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_SDA0
IDE_SDA1
IDE_SDA2

Power

USB_RBIAS

ICH3-M

10K_0402

F7
F8
K10

USB_LEDA#0/GPIO32
USB_LEDA#1/GPIO33
USB_LEDA#2/GPIO34
USB_LEDA#3/GPIO35
USB_LEDA#4/GPIO36
USB_LEDA#5/GPIO37
USB_LEDG#0/GPIO38
USB_LEDG#1/GPIO39
USB_LEDG#2/GPIO40
USB_LEDG#3/GPIO41
USB_LEDG#4/GPIO42
USB_LEDG#5/GPIO43

MB_ID1
R444

+1.8VS

USB
Interface

MB_ID0

R443

+3VS

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

0_0805
0_0805

VCCUSBBG/VCC_SUS8

R363
2

USB_PP0
USB_PP1
USB_PP2
USB_PP3
USB_PP4
USB_PP5
USB_PN#0
USB_PN#1
USB_PN#2
USB_PN#3
USB_PN#4
USB_PN#5

R402

R403

VCCPAUX0/VCCLAN3_3
VCCPAUX1/VCCLAN3_3

USBP2+

D19
A19
E17
B17
D15
A15
D18
A18
E16
B16
D14
A14

VCC_AUX0/VCCLAN1_8
VCC_AUX1/VCCLAN1_8
VCC_AUX2/VCCLAN1_8

+3VS

VCCREFSUS

VCC_SUS0
VCC_SUS1
VCC_SUS2
VCC_SUS3
VCC_SUS4
VCC_SUS5

U37B

USBP0+

FBM-11-201209-601T

E13
F14
K12
P10
V6
V7

Layout note The Cap c lose to


ICH3-M (< 1 inch)

+VCC_RTC

+1.5VS

AC15
AB15
AC21
AC22

PDCS1#
PDCS3#
SDCS1#
SDCS3#

AA14
AC14
AA15
AC20
AA19
AB20
W12
AB11
AA10
AC10
W11
Y9
AB9
AA9
AC9
Y10
W9
Y11
AB10
AC11
AA11
AC12

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

Y17
W17
AC17
AB16
W16
Y14
AA13
W15
W13
Y16
Y15
AC16
AB17
AA17
Y18
AC18

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

<19>
<19>
<19>
<19>

PDA0 <19>
PDA1 <19>
PDA2 <19>
SDA0 <19>
SDA1 <19>
SDA2 <19>
PDD[0..15] <19>

SDD[0..15] <19>

Y13
Y19
AB12
AB18
AC13
AC19
Y12
AA18
AB13
AB19

PDDACK# <19>
SDDACK# <19>
PDDREQ <19>
SDDREQ <19>
PDIOR# <19>
SDIOR# <19>
PDIOW# <19>
SDIOW# <19>
PDIORDY <19>
SDIORDY <19>

E14 VSS35
E15 VSS36
E18 VSS37
E19 VSS38
E20 VSS39
F22 VSS40
G3 VSS41
G20 VSS42
H19 VSS43
AA22VSS44
J5 VSS45
K11 VSS46
K13 VSS47
K20 VSS48
K21 VSS49
K22 VSS50
K23 VSS51
L3 VSS52
L10 VSS53
L11 VSS54
L12 VSS55
L13 VSS56
L14 VSS57
L21 VSS58
L23 VSS59
M11 VSS60
M12 VSS61
M13 VSS62
M20 VSS63
M22 VSS64
N5 VSS65
N10 VSS66
N11 VSS67
N12 VSS68
N13 VSS69
N14 VSS70
N21 VSS71
N23 VSS72
P11 VSS73
P13 VSS74
P20 VSS75
P22 VSS76
R3 VSS77
R5 VSS78
R21 VSS79
R23 VSS80
T4 VSS81
T20 VSS82
T22 VSS83
V3 VSS84
AC23VSS85
V20 VSS86
W6 VSS87
W7 VSS88
W10 VSS89
W14 VSS90
W18 VSS91
W22 VSS92
Y8 VSS93
AA3
VSS94
AA8 VSS95
AA12VSS96
AA16VSS97
AA20VSS98
AB8 VSS99
AC1 VSS100
AC8 VSS101

1
2
C598 5PF_0402

0_0805

+V1.8_ICHLAN

L63
1

F15
F16

USBP2+
USBP2-

<30> USBP2+
<30> USBP2-

VCC1.8SUS
R389

VCC1.8SUS

VCC_USB0/VCC_SUS6
VCC_USB1/VCC_SUS7

+1.8VALW

1
2
C597 5PF_0402

+1.8VALW

+3VALW

VCCUSBPLL/VCC_SUS9

C573
1UF

C488
.1UF_0402
USBP0+
USBP0-

<30> USBP0+
<30> USBP0-

C602
.1UF_0402

VCC5REF

rt)

MB_ID0

MB_ID1

SST

PT

ST

QT

R346
+3VS

ICH_SPKR

Compal Electronics, Inc.

@1K_0402

Disable Timeo ut feature

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:

Intel ICH3-M
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001
D

Sheet

17

of

41

+3VS

+3VS
RP13

FRAME#
IRDY#
TRDY#
STOP#

10
9
8
7
6

SERR# <16,20,21>
DEVSEL# <16,20,21>
PERR# <16,20,21>
PLOCK# <16,21>

+1.5VS

10P8R_8.2K

RP21
<16>
<16>
<16>
<16>

1
2
3
4
5

PCI_REQA#
PCI_REQB#
REQ#0
REQ#1

10
9
8
7
6

REQ#2 <16,21>
REQ#3 <16,20>
REQ#4 <16>
SIRQ <16,21,26>

C499
.1UF_0402
2

C503
1UF

C517
.1UF_0402
2

+3VS

+3VS

<16,20,21,27>
<16,20,21>
<16,20,21,27>
<16,20,21>

1
2
3
4
5

+3VS

IRQ15 <16,19>
PIRQA# <16,21>
PIRQB# <16,20>
PIRQC# <16>

C490
.1UF_0402

C491
.1UF_0402

C523
.1UF_0402
2

C521
C479
.1UF_0402 47PF_0402
2

C568
.1UF_0402
2

C591
C563
.1UF_0402 47PF_0402

C566
.1UF_0402

1
2

C567
C608
.1UF_0402 47PF_0402

C485
.1UF_0402

C476
.1UF_0402

C610
47PF_0402

C611
.1UF_0402

C524
.1UF_0402

VCCPSUS
2

<16> GNT#4

2
@8.2K_0402
2
@8.2K_0402
2
@8.2K_0402

2
<16> GNT#0
<16,20> GNT#3

1
C576
47PF_0402

+3VS

C569
.1UF_0402

+3VS

10P8R_8.2K

1
R398
1
R400
1
R399

C596
22UF_10V_1206

+
C475
22UF_10V_1206

10
9
8
7
6

1
+
2

1
2
3
4
5

<16> GNT#1
<16,21> GNT#2
<16> PIRQD#
<16,19> IRQ14

+3VS
RP19

+3VS

10P8R_8.2K

10K_0402
10K_0402

2
2

C600
.1UF_0402

C601
.1UF_0402

2
R434 1
R435 1

C590
.1UF_0402

+1.8VS

<16,20,21,26> PM_CLKRUN#
<17> ICH_M_SEN#

C588
.1UF_0402
2

C609
22UF_10V_1206

+3VS

R267 1
R262 1

2
2

4.7K_0402
4.7K_0402

<16> ICH_RI#

R291 1

10K_0402

<16> SMB_ALERT#

R289 1

10K_0402

C561
.1UF_0402

C497
.1UF_0402

C530
33PF_0402
2

C509
.1UF_0402
2

C545
.1UF_0402
2

C519
33PF_0402

VCC1.8SUS

+
2

C586
C583
22UF_10V_1206 .1UF_0402

C589
.1UF_0402

C603
.1UF_0402

+3VALW

<12,14,16> SMB_DATA
<12,14,16> SMB_CLK

C550
.1UF_0402

C522
100UF_D2_6.3V

+3VS

+3VALW

<16> SMLINK0
<16> SMLINK1

R283 1
R284 1

2
2

4.7K_0402
4.7K_0402

+RTCVCC
<16> SM_INTRUDER#

1
R263

2
10K_0402

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

ICH3-M Decoupling & Pull-Up


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001
D

Sheet

18

of

41

Q14

+5VS
+12VALW
3

HDD Connector

+5VSHDD

SI2301DS
1

R237

PDD[0..15]

<17> PDD[0..15]

SI2301DS: P CHANNEL
VGS: -4.5V, RDS: 130 mOHM
VGS: -2.5V, RDS: 190mOHM
Id(MAX): 2.3A
VGS(MAX): +-8V

100K_0402

# means no-pop for Tang


Note: PT-test must pop these component

G
FDD Connector

Correct HDD pin define ,pls update layout

D 1

10UF_16V_1206

10UF_16V_1206

C444

C100

1UF_25V_0805

C102

<26> WDATA#

.1UF_0402

<26> WGATE#

WDATA#
WGATE#

1000PF_0402

C445

+5VSHDD

<26> STEP#
C451

TRK0#

<26> TRK0#
HH99221-S6-HDDCON

WRPRT#

<26> WRPRT#

RDATA#

<26> RDATA#
<29> FDD_PRES#
<26> HDSEL#
2

R243
1

+3VS

1
R242
1
R241

<17> PDDACK#

PDIORDY

<16,18> IRQ14

4.7K_0402

2
22_0402
2
22_0402

PDDREQ

1
R240
1

HDSEL#

RPDDACK#

C599

#.1UF_0402

C592

#10UF_16V_1206

<26> FDDIR#

C587
#1UF_25V_0805

C584
#.1UF_0402

Layout Note: +5VSHD D trace


width 60 mil

+5VSHDD

PDA2 <17>
PDCS3# <17>

Placec caps. near FDD CONN.


+5VS

470_0402

MTR0#
3MODE#_11
FDDIR#
3MODE#_13
STEP#

<26> MTR0#

PCSEL 1

Placea caps. near HDD


CONN.

DISKCHG#

<26> DISKCHG#

+5V
INDEX
+5V
DRIVE SELECT
+5V
DISK CHANGE
NC
READY
DENSITY OUT
MOTOR ON
NC
DIRECTION
DENSITY 2
STEP
GND / NC
WRITE DATA
GND
WRITE GATE
GND
TRACK 00
NC / GND
WRITE PROTECT
GND
READ DATA
GND
SIDE 1 SELECT

DRV0#

<26> DRV0#

R239

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

INDEX#

<26> INDEX#

C438
.01UF_0402

JP24

2N7002

+5VSHDD

+5VS
R428
150K

Q13
S

PHDD_LED#

2
G

<16> PIDEPWR

PDIORDY
RPDDACK#
RIRQ14

<17> PDA1
<17> PDA0
<17> PDCS1#

PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

PDDREQ

PDDREQ
PDIOW#
PDIOR#
PDIORDY

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

R244
@10K_0402

<17>
<17>
<17>
<17>

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

JP20
<17> PIDERST#

#85201-2605-ACES-FDDCON

RIRQ14
2
@5.6K_0402
C443
2
<26> 3MODE#

33PF_0402

3MODE#

2 3MODE#_11
@0_0402
2 3MODE#_13
#0_0402

1
R366
1
R365

CD-ROM Connector
1
R213
1
R207

<17> SDDACK#
<16,18> IRQ15

SDD[0..15]

SDDREQ

CD_AGND <23>

1
C416

JP16

SHDD_LED#
+5VS

SEC_CSEL

+5VS

+5VS

R79
100K_0402

R238
100K_0402
1

+5VS
+5VS

R206

10UF_16V_1206

C81
2

C366

.1UF_0402 1UF_25V_0805

SDDREQ <17>
SDIOR# <17>

W=80mils

C364

1000PF_0402

RSDDACK#
PDIAG#

C365

+5VS

U26D
2 100K_0402

SDA2 <17>
SDCS3# <17>

+5VS

PHDD_LED#

12

SHDD_LED#

13

C376

C377

C378

C85

14
1

74HCT08
1
C83

+5VS

2
.1UF_0402

C101
2

11

1000PF_0402

.1UF_0402 1UF_25V_0805

.1UF_0402
U26A

10UF_16V_1206

3
DRV0#

ACT_LED#

ACT_LED# <27>

2
7
74HCT08

R197
470_0402

STEP#
MTR0#
RDATA#
DRV0#

SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDDREQ

<17> SDA1
<17> SDA0
<17> SDCS1#

5
4
3
2
1

Placea caps. near CDROM


CONN.

SDIORDY
RIRQ15

6
7
8
9
10
10P8R_1K

<17> SDIOW#
<17> SDIORDY

RP15
WDATA#
WGATE#
HDSEL#
FDDIR#
+5VS

8
7
6
5
8P4R_1K

R76
@10K_0402

1
2
3
4

47PF_0402

SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

INT_CD_R <23>

<17> SIDERST#
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CD-ROM CONN.

DISKCHG#
INDEX#
WRPRT#
TRK0#

2
@5.6K_0402
C399
1
2

2
47PF_0402

1
C413
<23> INT_CD_L

+5VS
RP20

RIRQ15

33PF_0402

2
47PF_0402

1
C411

1
R217

RSDDACK#

<17> SDD[0..15]

2
22_0402
2
22_0402

+3VS

R212

SDIORDY
2
4.7K_0402

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

IDE/FDD/CD-ROM Module
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

19

of

41

+3VASB

+3VALW

L51 @BLM21A601SPT
2
1

C425
L52

#FBM-11-160808-121T
C428
#2.2UF_16V_0805

LAN_100

R236
L54
2
1

#10K_0402

C422
2
M4

2
LAN_DTOEE
(LAN_100LINK)

+3VASB

LAN_DFRMEE
(LAN_10LINK)

S1

G2

D2

6
5
R447
4

F3
G4

R436

VCC
NC
NC/ORG
GND

CS
SK
DI
DO

D2

5
R437
4

AT93C66 P in6 (ORG)


1=16 bit ; 0=8 bit

Place closely to Lan chips

2 #10K_0402

D9
A9
C8
D8

LAN_EESEL
LAN_EECLK
LAN_DTOEE
LAN_DFRMEE

N6
P6

LAN_TX+
LAN_TX-

10M LINK : Green LED


100M LINK :O range LED
Activity :
Blink(Y ellow LED)

#FLM-160808-68NKT
2
1
L55
1

1 R233

R214

R223

+3VASB

R448 Closel y AT93C86


#61.9_1%_0805

#61.9_1%_0805
R448
LAN_EECLK
(LAN_ACT)

1
#200_0402

R225

CT
TX+
TX-

LAN_RJ45T+
LAN_RJ45R+
LAN_RJ45R-

1
3
4

#56.2_1%_0805

LAN_TX+
LAN_TX-

LAN_CRY1

6
7
8

11
10
9

5
6

R165
#75_1%

10

PR3PR2PR4+
PR4-

R158
#75_1%

#0_0402

R174
1

Place closely to Lan chips

C423
C424
#33PF_0402 #33PF_0402
2

PR3+

#JM36113-L5H7

R178
R177
#75_1% #75_1%

Conn.

Layout Note:
H0022 Pls closely to RJ45

8
1

#.1UF_0402

XTAL
L2
P8
P13

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

C298

C253

#3C920-V3
1

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

P5 VSSTX1
M6 VSSTX2

D2 VSSIO1
J2 VSSIO2
A10 VSSIO3
A7
VSSIO4

L5

C407

NC3
NC5
NC6

PCICLK

Y2
#25MHZ

PR2+

TXCT (NC)

LAN_CRY2

WPOUT
GRST#

F1

X25HI

#Pulse-H0022

PR1+

LDE_YELLOW-

CT
TD+
TD-

16
15
14

LED_ORANGE

RX+
RXCT

R228

#56.2_1%_0805
G2

RD+
RDCT

LDE_YELLOW+

1
2
3

SHLD2

L7
C9
B9

LAN_RX+
LAN_RX-

SHLD1

#4.7PF_NPO

Note1

PR1-

14

C412

LAN_100
LAN_10

M5
L6

11

JP10
LAN_RJ45T-

12

LAN_RX+
LAN_RX-

LED_GREEN

N4
P4

H0022

SMBDATA
SMBCLK
SMBCS#

#FDC6320C

8
7
6
5

#AT93C86-10SC2.7

T1
MEDTEST
GLBTEST#
PHYTEST#

G2

#200_0402

U15
REF100
REF10

S1

U17
1
2
3
4

The cap please closely to


RXIP
RXIN

D1

S2

R414

H3
H4
J4
J3
K4
D7
B3
D4
B2

G1

13

TXOP
TXON

PAR
IDSEL
INTA#
RST#
GNT#
REQ#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PME#
CLKRUN#

#1000PF_1206_2KV

DSX630G H:1.2mm +-30ppm


(20PF)
R450 #10K_0402
1
2

CLK_PCI_LAN
R199
@33_0402

+3VASB

1
D28

2 LAN_SOS5#
#RB751V

<29> SOS1#

1
D27

2 LAN_SOS1#
#RB751V

R224 @10K_0402
SOS5# 1
2
R234 @10K_0402
SOS6# 1
2
R232 @10K_0402
SOS7# 1
2

<29> SOS5#

+3VASB

R449 #10K_0402
1
2

Note1:Place this test point in theRAM door area

+3VASB

<28> LAN_DISABLE#
C367
@10PF_0402

1
D29

2
#RB751V

R208 @0_0402
1
2

@8P4R_10K

R452 #10K_0402
1
2

Compal Electron ics, Inc.

LAN_RST#
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:

1
2

@1000PF_1206_2KV

8
7
6
5

D1

S2

#FDC6320C

C1
D3
E4
E3

2 LAN_AD17

RP10

G1

#200_0402

EESEL
EECLK / ACT
DTOEE / 100LNK
DFRAMEE / 10LNK

LAN_P1

1
2
3
4

#10K_0402

A4
D5
B4
C4
A3
A2

SOS1#
SOS2#
SOS3#
SOS4#

Set 16K EEPROM


R222

SOS1#
SOS2# / TXCLK
SOS3# / TXEN
SOS4# / CRS
SOS5# / RXOE
SOS6# / RXCLK
SOS7# / MDCLK

N10
M14
H14
D14
A13
R198
AD17 1
#100_0402

#10K_0402
ROMCS#
MEMR#
MEMW#
MDIO

VSSPCI1
VSSPCI2
VSSPCI3
VSSPCI4
VSSPCI5

L8

Q36

Set SMBus Mandatory

CBE#0
CBE#1
CBE#2
CBE#3

VSSRX1
VSSRX2
VSSRX3

CLK_PCI_LAN

<14> CLK_PCI_LAN

TXD0 / LA12
TXD1 / LA13
TXD2 / LA14
TXD3 / LA15
COL / LA16

N2
P3
K2

C10
D10

LAN_RST#

#10K_0402
2

+3VASB

#10K_0402

VSSX1
VSSX2
VSSX3
VSSX4
VSSX5
VSSX6
VSSX7
VSSX8
VSSX9

R218
1

FDC6320C
Gate 1: N-MOS
Gate 2: P-MOS

Set Standard features

RXD0 / LA6
RXD1 / LA7
RXD2 / LA8
RXD3 / LA9
RXER / LA10
RXDV / LA11

E2
F2
H2
P1
P7
N8
K14
A8
L1

R226
1
#10K_0402

#10K_0402
2

Q37

3COM
3C920 LAN CONTROLLER

X25L0
A1
C3
G3

C388

VDDLVDET

M1
PME

N5
N7
VDDTX1
VDDTX2

P2
N3
N1
VDDRX1
VDDRX2
VDDRX3

E1
G1
H1
P9
J14
B8
VDDX1
VDDX2
VDDX3
VDDX4
VDDX5
VDDX7

D1
J1
B10
A6
VDDIO1
VDDIO2
VDDIO3
VDDIO4

K1
M2
M7

LA0
LA1
LA2 / POR10
LA3
LA4
LA5

R215
1

B7
C7
B6
D6
C6
C5
A5
B5

LAN_AD17

<16,18> PIRQB#
<8,15,16,21,26,27,28> PCIRST#
<16,18> GNT#3
<16,18> REQ#3
<16,18,21,27> FRAME#
<16,18,21> IRDY#
<16,18,21,27> TRDY#
<16,18,21> DEVSEL#
<16,18,21> STOP#
<16,18,21> PERR#
<16,18,21> SERR#
<29> LAN_PME#
<16,18,21,26> PM_CLKRUN#

G12
M12
L9
N9
M9
L10
J11
H11
G13
H12
F14
G11
F13
M8
M10

R204
#1.91K_1%

#2.2UF_16V_0805

LAN_10
LD0 / POR0
LD1 / POR1
LD2 / POR2
LD3
LD4 / POR4
LD5
LD6 / POR6
LD7

<16,21> PAR

#.01UF_0402

LAN_SOS1# M3
SOS2#
L3
SOS3#
L4
SOS4#
K3
LAN_SOS5# F4
SOS6#
C2
SOS7#
B1

#.01UF_0402 #.01UF_0402

D12
F12
H13
M13

C/BE#0
C/BE#1
C/BE#2
C/BE#3

#FBM-11-160808-121T
C381

U21

C417

#.1UF_0402
LAN_P1

C396

<16,21,27>
<16,21,27>
<16,21,27>
<16,21,27>

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C389

R209
#1.62K_1%

#.01UF_0402

B11
D11
C11
B12
A12
C12
B13
A14
C13
E11
B14
E12
D13
F11
E13
E14
J12
J13
K11
L12
K12
K13
L11
L13
N14
N13
P14
P12
M11
N12
P11
N11

VDDPCI1
VDDPCI2
VDDPCI3
VDDPCI4
VDDPCI5

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

MAINP5
AUX5PN
AUXP

2
<16,21,27> AD[0..31]

P10
L14
C14
A11
G14

#1UF
#.01UF_0402

C356
#2.2UF_16V_0805

+3TX_PWR

+3VASB

2
C419

+3TX_PWR
1

+3RX_PWR

C361

+3VASB

+3VS +3VASB +3VS

R231
#11.5K_1%

#FBM-11-201209-601T
2
1
+3V

#.01UF_0402 #.01UF_0402
2

#.01UF_0402
2

#.01UF_0402
2

#.01UF_0402
2

#.01UF_0402
2

#.01UF_0402
2

#.01UF_0402
2

#.01UF_0402
2

#.01UF_0402
2

#.01UF_0402
2

#.01UF_0402 #.01UF_0402
2

#.01UF_0402

C426

C427

C373

C370

C371

C395

C375

C410

C397

C363

C374

C369

L56
C372

+3RX_PWR

+3RX_PWR

+3VS

+3VASB

3COM 3C920 LAN


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
1

20

of

41

+3VS

+3VS

D7
1

<29> PCM_PME#
AD20

RB751V

1
R195
1
R203

2
0_0402

59
70

2
100_0402

13

<16,18,20,26> PM_CLKRUN#

60
61
64
65
67
68
69

<22,28> V_PRST#

66

<16,18> PIRQA#
1

CLK_PCI_PCM

12

R201
@33_0402

C384

20
28
29
31
32
33
34
35
36
1
2
21

<27> PCM_RI#
<16,18,26> SIRQ
<16,18> PLOCK#

PCM_RI#

C/BE3#
C/BE2#
C/BE1#
C/BE0#

CCBE3#/REG#
CCBE2#/A12
CCBE1#/A8
CCBE0#/CE1#
CRST#/RESET
CFRAME#/A23
CIRDY#/A15
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CPAR/A13
CREQ#/INPACK#
CGNT#/WE#
CCCLK/A16

RI_OUT#/PME#
SUSPEND#

CSTSCHNG/BVD1
CCLKRUN#/WP

IDSEL

CBLOCK#/A19

MF0
MF1
MF2
MF3
MF4
MF5
MF6

CINT#/READY

G_RST#

OZ6912

.1UF_0402

C357

C353
.1UF_0402

C382
.1UF_0402

.1UF_0402

C383

.1UF_0402

C337

.1UF_0402

C338

C345
.1UF_0402
2

63
VCCI

138
122
102
86
50
30
14
VCC
VCC
VCC
VCC
VCCP
VCCP
VCC

126
90
VCCCB
VCCCB

44
18
VCCP
VCCP

PQFP 144
22.2 X
22.2 X
1.60

PCIRST#
PCIFRAME#
PCIIRDY#
PCITRDY#
PCIDEVSEL#
PCISTOP#
PCIPERR#
PCISERR#
PCIPAR
PCIREQ#
PCIGNT#
PCIPCLK

@22PF_0402
2

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

SPKROUT
CAUDIO#/BVD2
84 RSVD/D14
100 RSVD/A18
143 RSVD/D2

PCIRST#

<8,15,16,20,26,27,28> PCIRST#
<16,18,20,27> FRAME#
<16,18,20> IRDY#
<16,18,20,27> TRDY#
<16,18,20> DEVSEL#
<16,18,20> STOP#
<16,18,20> PERR#
<16,18,20> SERR#
<16,20> PAR
1
2
<16,18> REQ#2
R192 10K_0402
<16,18> GNT#2
<14> CLK_PCI_PCM

<28> PCM_SUSP#

12
27
37
48

C/BE#3
C/BE#2
C/BE#1
C/BE#0

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

VPPD1
VPPD0

74
73

3
4
5
7
8
9
10
11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57

72
71

VCCD1#
VCCD0#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
<16,20,27>
<16,20,27>
<16,20,27>
<16,20,27>

.1UF_0402

VPPD0
VPPD1
VCCD0#
VCCD1#

GND
GND
GND
GND
GND
GND
GND
GND

<22>
<22>
<22>
<22>

6
22
42
58
78
94
114
130

S1_D[0..15] <22>

AD[0..31]

<16,20,27> AD[0..31]

C340

.1UF_0402
+3VALW
+3VS

S1_D[0..15]

C339

S1_A[0..25] <22>

.1UF_0402

C351

C348

.1UF_0402

C359
4.7UF_10V_0805
S1_A[0..25]

S1_VCC

+3VS

CCD2#/CD2#
CCD1#/CD1#
CVS2/VS2#
CVS1/VS1#

U18

144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

125
112
99
88

S1_REG#
S1_A12
S1_A8
S1_CE1#

119
111
110
109
107
105
104
133
101
123
106
108
135
136

S1_RST
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#
1
2
R186
33_0402
S1_BVD1
S1_WP

103

S1_A19

132

S1_RDY#

62
134

PCM_SPK#
S1_BVD2

137
75
117
131

S1_CD2#
S1_CD1#
S1_VS2
S1_VS1

S1_IOWR# <22>
S1_IORD# <22>
S1_OE# <22>
S1_CE2# <22>

S1_REG# <22>
S1_CE1# <22>
S1_RST <22>

S1_WAIT# <22>
S1_INPACK# <22>
S1_WE# <22>

S1_A16

S1_BVD1 <22>
S1_WP <22>

S1_RDY# <22>
PCM_SPK# <24>
S1_BVD2 <22>
S1_CD2# <22>
S1_CD1# <22>
S1_VS2 <22>
S1_VS1 <22>

S1_D2
S1_A18
S1_D14

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC.
D CONTAINS
AN
CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF MPETENT
THE CO DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE
RMATION
INFO CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OFALCOMP
ELECTRONICS,INC.
Date:
A

Compal Electronics, Ltd.


PCMCIA controller OZ6912
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

21

of

41

PCMCIA Power Controller

+12VALW

S1_VCC

13
12
11

VCC
VCC
VCC

.1UF_0402
12V

C404
4.7UF_10V_0805

C414

U22
TPS2211

S1_VPP

+5VALW

5
6

.1UF_0402

.1UF_0402

5V
5V
1
2
15
14

VCCD0
VCCD1
VPPD0
VPPD1

GND

3.3V
3.3V

.1UF_0402

VCCD0# <21>
VCCD1# <21>
VPPD0 <21>
VPPD1 <21>

OC

V_PRST#

V_PRST# <21,28>

S1_A[0..25]
S1_D[0..15]

<21> S1_A[0..25]
<21> S1_D[0..15]

16

3
4
2

SHDN

+3VALW

C431

C406

10

VPP
C432

CardBus Socket
1

C324
2

JP11
1000PF_0402

<21> S1_CE1#

S1_VPP

C435

C405

<21> S1_OE#

C355
+ C362

C409
1UF_25V_0805

4.7UF_25V_1206

10UF_10V_1206

.01UF_0402
10UF_10V_1206

S1_VCC

<21> S1_WE#
L50
<21> S1_RDY#
1
2
FBM-11-160808-800LMT

S1_WP

2
22K_0402
2
22K_0402

C350

.1UF_0402

S1_VCC

C346
10UF_10V_1206

1
R181
1
R193

S1_A23

S1_VCCL

S1_VCC

<21> S1_WP

S1_VPP

S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
GND
GND
GND
GND
GND
GND
GND
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
GND
GND
GND
GND
GND
GND
GND
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84

S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_VCCL

S1_CD1# <21>

S1_CE2# <21>
S1_VS1 <21>
S1_IORD# <21>
S1_IOWR# <21>

S1_VPP

S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#

S1_VS2 <21>
S1_RST <21>
S1_WAIT# <21>
S1_INPACK# <21>
S1_REG# <21>
S1_BVD2 <21>
S1_BVD1 <21>

S1_CD2# <21>

S1_VPP

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83

C400
1000PF_0402
2

+5VALW

+3VALW

S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#
S1_VCCL

FOXCONN_1CA415M1-TA_68P

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

CardBus Socket
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

22

of

41

reserve for AC97 coedc us


ing only

2
Q25
@SI2306DS

+5VALW

CNOISE

1
3

ON/OFF#
GND
SI9182DH-AD

VDDA

C577

<27,28,31,32,36> SUSP#

28.7K_1%
10K_1%

ERROR

R383
6

C579

C581
.1UF_0402

4.7UF_10V_0805
2

2
1

.1UF_0402

SENSE

C582
7

@4.7UF_10V_0805

R343

DELAY

VOUT

VIN

C580

R394
2

W=40Mil

R359
@5.1K

2
1
C571 @68PF
1
2 1
2
1
2
R341
@5.11K_0.5%
@442_1% @5.11K_0.5%
R340
1
2 2
1
@0_0402 C548 @220PF
R344

VDDA
U36

2
G

1
@LM358

2
SUSP <31>

2
G
Q30
@2N7002

C560
@.1UF_0402

U34A

C572
@.1UF_0402

@100K_0402
2

8
2
1

2
3

@.1UF_0402
2
C557

R364

D20
@AS2431L

+12VALW

+5VALW

R353
@2.4K

+5VALW

L61
2
1
@BLM21A601SPT

+5VAU

.01UF_0402

C549

@.1UF_0402

AVDD_AC97
L59
VDDA

2
VDDC

FBM-11-201209-121MT

.1UF_0402

.1UF_0402

C500

C484

2
0_0805

+3VS

C501
2

4.7UF_10V_0805

.1UF_0402

.1UF_0402

C512
4.7UF_10V_0805

C473

1
R302
C510

17

1
2

2200PF

2
R276 2
R275

MIC2
PHONE
PC_BEEP

CD_GNA

REFFLT

C486
29
30

1
C498
1
C495

28
27
32

SDATA_OUT
ID0#
ID1#
EAPD#

BPCFG
FLTI
FLTO
NC
NC

S/PDIF_OUT
GND
GND

short the digital ground and ana


long ground

22PF_0402

2
1000PF_0402
2
1000PF_0402

FLT3D

1
45
1 @10K_0402 46
@10K_0402
47

1
2

9
VCC

AFLT2

NC
AGND
AGND

31
33
34
43
44

+ C493

40
26
42

C489

C620

C492
1UF_25V_0805

C506
.1UF_0402

C502
1UF_25V_0805

.1UF_0402

R299
@100K_0402

@4.7U_25V_1206

@1000PF_0402

U30
STAC9700

C494
@1UF_25V_0805
C487
@.047UF

R330
3.3K_0402

AFLT1

VREFOUT

4
7
2

XTL_OUT

SYNC

22PF_0402

24.576 MHz

RESET#

48

<19> CD_AGND

C483
Y3

10

SDATA_IN0 <16>

11

<16,25> IAC_SYNC

2
22_0402
2
47_0402

<16,25> AC97_RST#

1
R295
1
R296

@4.7UF_10V_0805

1
2
R272
@100K_0402
2
@1000PF_0402
C496
@15PF_0402
IAC_BITCLK <16,25>

MIC1

2
13
1UF_25V_0805
2
12
1UF_25V_0805

<16,25> IAC_SDATAO
C619

XTL_IN

C450

1
C474

CD_GNA

2 .1UF_0402 22

2700PF

CD_R

2
@1000PF_0402
2
@1000PF_0402

C516

SDATA_IN

1
C472
1
C471

@.1UF_0402

MD_MIC <25>

R309
4.7K_0402

1
C526
1
C507

BIT_CLK
CD_L

41

C480
2 @1UF_25V_0805

<24> MONO_IN

C618
MDSPK

<25> MD_SPK
MONO_IN
1
R310
47K_0402

<24> MICIN

LIN_IN_R

39

C449

RIGHT <24>

<19> INT_CD_R

1
C527
CD_R_R
1
C529
CD_GNA 1
C528

HP_OUT_R

MDMIC

2
18
1UF_25V_0805
2
20
1UF_25V_0805
2
19
2.2UF_16V_0805
21

1
6.8K_1%
1
6.8K_1%
1
6.8K_1%
1
6.8K_1%
1
@1K_0402
1
1K_0402

HP_OUT_L

LIN_IN_L

37

LEFT <24>

CD_L_R

24
2
R327
2
R328
2
R345
2
R326
2
R320
2
R321
2

<19> INT_CD_L

MONO_OUT

VIDEO_R

LINER

23

LINEL

36

VIDEO_L

1
.1UF_0402

LINE_OUT_R

35

AUX_R

16

LINE_OUT_L

C515

VCC

38

AUX_L

15

C467
1 1000PF_0402
C478
2 1000PF_0402

14

AVCC

AVCC

25

VDDA

R322
3.3K_0402

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.

AC97 CODEC
Document Number

Rev
2

ADY11 LA-1181

Date:

Friday, November 16, 2001


G

Sheet

23
H

of

41

Speaker Connector
L57
1
2
BLM21A05_0805
L58
1
2
@BLM21A05_0805

+5VAMP

JP19

+5VALW

INTSPK_R+
INTSPK_RINTSPK_L+
INTSPK_L-

VDDA

10 mils trace

C464
4.7UF_10V_0805

C462
.1UF_0402

U27

1
2
3
4
Speaker Conn.

LVDD
RVDD

7
18

.1UF_0402

C463

W=40mils

1
2
3
4

<28> MUTE

INTSPK_L-

OP_SHUT

1
.1UF_0402

100K_0402
C626

10UF_10V_1206
2

LHPIN
LOUT-

MICSEL

HO/LINE#
SE/BTL#
SHUTDW
MUTEIN

NC
NC
NC

SEL

MIC_IN

<23> MICIN

OUT

EXTRMIC

INT_MIC+

MIC-

MIC+

C175

7
1

.1UF_0402
1

C531
2

3
6
2
1

EXT_MIC

C226

INT_MIC- <30>
VDDA
R350
2K_0402

@1K_0402
R337
2K_0402

@.22UF_0805
R247
1K_0402
R338
1K_0402

2
2K_0402

1
R329
100K_0402
1

C533
2

1UF_25V_0805

GND

@.1UF_0402

TC7SH14
2

VDDA
1

C525
2

MONO_IN

MONO_IN <23>

+3V POWER
<21> PCM_SPK#

R339

2K_0402

C546
2

1UF_25V_0805

R269
100K

2
3 Q21
2SC2411EK

1UF_25V_0805

R331

3
6
2
1
JA6333L-100

C128
47PF_0402

1UF_25V_0805
R315

C121
47PF_0402

D16
1SS355
2

@10K_0402
4

PL

C536
2

2K_0402

4
PR

JP7
5

NBA_PLUG
47PF_0402
C448
220UF_10V_D
1
2 PR_RIGHT
1
2
L43 FBM-11-160808-121T
INTSPK_L+ 1
2 PR_LEFT
1
2
L44
FBM-11-160808-121T
C447
220UF_10V_D

INTSPK_R+

<17> ICH_SPKR

LINE OUT

C124
2
1

VCC

C562
.1UF_0402

R356
100K_0402
C553
1
2

R348

INT_MIC+ <30>

.22UF_0805

+5V POWER
74HCT08

C452

2
10K_0402
1

R360

C556
2

.1UF_0402
2

4
6

NC

2
3

VDDA

U35
1

C552
1UF_25V_0805

C537
1
2

1UF_25V_0805

+3VS

U26B
<29> BEEP

2K_0402
+5VS

C558
1UF_25V_0805

R349
1K_0402

R246
VDDA
+3VS

R357
100K_0402

JA6333L-100

47PF_0402

C538
2

.22UF_0805

C461
R312

BIAS

47PF_0402
1

C459
4.7UF_10V_0805

L46 1
2
FBM-11-160808-121T
EXTMIC 1
2
FBM-11-160808-121T
.22UF_0805
L47
C446
1
2

CMAMP110
OPBPASS

19

TPA0202

24
13
12
1

VBIAS

BIAS

INT_MIC-

.22UF_0805

GND/HS
GND/HS
GND/HS
GND/HS

RBYPASS

JP8
5

MICSEL

U32

EXT_MIC

R317

C520
1
2

2
17
23

0
LBYPASS

EXT. MI C

1
47PF_0402

RHPIN
MUTEOUT

INTSPK_L+

10

C633
2

R351

C542

14
8
11

LOUT+

49.9

NBA_PLUG
OP_SHUT

INTSPK_R-

20

15

R567
AVDD_AC97

RLINEIN
ROUT-

INTSPK_R+

21

22

ROUT+

16

LLINEIN

RIGHT 1
C456

VDDA

AVDD_MIC
4

LEFT
1
C457

2
R251
2
R250
2
R252
2
R253
2
R256
2
R255
2
R258
2
R259

VSUP

RIGHT 1
C453

<23> RIGHT

1
150K
1
50K
1
150K
2
1
.01UF_0402
50K
INTSPK_L+
1
100K
2
1
1UF_25V_0805 75K
INTSPK_R+
1
100K
2
1
1UF_25V_0805 75K
2
.01UF_0402
INTSPK_R+

GND

INTSPK_L+

LEFT
1
C454

<23> LEFT

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

AMP & Audio Jack


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

24

of

41

C393

+3V

C386

+5VMDC

1
R200

2
@0_0805

+5V

@.1UF_0402

@.1UF_0402
JP22
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

<23> MD_MIC

+3VMDC
D

2
0_0805
2
@0_0805
C630

C379
.1UF_0402

+3VALW

1
R190
1
R191

+3V

+3VMDC
1

4.7UF_16V_A
<16,23> IAC_SDATAO
<16,23> AC97_RST#

MDC Note
Pin 1 is NC for Pctel and connexant MDC modem

C380

C394
@1000PF_0402

@1000PF_0402

Pin 2 is NC for Pctel and connexant MDC modem

MONO_OUT/PC_BEEP AUDIO_PWDN
MONO_PHONE
AGND
RESERVED
AUXA_RIGHT
GND
AUXA_LEFT
+5V
CD_GND
RESERVED
CD_RIGHT
RESERVED
CD_LEFT
RESERVED
GND
RESERVED
3.3Vaux
RESERVED
GND
AC97_SYNC
3.3Vmain
AC97_SDATA_OUT AC97_SDATA_IN1
AC97_SDATA_IN0
AC97_RESET#
GND
GND
AC97_BITCLK
AC97_MSTRCLK

MDC_DN# <28>

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

MD_SPK <23>

1
2
R216 10K_0402
2
2

R221 1
@22_0402
R220 1
22_0402

+3V

1: Have primary CODEC on mot


her board
IAC_SYNC <16,23>
SDATA_IN1 <16>
IAC_BITCLK <16,23>

AMP-108-5424

MDC Conn.

Spare Logic Gate

Screw Hole
H1
C315D126

H7
C315D126

H22
C315D118

H13
O193X134D193X134N

H12
S315D118

+12VALW

FD1

FD3

1
FIDUCIAL MARK

H17
C134D134N

FIDUCIAL MARK

H24
C354D244

H15
H16
O217X106D177X67O217X106D177X67

FIDUCIAL MARK

FIDUCIAL MARK

CF3

CF1

SMDC40M80

SMDC40M80

CF4
H23
C354D244

FIDUCIAL MARK

H8
C315D157

H11
C256D157

H10
C256D157

FD5

1
H3
C315D157

FD4

FIDUCIAL MARK

FD6
H4
C315D157

FD2

H2
C315D126

CF14
1

U34B
7
@LM358

SMDC40M80

CF6
1

SMDC40M80

CF2
1

SMDC40M80

CF10
1

SMDC40M80

CF18
1

SMDC40M80

CF13
1

SMDC40M80

H6
C315D126

Fiduial Mark

CF15
1

SMDC40M80

SMDC40M80

CF12
1
SMDC40M80
H19
H25
O106X217D67X177O106X217D67X177

H27
C315D110

M9
S276D110

M2
S394D138

CF7
1
SMDC40M80

CF11
1
SMDC40M80

CF17
1
SMDC40M80

CF16
1
SMDC40M80

CF8
1

U38C

12

U38D
11

74LVC125

74LVC125

M11
SMDC200M157

M10
S315D244

M1
M6
C315D118 C315D118

H18
H14
H9
H5
S315D118 S315D118 R256X315D138 C315D118

M3
S315D118

H26
O75X213D40X177

H20
H21
O75X213D40X177 O75X213D40X177

13

10

SMDC40M80

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
5

MDC connector / Skew Hole


Document Number

Rev
2

ADY11 LA-1181
Thursday, November 22, 2001

Sheet
1

25

of

41

14

+3VALW

14

+3VALW

<8,15,16,20,21,27,28> PCIRST#

1
R429

2
10K_0402

LPC_RST#

6
U40C
74LVC14
7

C624

+3VS

5
1

U40D
74LVC14

+3VS

.01UF_0402
1

<16> LFRAME#
<16> LDRQ#0

<16> SUS_STAT#
<16,18,20,21> PM_CLKRUN#
<16,18,21> SIRQ
<16,28> EC_SMI#
CLK_14M_SIO

2
1

<19> DISKCHG#
<19> HDSEL#
<19> RDATA#
<19> WRPRT#
<19> TRK0#
<19> WGATE#
<19> WDATA#
<19> STEP#
<19> FDDIR#
<19> DRV0#
<19> MTR0#
<19> INDEX#
<19> 3MODE#

R325
@33_0402

R324
10_0402

<14> CLK_14M_SIO
+3VS

CLK_PCI_SIO

C543

@15PF_0402

5PF_0402

C544

8
9
12
11
7
6
SIRQ
10
1
2 LPCSMI# 19
R342
@0_0402
CLK_14M_SIO
20
1
2
R334
@10K_0402
DISKCHG#
21
HDSEL#
22
RDATA#
23
WRPRT#
24
TRK0#
25
WGATE#
26
WDATA#
27
STEP#
28
FDDIR#
29
DRV0#
30
MTR0#
31
INDEX#
32
3MODE#
33
34

5
6
7
8

+3VS

CLK_PCI_SIO
LPC_RST#
LFRAME#
LDRQ#0

4
3
2
1

RP11
8P4R_10K

<28> XA0
<28> XA1
<28> XA2
<28> XA3
<28> XSTB0#

<28> IRQ1

XA0
XA1
XA2
XA3
XSTB0#
XCNF2

IRQ8

<28> IRQ11
<28> IRQ12

XIOR#
XIOW#
XA12
XA13
XA14
XA15
XA16
XA17
XA18

PC87393

CLKIN
DSKCHG#
HDSEL#
RDATA#
WP#
TRK0#
WGATE#
WDATA#
SETP#
DIR#
DR0#
MTR0#
INDEX#
DENSEL
DRATE0/IRSL2

IRTX
IRRX1
IRRX2_IRSL0
XA0/GPIO20
IRSL1
XA1/GPIO21
IRSL3/PWUREQ#
XA2/GPIO22
XA3/GPIO23
XA4/GPIO24/XSTB0#
XA5/XSTB1#/XCNF2
XD0/GPIO00/JOYABTN1
XA6/GPIO26/PRIQA/XSTB2#
XD1/GPIO01/JOYBBTN1
XA7/GPIO27/PIRQB
XD2/GPIO02/JOYAY
XA8/GPIO30/PIRQC
XD3/GPIO03/JOYBY
XA9/GPIO31/MTR1#/PIRQD
XD4/GPIO04/JOYBX
XA10/GPIO32/XIORD#/MDRX
XD5/GPIO05/JOYAX
XA11/GPIO33/XIOWR#/MDTX
XD6/GPIO06/JOYBBTN0
XA12/GPIO10/JOYABTN1/RI2#
XD7/GPIO07/JOYABTN0
XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2
XA14/GPIO12/JOYAY/CTS2#
XWR#/XCNF1
XA15/GPIO13/JOYBY/SOUT2
XRD#/GPIO34/WDO#
XA16/GPIO14/JOYBX/RTS2#
XIOWR#/XCS1#/MTR1#/DRATE0
XA17/GPIO15/JOYAX/SIN2
XIORD#/GPIO37/IRSL2/DR1#
XA18/GPIO16/JOYBBTN0/DSR2#
XCS0#/DR1#/XDRY/GPIO25
XA19/DCD2#/JOYABTN0/GPIO17

Pin #

Description

BADDR

61

BASE Address Selection

52
50
48
46
45
44
43
42

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

35
36
37
40
41
47
49
51
53
54

LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTSLCTIN#
LPTINIT#
LPTERR#
LPTAFD#
LPTSTB#

55
56
57
58
59
60
61
62

DCDA#
DSRA#
RXDA
RTSA#
TXDA
CTSA#
DTRA#
RIA#

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>

LPTSLCT <27>
LPTPE <27>
LPTBUSY <27>
LPTACK# <27>
LPTSLCTIN# <27>
LPTINIT# <27>
LPTERR# <27>
LPTAFD# <27>
LPTSTB# <27>
DCDA# <27>
DSRA# <27>
RXDA <27>
RTSA# <27>
TXDA <27>
CTSA# <27>
DTRA# <27>
RIA# <27>

$ means no-pop for

70
69
68
67
66
3
2
1
100
99
98
97
96

XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7

4
5
73
71
72

XMEMW#
XMEMR#

XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7

R565
10K_0402
BOARD_ID

XMEMW# <28>
XMEMR# <28>

BOARD_ID
XIOCHRDY

XIOCHRDY

TANGBTO

+3VS

<28>
<28>
<28>
<28>
<28>
<28>
<28>
<28>

R566
$0_0402

<28>

2
10K_0402

1
R274 +3VS

BOARD_ID = HIGH -------> TANGBTO


BOARD_ID = LOW --------> TANG

13
38
64
89

PC87393F

Signal

PNF/XRDY
SLCT/WGATE#
PE/WDATA#
BUSY_WAIT#/MTR1#
ACK#/DR1#
SLIN#_ASTRB#/STEP#
INIT#/DIR#
ERR#/HDSEL#
AFD#_DSTRB#/DENSEL
STB#_WRITE#
DCD1#
DSR1#
SIN1
RTS1#/TEST
SOUT1/XCNF0
CTS1#
DTR1#_BOUT1/BADDR
RI1#

VSS
VSS
VSS
VSS

<28> XIOR#
<28> XIOW#
<28> XA12
<28> XA13
<28> XA14
<28> XA15
<28> XA16
<28> XA17
<28> XA18

95
94
93
92
91
90
87
86
85
84
83
82
81
80
79
78
77
76
75
74

LCLK
LRESET#
LFRAME#
LDRQ#
LPCPD#
CLKRUN#/GPIO36
SERIRQ
SMI#/GPIO35

PD0/INDEX#
PD1/TRK0#
PD2/WP#
PD3/RDATA#
PD4/DSKCHG#
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1

<14> CLK_PCI_SIO

LAD0
LAD1
LAD2
LAD3

1
R332
4.7K_0402

LAD0
LAD1
LAD2
LAD3

15
16
17
18

<16>
<16>
<16>
<16>

+3VS

U33

2
10K_0402

LAD0
LAD1
LAD2
LAD3

1
R333

14
39
63
88

4.7UF_10V_0805

1000PF_0402

+3VS

C481

VDD
VDD
VDD
VDD

C511

.1UF_0402

.1UF_0402

C535

C505

"0": 2E~2F (Default)


"1": 4E~4F
TEST

58

BADDR PULL-UP :4E


BADDR PULL-DOWN:2E
(DEFAULT)

+3VS

"0": Normal (Default)

+3VS

"1": Test Mode


XCNF[2:0]

90, 4, 59

(default)

TXDA
XCNF0

1
R279

2
@10K_0402

Function

No BIOS

XMEMW#
XCNF1

1
R323

2
10K_0402

Normal Mode. XRDY dis abled

XCNF2

1
R303

2
@10K_0402

Latch Mode. XA12-19, XRDY enab

led

Latch Mode. GPIO10~17,XRDY enab

led

Latch Mode. XA12-19, XRDY disab

led

Latch Mode. GPIO10~17,XRDY disab

* 1 ROM SOLUTION

DTRA#

1
R278

2
@10K_0402

Pin # 61

XBUS RESET CONFIGU


RATION

BASE ADDRESS CONFIG


URATION

led

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

LPC Super I/O NS PC87393


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

26

of

41

1
3
5
7
9
11
13
15
17
19

+5VS
ACT_LED#
CHARGE_LED#

<19> ACT_LED#
<29> CHARGE_LED#
1

+3VALW

2
4
6
8
10
12
14
16
18
20

TP_DATA <28>

+5VS

+5V_PRN

10P8R_2.7K

+5VALW
PWR_LED# <29>
BATT_LED# <29>

PWR_LED#
BATT_LED#

FD7
FD6
FD5
FD4

AFD/3M#
ERR#
PRNINIT#
SLCTIN#

1
2
3
4

ACK#
BUSY
PE
SLCT

8P4C_270PF
CP12
1
8
2
7
3
6
4
5

+5V_PRN
RP1

LID_SW# <29,30>

JST BM20B-SRDS-G

SLCTIN#
PRNINIT#
ERR#
AFD/3M#
+5V_PRN

8
7
6
5

C108

10
9
8
7
6

ACK#
BUSY
PE
SLCT

D6

.1UF_0402

1w=10mils

+5VS

1SS355

LPTSTB#

<26> LPTSTB#

1
2
3
4

FD4
FD5
FD6
FD7

1
2
3
4

8
7
6
5

8P4C_270PF

<26> LPTAFD#

LPD0

<26> LPTERR#

LPD1

<26> LPTINIT#

CP13

@220PF
C97
1
2 TP_DATA

8
7
6
5

LPD2

<26> LPTSLCTIN#

LPD3

L39
L7
L38
L6
L8
L37
L36
L35

LPD4

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

L34
@220PF
CP11

LPD5

8P4C_270PF

LPD6

PWR_LED#
ACT_LED#
BATT_LED#
CHARGE_LED#

LPD7

@8P4C_220PF

PS2 CONN.

L12

<26> LPTBUSY

L1

<26> LPTPE

L2

FD5
FD6
FD7

ACK#

BUSY

2
0

PE

2
0

1
L3

FD4

0
1

<26> LPTSLCT

1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

AFD/3M#
FD0
ERR#
FD1
PRNINIT#
FD2
SLCTIN#
FD3

0
1

<26> LPTACK#

L11

LPD[0..7]

SLCT

2
47PF_0402

L10
<26> LPD[0..7]

0
0
0
0
0
0
0
0

PWRPRN 1

L9
4
3
2
1

C111
2

CP4
FD0
FD1
FD2
FD3

2 TP_CLK

5
6
7
8

R100
2.7K_0402

R99
33_0402

10P8R_2.7K
C96
1

+5V_PRN

4.7UF_10V_0805

8P4C_270PF

1
2
3
4
5

Parallel Port
C107

<28> TP_CLK

TP_DATA

10
9
8
7
6

JP15
TP_CLK

1
2
3
4
5

w=10mils

RP2
FD0
FD1
FD2
FD3

+5V_PRN

Touch Pad & Status LED Conn.

CP3

+5V_PRN

JP1
LPTCN-25-SUYIN

U4
2

PS2_DATA

<28> PS2_DATA

1
2
3

PS2_CLK

<28> PS2_CLK

DATA IN
GND
CLK IN

DATA OUT
VCC
CLK OUT

6
5
4

KBMF01SC6

PS2KB_VCC

+5VS

KB_AS
JP6

W=40mils

W=40mils

L41
FBM-11-451616-800T

6
4
2
1
5
3
KBD/PS2_6

C114
1UF_25V_0805

POLYSWITCH_1.1A
4516

F1

S/W debug only

33005A-06T1-01-PS2
I16795326
U3
KBD_DATA

<28> KBD_DATA

1
2
3

KBD_CLK

<28> KBD_CLK

DATA IN
GND
CLK IN

DATA OUT
VCC
CLK OUT

6
5
4
JP3

KBMF01SC6

<26> DCDA#
<26> TXDA
<26> RTSA#
<26> RIA#
<23,28,31,32,36> SUSP#

+5VS

DCDA#
TXDA

1
3
5
7
9
11

2
+ +
4
+ + 6
+ +
8
+ + 10
+ +
12
+ +
@E&T 2041-012-12

RTSA#
RIA#
SUSP#

RXDA
DTRA#
DSRA#
CTSA#
RIA0

<26>
RXDA <26>
DTRA#
<26>
DSRA#
CTSA# <26>

ACPI Debug port

+5VALW
3

JP23
<16,20,21> AD9
<16,18,20,21> FRAME#

TRDY# <16,18,20,21>
PCIRST# <8,15,16,20,21,26,28>
CLK_PCI_LPC <14>
C/BE#3 <16,20,21>
C/BE#1 <16,20,21>
AD7 <16,20,21>
AD3 <16,20,21>
AD0 <16,20,21>
AD4 <16,20,21>
C/BE#0 <16,20,21>

<16,20,21> C/BE#2
<16,20,21> AD8
<16,20,21> AD5
<16,20,21> AD1
<16,20,21> AD2
<16,20,21> AD6

+5VALW

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
@AMP 5-175638-0

R374
20K_0402
2

from cardbus
D22

PORT

CLK_PCI_LPC

<21> PCM_RI#

Debug

RING# <28>

RB751V

R564
@33_0402

C842
@10PF_0402
4

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

PIO/SIO/PS2 Port/T_P Conn. & LPC Debug Conn.


Document Number

Rev
2

ADY11 LA-1181
Monday, November 19, 2001

Sheet
E

27

of

41

+5VALW

L62

+5VALW

Q22 3
2N7002

HMEMR#
HMEMW#

1
G

<26> XMEMR#

Q23 3
2N7002

+5VALW

156
155
154
153

<26> IRQ1

<26> XMEMW#

2
1K_0402

<26> IRQ11
<26> IRQ12
2
1
R361 10K_0402

2 R292

<7> EC_HPOWON
<7> EN_DFAN
<34> IREF
<25> MDC_DN#
<15> DAC_BRIG

IREF: Charger current control


ADPREF: Adapter current
control
VBATT

1
C551

ECAGND
2
.01UF_0402

BATT_CHGI

1
C555

ECAGND
2
.01UF_0402

VBATT

<16> SLP_S5#
<16> SLP_S3#
<14,16> SLP_S1#

BATT-OVP

BATT_CHGI

LI/MH#

ECAGND
1
2
C547 .01UF_0402

BATT_TEMP

<33> BATT_TEMP

ECAGND
1
2
C540 .01UF_0402

79
164
165

2 R260
1
@0_0402

<34> BATT-OVP

BATT_TEMP

PFAIL#
1 51RST
10K_0402

<30> SCRLED#
<30> NUMLED#
<30> CAPSLED#
<15> CRT_ON#
<23,27,31,32,36> SUSP#

2 R293
0

95
96
97
98
81
82
83
84
85
86
93
94
61
62
63
64
65
68

G20
RCL#

<30> ON/OFF

SMB_EC_DA1
SMB_EC_CK1

+RTCVCC

+3VS

C466
1UF_25V_0805
28
2

2
2

CRY1

R314
10K_0402

1
R347
10K_0402

R271
22M
X1

RB751V
D17

32.768KHZ

PD0/AD0
PD1/AD1
PD2/AD2
PD3/AD3
PD4/AD4
PD5/AD5
PD6/AD6
PD7/AD7
PC0
PC1
PC2
PC3/EXINT0
PC4/EXINT11
PC5/EXINT15
PB0/RING#
PB1/SCL
PB2/SDA
PB3/TA
PB4/TB/EXINT10
PB5/GA20
PB6/HRSTO#
PB7/SWIN
VBAT
32KX1/32CLKIN
32KX2

1
51K_0402

C470

PC87570C4-176PIN

92

EC_SMI# <16,26>

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15
PSDAT1
PSCLK1
PSDAT2
PSCLK2
PSDAT3/PC7
PSCLK3/PC6
PG4/WR1#
PG3/SEL1#
PG2/CLK
PG0/SELIO

KBA18

+5VALW
1

RB751V

R188
0_0402
2

FRD#
FWR#
FSEL#

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

+5VBIOS

VCC

111
112
105

22
24
31

VPP

13
14
15
17
18
19
20
21

+ C342

32

C341

10UF_10V_1206

CE#
OE#
WE#

GND

.1UF_0402
1

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

D0
D1
D2
D3
D4
D5
D6
D7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17

137
138
139
140
141
142
143
144

12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30

AGND

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18

16

+5VALW
2

36
35
34
33
32
31
30
29

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

56
55
54
53
52
51
50
49
48
47
42
41
40
39
38
37

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

57
58
59
60
69
70

KBD_DATA
KBD_CLK
PS2_DATA
PS2_CLK
TP_DATA
TP_CLK

113
106
107
110

EC_THRM#
G_RST#

R406

+5VALW

R410
100K_0402
14
1

FWE#

+5VS
+5VALW

100K_0402
RP17

FWR#

2
7

EC_FLASH# <17>

PH0/BST0/ENV0
PH1/BST1/ENV1
PH2/BST2/TRIS
PH3/PFS
PH4/PLI
PH5/ISE#
D8/PF0
D9/PF1
D10/PF2
D11/PF3
D12/PF4
D13/PF5
D14/PF6
D15/PF7

104
103
102
101
100
99

74HCT32

145
146
147
148
149
150
151
152

8
7
6
5
8P4R_10K

RP12
+5VS
PS2_DATA
PS2_CLK

10
9
8
7
6

1
2
3
4
5

KBD_DATA
KBD_CLK
TP_DATA
TP_CLK
+5VS

10P8R_10K

RP16
FSEL#
KBA18
KBA15
KBA17

KBD_DATA <27>
KBD_CLK <27>
PS2_DATA <27>
PS2_CLK <27>
TP_DATA <27>
TP_CLK <27>

8
7
6
5

+5VALW

EC_THRM# <16>
G_RST#
LAN_DISABLE# <20>
SELIO# <29>

KSO17 <30>
ACOFF <34>

1
2
3
4

8P4R_10K

+3VALW
R372
100K

PCM_SUSP# <21>
ACOFF
570_SMI#
EC_ON

1
2
3
4

FRD#
SELIO#
BKOFF#

Q33
2N7002

G_RST#

V_PRST# <21,22>

1
7SH32

EC_ON <30>
SCI# <16>

TRICKLE
VTT_PWRGD# <5,14>
VR_ON <31,32>
FSTCHG <34>
MUTE <24>
SYSON <31,33>
ACIN <17,33,35>
BKOFF# <15>

U31

<8,15,16,20,21,26,27> PCIRST#

R297 2
@0_0402
ADB[0..7]

RP18
570_SMI#
PCM_SUSP#
KSO17

1
2
3
4

8
7
6
5

ADB[0..7] <29>

KBA[0..18]

KBA[0..18] <29>

KSI[0..7]

KSI[0..7] <29,30>

KSO[0..15]
8P4R_10K

KSO[0..15] <29>
4

33PF_0402

RB751V

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:

10PF_0402
1 RCL#

<16> KBRST#

1
1

C468

91
80

PFAIL#
HMR
HPWRON

R270
2

1 G20

25
27

AVCC
VREF

161
108
67
23
VCC
VCC
VCC
VCC

IRQ1
IRQ8#
IRQ11
IRQ12

DA0
DA1
DA2
DA3

114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
135
136

U45A
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

CRY2

D15
<16> GATEA20

71
72
73
74
75
76
77
78

RD/HDEN
WR0#
HRMS/SEL0#

GND
GND
GND
GND
GND

R313
4.7K_0402

R316
4.7K_0402

SMB_EC_CK1
SMB_EC_DA1

D0
D1
D2
D3
D4
D5
D6
D7

HAEN
HIOCHRDY
HIOR#
HIOW#
HMEMCS#/PA0
HMEMRD#/PA1
HMEMWR#/PA2

+5VALW
<27> RING#
<5,15,29,33> SMB_EC_CK1
<5,15,29,33> SMB_EC_DA1
<15> INVT_PWM
<7> FAN1_TACH

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13/BE0
A14/BE1
A15/PG1/CBRD
A16/PA5/FXBUSEN
A17/PA6
A18/PE1/SHBM#

<26> XIOCHRDY
<26> XIOR#
<26> XIOW#

570_SMI#

13
14
158
159
1
157
R305 162
163

D18

U16
28F040

PC87570

HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7

R301
100K_0402

Pin 130 PU for


Zero Latch

100K_0402

FBM-11-160808-601T

2
G

+5VS

15
16
17
18
19
20
21
22

.1UF_0402

XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7

HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HA11
HA12
HA13
HA14
HA15
PA3/HA16
PA4/HA17
PE0/HA18

R187
10K_0402
2

R407
1

166
167
168
169
170
171
172
173
174
3
4
5
6
7
8
9
10
11
12

2 ECAGND 1

24
26
66
109
160

R307
10K_0402

XA0
XA1
XA2
XA3
XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7
XA12
XA13
XA14
XA15
XA16
XA17
XA18

U29

NC: 1,2,43,44,45,46,87,88,89,90,131,132,133,134,175,17
6

<26> XSTB0#

1000PF_0402

.1UF_0402

<26> XA0
<26> XA1
<26> XA2
<26> XA3
<26> XD0
<26> XD1
<26> XD2
<26> XD3
<26> XD4
<26> XD5
<26> XD6
<26> XD7
<26> XA12
<26> XA13
<26> XA14
<26> XA15
<26> XA16
<26> XA17
<26> XA18

XD[0..7]

<26> XD[0..7]

1000PF_0402

.1UF_0402

L60

C541

C469
1

.1UF_0402
1

+3VALW

C504

KB_VCC

C508

C565

C513

FBM-11-160808-601T

+5VALW

PC87570
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

28

of

41

ADB[0..7]

<28> ADB[0..7]

KBA[0..18]

<28> KBA[0..18]

+5VALW
+5VALW
+3VALW

R371 2
100K_0402
R378 2
100K_0402

+5VALW

R384 2
100K_0402

R390 2
100K_0402

Input Port

Output Port

+5VALW

+5VALW
C578
1
2

C593
2
1

.1UF_0402

1
19

U45C
74HCT32

14
9

KBA1

20
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

C575
1
2

+5VALW

.1UF_0402

U45B
74HCT32

14
4

KBA3

6
SELIO#

5
7

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

3
4
7
8
13
14
17
18

AA
LARST#

11
1

U41
2
5
6
9
12
15
16
19

VCC

18
16
14
12
9
7
5
3

D0
D1
D2
D3
D4
D5
D6
D7
CLK
CLR

74HCT244

+5VALW

CC

8
SELIO#

<28> SELIO#

1G
2G

10

+5VALW

U39
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

1
R385

2
20K_0402

PWR_LED# <27>
CHARGE_LED# <27>
SWI# <16>
LID_OUT# <16>
PWRBTN_OUT# <16>
VLBA# <16>
BATT_LED# <27>
BEEP <24>

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND

20

PCM_PME#

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

74HCT273

10

3/06 01

2
4
6
8
11
13
15
17

2 R380
1
@0_0402

VCC

<33,34> 6C/8C#/4C#
<5> THRM#
<19> FDD_PRES#
<20> LAN_PME#
<27,30> LID_SW#
<21> PCM_PME#
<15> ENABKL
<33>
AIR_ADP#

.1UF_0402

GND

2/29 01

R404 2
100K_0402

+3VALW

C594
1
2
1UF_25V_0805

10
7
+3V
PCM_PME#

+5VALW
RP24

R387

AA
CC
BB
DD

100K_0402

+5VALW

+5VALW

1
2
3
4

8
7
6
5

8P4R_100K
+5VALW

4
3
2
1

4
3
2
1

+5VALW

RP25
@8P4R_100K

RP23
@8P4R_100K

C613
2

KBA2

SELIO#

@.1UF_0402
1
19

DD

1G
2G

10

20
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

+5VALW

KBA4

14
12

U45D
74HCT32
11

SELIO#

13
7

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

3
4
7
8
13
14
17
18

BB
LARST#

11
1

D0
D1
D2
D3
D4
D5
D6
D7
CLK
CLR

@74HCT244

U42
2
5
6
9
12
15
16
19

VCC

18
16
14
12
9
7
5
3

EC_VCHRST# <15>
SOS1# <20>
SOS5# <20>
EC_WAKEUP# <16>

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

74HCT273

10

C614
1

U43
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
GND

+5VALW

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

C612
2

.1UF_0402

GND

20
2
4
6
8
11
13
15
17

VCC

5
6
7
8

5
6
7
8

@.1UF_0402

U44
@7SH32

KSO[0..15]

<28> KSO[0..15]

KSI[0..7]

11

13

15

19

21

17

10

12

14

16

18

20

22

24

Dummy
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

23

KSO0

25

KSI1

KSI6

KSI4

KSI3
KSO1

KSO2

KSO7

KSO6

KSO12

KSO14

KSO10

KSO9

KSO5

KSO4

KSO8

KSO3

KSO13

KSO11

KSO15

KSI7

KSI5

KSI2

KSI0

JP14
INT_KB_CONN.

KSI1
KSI7
KSI6
KSO9

4
3
2
1

5
6
7
8

CP10
8P4C_220PF

KSI4
KSI5
KSO0
KSI2

4
3
2
1

5
6
7
8

CP9
8P4C_220PF

KSI3
KSO5
KSO1
KSI0

4
3
2
1

5
6
7
8

CP8
8P4C_220PF

KSO2
KSO4
KSO7
KSO8

4
3
2
1

5
6
7
8

CP7

KSO6
KSO3
KSO12
KSO13

4
3
2
1

5
6
7
8

CP6

KSO14
KSO11
KSO10
KSO15

4
3
2
1

5
6
7
8

CP5

NM24C164 Address definition: 1 A2 A1# A0 B2 B1 B0 R/W#


+5VALW
+5VALW

INT_KBD CONN.

1
2
C458 .1UF_0402

<5,15,28,33> SMB_EC_CK1
<5,15,28,33> SMB_EC_DA1

8P4C_220PF

R286
100K_0402
U28
8
7
6
5

VCC
WC
SCL
SDA
NM24C16

A0
A1
A2
GND

1
2
3
4

<28,30> KSI[0..7]

EC I2C Bus Address:


8P4C_220PF

24C164: 1011 xxx R/W#


24C16: 101 0xxx R/W#
4

8P4C_220PF

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

EC Extend I/O KB Conn. & BIOS


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

29

of

41

+5VALW

RTC Battery

Power ON Circuit
+3VALW
BATT1

R362
100K_0402

1000PF_0402

CHGRTC

C564

D21

HSM126S

R367
4.7K_0402

+RTCVCC
R401
10K_0402

.1UF_0402

EC_ON# <36>

DAN202U

RLZ20A

U40B
74LVC14

C585

D24

RSMRST# <16>

<28> EC_ON

EC_ON

ON/OFF <28>

2
+5VALW

ON/OFF

RTCBATT

Power BTN

RTCPWR
ON/OFFBTN#

14

U40A

14
1M_0402
1

74LVC14

1
1

D19

R379

+3VALW

+3VALW

R388
150K

1
R358
22K_0402

22K

22K

Q31
DTC124EK
+3V

WHEN R=0,Vbe=1
.35V
WHEN R=33K,Vbe
=0.8V
+3VALW

+3VALW

+3VALW

R377 20K_0402
2

14

11

10

13

Q28
@2N7002

S
3

ITP_PWROK <7,16>

U40F
74LVC14

C570
1UF_0805_X7R

2
G

<31> VR_ON#

12

U40E
74LVC14

+3V

C19
ICH_VGATE <7,16>

.1UF_0402

@74LVC125

C112
150UF_10V_E

C21

USBP0USBP0+

<17> USBP0<17> USBP0+

1000PF_0402
1

R381 @0_0402
1
2

L42 4516
W=40mils
1
2
FBM-11-451616-800T

R386
@10K_0402
U38B

USB Port 0

USB_A

USB_AS

3
74LVC125

14

U38A

<32> VGATE

14

R373
10K_0402

L19
FBM-11-160808-121
1
2
1
2
FBM-11-160808-121
L18

JP5
1
2
3
4

USB0DUSB0D+

VCC
DD+
GND
USB_CONN

+5VS

USB0DUSB0D+

USB Over Current

USB_AS USB_BS +3V

C18
1
1

@150PF_0402
2
2

C17

@150PF_0402

Place close to USB connector.


R105
100K_0402

R106
100K_0402

2
47K_0402

OVCUR#0

1
R107

2
47K_0402
C115

OVCUR#2
C116
2

.1UF_0402
2

.1UF_0402

OVCUR#0 <17>
OVCUR#2 <17>

USB_BS

USB Port 1

USB_B

L40 4516
W=40mils
1
2
FBM-11-451616-800T

Note:

C15

USB_AS=USB_BS=Trace width=40mils

C113
150UF_10V_E

.1UF_0402

LID Switch & Function Button

USBP2USBP2+

<17> USBP2<17> USBP2+

TPS2042

1
R104

C20
1000PF_0402

8
7
6
5

.1UF_0402

OC1#
OUT1
OUT2
OC2#

C117

GND
IN
EN1#
EN2#

U11
1
2
3
4

W=40mils

L21
FBM-11-160808-121
1
2
1
2
FBM-11-160808-121
L20

JP4
1
2
3
4

USB2DUSB2D+

VCC
DD+
GND
USB_CONN

USB2DUSB2D+

JP12
<24> INT_MIC-

<28,29> KSI3
<28,29> KSI1
<28> KSO17
<28> CAPSLED#
<27,29> LID_SW#
+3VALW

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

INT_MIC+ <24>

@150PF_0402
2
2

C13

@150PF_0402

Place close to USB connector.

KSI2 <28,29>
KSI0 <28,29>
SCRLED# <28>
NUMLED# <28>

ON/OFFBTN#

C14
1
1

+5VS

SUYIN 12750AR-16G2T-9

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

Power OK/Reset/RTC battery/USB Conn.& Lid Switch


Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

30

of

41

+12VALW

+12VALW

+5VALW to +5V Transfer


R229
100K_0402

+CPU_CORE

3
VR_ON 2
G

<28,32> VR_ON

2
3
1

@SMO5
D

2
G

Q27
@2N7002

S
3

C440
33UF_D2_16V

Q20

2
1

Q11
2N7002

@330

C442

R179
Q24
@2N7002

12

Q3
2N7002
S

2
G
S

2 SYSON#
G

1
VR_ON#

<30> VR_ON#

2
G

<28,33> SYSON

.1UF_0402

+5VALW

SYSON#

R227
470_0402
1

10UF_10V_1206

C439

+VTT

@330

1
1

C441

+5VALW

R140

R368
@100K_0402

1M_0402
2

.01UF_0402

1
2
3
4

S
S
S
G

R230

D
D
D
D
SI4800
SUSON

1
1

8
7
6
5

C418

2
G
Q12
2N7002

+5V
U23

SYSON#
1

R77
47K_0402

+3VALW
+5VALW

Q29
@2N7002

+12VALW

4.7UF_16V_A

R382
10K_0402

1.8VALW/+1.5VS

Power

direct prov

ide

<23> SUSP

+3VALW

+3VALW to +3V Transfer


+3V

3
1
1

S
S
S
G

C305

22UF_10V_1206
2

SI4800

C317

C301
.1UF_0402

10UF_10V_A

R175
470_0402
2

C307
100UF_D_10V

D
D
D
D

Q32
2N7002
S

1
2
3
4

8
7
6
5

2
G

<23,27,28,32,36> SUSP#

U13

SYSON#
2
G
Q7
2N7002

SUSON
3

+5VALW to +5VS Transfer

+1.8VALW

Q35

22UF_10V_1206

D
RUNON

2N7002

Q8
2N7002
2 SUSP
G

S
3

S
C604

R39
470_0402

C40
10UF_6.3V_A

2 SUSP
G

+5VALW

C42

.1UF_0402

C43

.01UF_0402

+5VALW

+1.8VALW to +1.8VS Transfer


1

S
S
S
G

1
2
3
4

D
D
D
D

2
2

C617

C616

.1UF_0402 22UF_10V_1206

RUNON
R412
1M_0402

8
7
6
5

C615

SUSP

+1.8VS

U8 SI4800
R413
470_0402

SI4800
1
S 2
S
3
S 4
G

D
D
D
D

2
1

2
G
Q34
2N7002

+5VS
U46

8
7
6
5

+5VALW

R405
100K_0402

+12VALW

+
2

4.7UF_16V_A

C605
100UF_D_16V

+3VALW

+3VS

+3VALW to +3VS Transfer


C421

C336

22UF_10V_1206

C315
10UF_10V_A

R189
470_0402

.1UF_0402

C325
100UF_D_10V

S
S
S
G

1
4

D
D
D
D

1
2
3
4

U14 SI4800
8
7
6
5

D
RUNON

Q9
2N7002
2 SUSP
G

S
3

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:

DC/DC Circuit
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

31

of

41

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL LECTRONICS,INC.


E
AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THECUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS HEET
S
NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECTRONICS,INC.
PC149
4700PF

CPU-CORE/VTT
2

B+
PL18

4.7UF_1210_25V

4.7UF_1210_25V

B++

PC148
4700PF

PC150
4700PF

1
PC163

PC161

PC160

4.7UF_1210_25V

4.7UF_1210_25V

<6> CPU_VID4

+5VALWP

PR196

15

OVP

SUS

REF

S1

ILIM

S0

GND

TON

3
2
1
1

1
4

5
6
7
8
4

+5VALWP

4
NC_TEST3
PC132
0.1UF_0805

1
PR236
1
PC136

PC167
@.01U/16V

0.1UF_0805
PU7

PR237
@0

1
PR232

PM_DPRSLPVR

PR212
1K_1%

<16>

V+

NO3

COM

NO1

NO0

NO2

10

KC-FBM-L11-322513-201LMAT
PC152

SUSP#
VTTVILIM

6
2

2 VTTVREF
PR201
14.3K_1%

PR209
150K_1%

ADDB

7
16
8

V+

DH

PGOOD

LX

SHDN

DL

ILIM

PGND

N/C

N/C

REF

N/C

TON

OUT

AGND

FB

19
1
20
13

D2

D1

D0

VOLTS

D4 = 1

D4 = 0

0.975

1.75

0.950

1.70

0.925

1.65

0.900

1.60

0.875

1.55

0.850

1.50

0.825

1.45

0.800

1.40

0.775

1.35

0.750

1.30

0.725

1.25

0.700

1.20

0.675

1.15

0.650

1.10

0.625

1.05

0.600

1.00

VTTBST
1
PR242
VTTVLX

0.1UF_0805
2
0

PC129

PC127
PC130
0.1UF_0805_25V

+
PQ42
SI4810DY

0.01UF

<5,16> H_DPSLP#
<6,16> PM_GMUXSEL

VTTVDL
4

12
PC144
220UF_D_4V

11

PR220
3K_1%

9
5

VTTVFB

1
PR247

2
@0

NC_TEST4

MAX1714A
2

PC128
0.22UF_0805_16V

PC137
150PF

PR206
12K_1%

PC141
1UF_0805_25V

Compal Electronics, Ltd.


Title

CPU VCORE
Size

Document Number

Rev
2

ADY11 LA-1181
Date:
A

+VTTP
1

PL16
4.7UH-SPC-1205P-4R7A

D3

PR202
10K

S
4

BST

PR210
PR211
PR227
16.2K_1%
61.9K_1%
604K_1%
19.6K_1%

5
6
7
8

SKIP

14

1
1K_1%

PQ31
2SC2411K

PR226

3
2
1

10

VDD

4.7UF_1210_25V

1
2
5
6

PQ43
SI3456DV
G
3

PR244
0

18
17

<5> VTT_PWRGD

GND

4.7UF_1206_16V
1SS355

SB+

4.7UF_1210_25V

0.1UF_0805_25V

ADDA

MAX4524
2

PC155

PC153

INH

PR203
10K

B+

PL19

PD32

VCC

2
PR216

OUTPUT

15

1
510_1%
1
604_1%

+3VALWP

PU10

SB+

PU3

2
PR214
2
PR215

- 4

@0

10

2VREF

4.7UF_1206_16V

+ 3

1
MAX4322

PR245

PC156

2
0

18

+5VALWP

PR197

1000PF_0603

19

PC134

PC133
5

PC154
4.7UF_0805_10V

10

2
@0
2

13

@10K

PD35
EC31QS04

PR230

PR195

+
220UF_D_4V

PR219
27.4K

220UF_D_4V

B++

PR243
0

<23,27,28,31,36>

PC145
PC146

PQ39
SI4362DY
2

PQ38
SI4362DY

ZMODE

PQ37
SI4362DY

NEG

16

PC131
0.1UF_0805

12
PR218
24.9K

POS

VDD

11

FB

SDN/SKIP

CC

1
3mR

PC171
0.1UF_0805_25V

PC140 2VREF
1U

V+
VCC

26

2
0 PR193
2
0 PR192
2
0
PR246

PR208
180K_1%

DL

TIME

PC157
17
4.7UF_0805_10V
PC165
6
470PF_0603
20

316K_1%

D1

<28,31> VR_ON

BST

VGATE

1
3mR

2
PR228

D2

28

3
2
1

51K 2
PR225

DH

D0

14

PR207

LX

D3

3
2
1

25

D4

VTTLX

5
6
7
8

23

2
PR229

CEP125-0R8NC-U
27

3
2
1

22

24

<30> VGATE

PL17

MAX1718
1

21

PR185
0

PR186
@10K

PD33
1SS355

20
PU6

2
+5VALWP

PQ36
IR7811A

IR7811A

3
2
1

PR217

PR182
0
1

PR183
0
PR184
0

<6> CPU_VID0

5
6
7
8

PR181
0

2
2

<6> CPU_VID1

PQ35

2
2

2
<6> CPU_VID2

+CPU_CORE

<6> CPU_VID3

PC162
4.7UF_1210_25V

PC151
4700PF

2200PF

PC164

1
PC147
4700PF

PC169

KC-FBM-L11-322513-201LMAT

5
6
7
8

PR191
1M

5
6
7
8

PR190
1M

PC170
0.1UF_0805_25V

PR189
1M

PR188
1M

PR187
1M

+3VALWP

Friday, November 16, 2001

Sheet
E

32

of

41

Detector

+5VALWP

PR29
100K_0402
2

+5VALWP

AIR_ADP# <29>
1

1
AIR_ADP

100K

100K
2

BATT++

BATT+

PQ11
DTC115EUA

PR1

PJP11
4MM

BATT+

PL4

<34>

PR2

100K

6C/8C#/4C# <29,34>

BATT++

1K_1%

VIN
PL2
2
PR170
10_1206

12

PR34
1K
1

BATT_TEMP

PCN2
BTC-07GR4 7P

BATT_TEMP <28>

PD7

PC26
1000PF

@BAS40-04

1
2
3
4
5
6
7

FBM-L11-453215-900LMAT

PR35
1
PR36
1K

1 ADPIN

2
2

+5VALWP
6.49K_1%

PCN3
@2DC-S107B200
1

@7A

1
2

PZD6
RLZ24B

PL3

PF1

4MM

PC25
100PF

ADPGND1

PJP4

1
2

4
5
6
7

PC24
470PF_0805_25V

FBM-L11-453215-900LMAT

GND
AIR_ADP

PD31
@EC10QS04

PC23
470PF_0805_25V

ADPIN

@1K_1%

PC29
1000PF

3
VIN

PC28
100PF

PCN1
RP34-8RD-3PDL2J

PR3
FBM-L11-453215-900LMAT

2 ADPGND

PR37
100

PCN2 battery connector pin assignm

ent

PR43 100
2
1
<5,15,28,29> SMB_EC_CK1

PD8
@BAS40-04

PD9
@BAS40-04
3

+5VALWP

+5VALWP
B+

PR46
499K_1%

1
1

PC111
1000PF

2
1

PACIN <34>

PR54
47K

ACIN <17,28,35>

PQ12
2N7002

Precharge detector
15.9V/13.2V FOR
ADAPTOR

PACIN <34>
1 PACIN

2
1
PC108
0.1UF_16V

PR163
10k

PR162
10K

PC109
0.01UF

PZD5
RLZ5.1B

PR164
10K

100K

PR158
20K_1%

2 SYSON

PQ13
DTC115EUA
100K

PC107
1000PF

PR49
499K_1%
PR48
215K_1%

1
1
2

PR50
10K

RTCVREF

VIN

PR159
22K

LM393A
PC31
1000PF

PU12A
LM393A

1
VS

VIN

PR160
1M_1%

1
2

PD11
RB751V
<34> ACON

PU12B
1

Vin Detector
17.93V/17.2V

PD10
RB751V
<35> SHDN#

PC32
0.1UF_16V

+5VP

PR45
1M_1%

PR44
100K

PR157
84.5K_1%

SMART Battery:
1.BAT+
2.LI/MH#
3.B/I
4.TS
5.SMB_EC_DA1
6.SMB_EC_CK1
7.GND

SMB_EC_DA1 <5,15,28,29>

2
1

SYSON <28,31>
4

RTCVREF

PR161
10K

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:
A

Detector
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

33

of

41

Charger

Iadp=0~3.07A
Iair=0~2.26A
B+++
P3

PL9

PC36
4.7UF_1210_25V

PC37
4.7UF_1210_25V

FBM-L11-322513-151LMAT

2
2

PR69
10K

FB2

6
2

PC46
2200PF

PR71
1K

2
1

<28> IREF

IREF=1 .746*Icharge
IREF=0~5V

PR75
100K_1%

PC118
.01UF_0402_16V
1

+INE1

10

PR76
10K

11

16

-INE3

OUTC1

FB3

OUTD

CTL

15

-INC1

PR77
330K

14

1
12

FSTCHG <28>

PL5
SLF12565T-220M
2

PR74
0.02_2512_1%
1
2

PD13
1SS355

PC49
1500PF
2

BATT+

PD30
RB051L-40

BATT+

PR79
10K

13

+INC1

ACOFF <28>

PC47
0.1UF_0805_25V
2

PR73
66.5K_1%

PR78
40.2K_1%

9
2

2
PQ18
DTC115EUA

LXCHRG
1

17

RT

100K

PC42
0.1UF_0805_25V

18

VCC

-INE1

100K

PC44
0.1UF_16V
1
2

19

VH

FB1

2
1
2

2
1

20

OUT

VREF

21

PC51
4.7UF_1210_25V
2
1

1
PR72
@30.1K_1%

PC101
1000PF

PC43
4700PF

-INE2 VCC(o)

PC41
2200PF

22

PC50
4.7UF_1210_25V
2
1

2N7002

CS

23

GND

+INE2

2
G

OUTC2

ACOFF#
5
6
7
8

10K

PQ17
FDS4435

PC48
68UF_EC_25V
2
1

PC45
0.1UF_16V

PR132
47K

11
1

AIR_ADP

PQ30

PR131
47K
2

PR65
19.6K_1%

<33>

1
PR66
100K

PQ19
2N7002

PR68
PC117
22.6K_1% .01UF_0402_16V

VIN

PR169

24

+INC2

PR70
10K_1%

ACON

<33> ACON

-INC2

PR61
47K

2
G

PR67
47K_0402
2

PR64
0

PU5
MB3878

2
1

PC40
2200PF

2
1
PR63
150K_0402

<33> PACIN

8
7
6
5

3
2
1

4
1

PQ16
SI4835DY
1
2
3

PR60
200K_0402

PD12
1SS355
ACOFF#

PC39
0.1UF_0805_25V

2
1

PR59
0.02_2010_1%
2
1

8
7
6
5

1
2
3

PQ15
SI4835DY
1
2
3
1

8
7
6
5

PQ14
SI4835DY
VIN

B+

P2

PC112
10PF

PR80
152K_0.1%

BATT++

1
PR81
309K_0.1%

PR4
3

PR177
205K_1%
2

100K

3S

DTC115EK
2

LI- ION : 12.75V

6C/8C#/4C# <29,33>

100K

2
5

100K

0.1UF

Charge voltage
4S LI-ION
NI-MH : 17.00V

+5VP

PC173

1
7
<28> BATT-OVP

2
PC113
22PF

PQ10

PR175
300K_0.5%

PU2B
LM358

1
305K_0.1%
PR5

PQ9
2N7002

PR174

PR176
143K_0.5%

PC116
0.01UF

PC115
@0.1UF_16V

2.2K

OVP voltage :
LI-4S :18.0V----BATT-OVP =3.97V
LI-3S :13.5V----BATT-OVP =2.98V
BATT-OVP=0.2 206*BATT++

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:

Charger
Document Number

Rev
2

ADY11 LA-1181
Wednesday, November 21, 2001

Sheet
E

34

of

41

+3.3V/+5V/+12V

B+

PL12
FBM-L11-322513-151LMAT

PC60

4.7UF_1210_25V

8
7
6
5

1
1

5
6
7
8

PC74
4.7UF_1210_25V

1
2

1
2

3
2
1

1
2

5
6
7
8

1
3
2
1

2
PD24
@RB751V

2
1
2

PC87
150UF_D_6.3V_FP

PC86
150UF_D_6.3V_FP

PR136
@0

VL

PD23
EP10QY03

10K_0402_1%

PR239
POK
2

PR106
1

PC123
100PF_0402

1
1

2
2

1
2

1
PR137
10.2K_0402_1%

2
PR104
@0_0402

PR156
47K_0402

+5VALWP

2
PR103
0_0402

1
2

PR105
@100K_0402

PC106

PR101
0.012_2512_1%

CSL5

VL

680PF_0402

NC_TEST2

VL

PC72
0.1UF_0805_25V

PC71
2200PF

2
1

1
2

PC76
0.1UF_0805_25V

1
2

PC81
4.7UF_1206_10V

PC172

CSH5

2.5VREF

+5VALWP

VS

PC122
47PF_0402

PR179
2M_0402

1
PC121
@.01UF_0402

4
PC80
@1000PF

TIME/ON5
RUN/ON3

PQ24
SI4810DY

DL5

MAX1632

4
5
18
16
17
19
20
14
13
12
15
9
6
11

CSH3
CSL3
FB3
SKIP#
SHDN#

PC73
4.7UF_1210_25V

PC70
0.1UF_16V

21
VL
PU9

LX3
DL3

28

DH3

12OUT
VDD
BST5
DH5
LX5
DL5
PGND
CSH5
CSL5
FB5
SEQ
REF
SYNC
RST#

PR241
@300K_0402

BST3

PT1
SDT-1205P-100

PQ22
SI4800DY

DH51

2
PR23
0_0402

PC124
@100PF_0402

PC120
100PF_0402

PR238
@0

PR134
10K_0402

PD22
EP10QY03

PR240
10K_0402

3.57K_1%

PD19
EC11FS2
1 FLYBACK

2
PR135

1
2
3
10
23

<17,28,33> ACIN
1

CSH3

PR99
0_0402

GND

26
24

V+

22

27

PC83

150UF_D_6.3V_FP
2
1

PC82
150UF_D_6.3V_FP
2
1

PC75
4.7UF_1210_25V

25

+3VALWP

+12VALWP

1
2
3

2
PC78
0.1UF_0805_25V

1
2

DH3

DL3
PC79
@1000PF

PR178
1M_0402

PR100
0.012_2512_1%

PR96
22_1206
2

B++++

1
2
3

PR98
10_1206

LX3

4
PC119

PL7
SLF12565T-100M

PC69
4.7UF_1206_10V

PR22
0_0402
2

PQ23
SI4810DY

47PF_0402

VS

DH31

8
7
6
5

+3.3V Ipeak = 6.6 6A ~ 10A

SNB

PC68
0.1UF_0805_25V
1
2

PQ21
SI4800DY
4

PR97
0_0402

BST51

VL

1
2

PC67
4.7UF_1210_25V

PC66
4.7UF_1210_25V

PC65
2200PF

1
2

PC64
0.1UF_0805_25V

DAP202U
PD20
BST31

PC63
0.1UF_0805_25V
B++++

PC61
470PF_0805_100V
1
2

0.047UF_16V
47K_0402_1%

+5V Ipeak = 6. 66A ~ 10A

PR155
47K_1%

PR150

NC_TEST1

2.15K_1%
PR152
16.9K_1%

PU4B
5

LM393A
7

SHDN# <33>

PC104
1UF_0805_25V

PH1
10K_1%_0805

PC103
1000PF

PC89
0.047UF_16V

PR153
100K_1%

PR154
100K_1%

VL

CPU thermal protection at 85 degree C


Recovery at 45 degree C

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,I
NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY
THEOFCOMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NORINFORMATION
THE
CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTCOMPAL
OF
ELECTRONICS,INC.
Date:

+3.3V/+5V/+12V
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
E

35

of

41

+1.8VALW/+1.5VS
+1.8V+-5%

D
S

2.5VREF

PR224
5.1K

100K
PR199
100K_1%

PQ33
DTC115EK

100K

PC126
0.01UF

PQ26
DTC115EK

PR198
100K

PC166
68PF

2.5VREF <35>

PR222
38.3K_1%
2
1

2.5VREF
+5VALWP

PR221
300K_0.5%

2
PC125
0.01UF

2
1
PC143
220PF

1
2
-

PC139
150UF_D_6.3V_KO

PR200
200K_1%
1

8
3

PR194
0

PR223
5.1K

G
3

PU2A
LM358

PC168
0.1UF_16V

PU4A
LM393A
2

PC135
0.1UF_16V

+1.5VSP
VS

PR235
@10K

VL

PC142
2200PF

3
PQ32
2SA1036K 1

PC138
150UF_D_6.3V_KO

PR205
10K

PQ25
PR213 2SC2411K
1K
2
2

1
1

2
2

PD37
RB751V

PR204
10K

PD36
RB051L-40

PC159
4.7UF_1206_25V

6
5
2
1

+1.8VALWP
PC158
4.7UF_1206_25V

PL14
5UH_SPC_06704-5R0A
2
1

LX18

6
5
2
1

4
1

+1.5VS+-5%

PQ40
SI3442DV

+1.8VALWP

PQ41
SI3445DV

+5VALWP

100K

SUSP# <23,27,28,31,32>

100K

PR83
200_1206
2

VS

PD17
RLS4148

PR84
1.5K_1206

PR85
1.5K_1206

PJP5
4MM

+VTTP

B+
2
1

PZD2
RLZ4.3B

+1.5VS
3

PJP7
3MM
PZD3
RLZ5.1B

+5VALWP

PC56
0.1UF_16V
+12VALWP

PJP10
3MM
PR95
200

OUT

+1.8VALWP
2

+1.8VALW

CHGRTC

PC59
4.7UF_1206_25V

PC58
1UF_0805_25V

PR21
200

GND

3
1

IN

+12VALW

RTCVREF

PU8
S-81233SG

PZD4
RLZ16B

+3VALW

2
PR94
22K

CHGRTCP

+5VALW

PJP8
3MM
+3VALWP

<30> EC_ON#

PR92
150K

1
1

PC55
0.1UF_0805_25V
2

PR91
100K

PC54
0.22UF_1206_25V

+VTT

PJP6
3MM
+1.5VSP

PR89
200_0805

+5VP
PR90
10K

PR20
1.5K_1206

PQ20
TP0610T
2

PR126
1.5K_1206

1
2

BATT+

VS1

PD16
RLS4148
1

VIN

PD15
RLS4148
2

PR173
200_1206
2

Compal Electronics, Inc.


Title

+1.8VALW
Size

Document Number

Rev
2

ADY11 LA-1181
Date:
A

Tuesday, November 20, 2001

Sheet
E

36

of

41

Version change list (P.I.R. List)


Item

Page 1 of 2

Fixed Issue

Reason for change

Rev.

PG#

Core-logic Chipset r evision

Revision er ror

0.1B

Leakage is sue

0.1B

19

Leakage is sue

+5VSHDD is on when plug AC-in and OS en ter S3,S4,S5.


we used GPIO25 of ICH3-M to control IDE
power,but this
pin is resume plane, keep high af ter RSMRST#.
+5VS has about 500mv backdrive on S3;U2 6 is +5VS but
pin9 pull up to +3V

FW82830M should be QB88 and FW8280


be QB6 3
Q14 pin3 change from +5VALW to +5V

0.1B

+3VS has about 253mv backdrive on S3;Q 16 is on when


S3
+3VS has about 253mv backdrive on
S3;U37 pinU5
(ICH_THRM#)is +3VS plane

0.1B
0.1B

Signal connect e rror

Leakage is sue

Leakage is sue

SM_CLK/DATA

read and progr am failed

Level shi ft

U26 is +5V output,but ICH3(U37 )pinAA

Correct Part v aule

BOM and schematic vaule d ifferent

None

10
11
12

6 is 3V level

B.Ver#

Phase

1CAM should

0.1

SST

S power plan

0.2

SST-2

R94 pull up change t o +3VS

0.2

SST-2

12

R268 pull up change t o +3VS

0.2

SST-2

16

ICH_THRM# pull up change

0.2

SST-2

0.1B

14

Correct net,U9 pin29 should be connec t to SMB_DATA


U9 pin30 should be connect t o SMB_CLK

0.2

SST-2

0.1B

Change R415 from 100_0402 to 5.6K_04

02;BOM change

0.1

SST

0.1B

19

Change JP20

o"HH9921-S6"

0.1

SST

20

Change JP10 vaule from"JM361


"JM36113-L5 H7"

0.2

SST-2

0.2

SST-2

0.2

SST-2

0.2

SST-2

0.2

SST-2

0.2

SST-2

Change U33(97338) pin7 1 to NC

VR_ON cont rol

0.1B

29

VTT_PWRGD# connect to U2 9 pin146

Debug ca rd

Design change,used PCI port 80 debug

0.1B

28

Change JP23 connector type from "SUYI


to "AMP 5-175638-0";BOM change

None

FAN power transistor change. Max. power of 2


SC2411 is 0.2W.
Max. power of FMMT619 is 0.615W.
Component is 0402 size,but layout pad
size is 0603

0.1B

0.1C

17

Mechanical

0.1C

32

Change Q4 from "2SC2411EK" to


"FMMT619"
BOM chan ge
Layout modified and correct vaule
from"5PF" to
"5PF_0402";BOM needn't
change
Change C440 from "100UF_D_16V" to " 33UF_D2_16V"
D2 size H=1.9mm; BOM change

0.1C

28

SST2 don't ch ange

0.2

SST-2

0.1C

14

0.2

SST-2

0.2

SST-2

0.1

SST

0.2

SST-2

We check layout file,C290 closely U7 pin AF26,so change


C290 from pag11 to pag10, C156 and C 186 change to
page 11(not change layout),and add C632 [0.01UF_0402]
near AF 26

0.2

SST-2

1.Change H1,H2,H6,H7 from 2.8m m to 3.2mm


2.Change H9 from 3.5mm long by
3.0mm wide
R12,R16 resistor to restore,de l item16-1

0.2

SST-2

0.1

SST

0.2

SST-2

0.2

SST-2

0.2

SST-2

Component pad

size

limit

issue

card solution

limit H:2.2mm,used compone

* 15

Delect item 11

PT implement PCI port 80

16

Clock wavef orm

Clock waveform ove r SPEC


1.CLK_HCLK/H CLK#
2.CLK_DR EF
3.CLK_ICHA PIC

17

None

LPC debug card on developer stage

18

Correct Part v aule

19
20

nt over limit

solution

N 12793-10G2"

16

1.Change R16,R12 from"33_1%"


to"10_1%"
2.Change R59 from"22_0402" to
"10_0402"
3.Pop R352 (10_0402) and pop
C559(10PF_04 02)

0.1C

28

Depop JP23 (S ST2)

BOM and schematic vaule d ifferent

0.1D

24

Change R383 vaule from "29K_1%" to

Fixed EE issue list item11( 2001/6/5)

Intel recommend series resistor

0.1D

17

Add R453(0_0402) series resistor on PIDERST

Fixed EE issue list item10( 2001/6/5)

VCCA_DAC should have a 0.1uf and 0

0.1D

10,1 1

, depop it.

on IDERST
.01uf nearby

Fixed EE issue list item26,27(


CLK_HCLK/HCLK# resistor need

2001/7/12)

n't change

1.Change CPU thermal skew hole s


2.CD-ROM skew hole size change.
Follow Dell's reco mmend

23

ICH3 revis ion

SST2 used QB62 or SL5LF

24

CLK EMI is sue

Add AC termination on as belo


1.CLK_GB IN
2.CLK_ICHH UB
3.CLK_ICH 48
4.CLK_PCI_S IO
5.CLK_GBO UT
6.CLK_ICHP CI

ize change.

revision
w signals

Gerber rele ase

"28.7K_1%"
#--- BOM modify

0.1D

26

0.1E

14

0.1E

17

0.1F

Change R376 from"22.6_1%" to "18.2_1% ",BOM already


change O K.
1.Pop R168(33_0402) and C297( 5PF_0402)

16

2.Pop R306(33_0402) and C514(

5PF_0402)

3.Pop R369(10_0402) and C574(

5PF_0402)

27

4.Pop R324(10_0402) and C543(

14

5.Pop R69(33_0402) and C92(1

16
None

0.2

6.Pop R311(10_0402) and C518(

13-L1H" to

27

Mechanical

25

vaule from"HH9927-S6" t

0.1B

13

21

to +3VS

Original design, EC_FLASH control by IC H3-M GPIO40 or


97338 pin 71. Follow compal common desi gn, use ICH3-M
GPIO40 control EC_F LASH#.
For EC can control VR_ON after VT T_PWRGD# on

14

* 22

Modify List

5PF_0402)
0PF_0402)
15PF_0402)

Change Schematic revisio n to 0.2

Compal Electronics, Inc.


Title

P.I.R History
Size

Document Number

Rev
2

ADY11 LA-1181
Date:
5

Friday, November 16, 2001

Sheet
1

37

of

41

Version change list (P.I.R. List)


Item
26

Page 2 of 2

Fixed Issue

Reason for change

Rev.

PG#

None

Connector cha nge

0.2A

19

27

None

Remove OZ6933 PCMCIA Co ntroller

28

None

Remove Power Switch (2 slot) and change Ca

29

None

Add Board_ID for check Mosaic

30

None

Remove Serial

31

None

Lid Switch function change to Touc

32

None

Debug Port change con nector

33

None

Power on switch board change

34

None

ICH_VGATE de lay

35

None

Schematic remove Serial PORT

and Tang

Port
h-pad Board

connector

function

Phase

0.3

PT

21
25

1. Del Page 21, and shift


2. Del CF5, CF9

0.3

PT

22

1. Schematic remove U20, C437, C403, C402 , C436, C434,


C433, C415, C408, C429, R219, R211, C79, C
80, C430, C318,
L53, C358, C343, C401
2. Change PCMCIA Socket vaule to FOXCO NN 1CA415M1-TA

0.3

PT

0.2A

26

Add U33 Pin71 for BOARD_ID, and Add Resiste


and R566 0_0 402

0.3

PT

0.2A

27

De-pop C1, C5, C10, C11, C109, U1, JP3,


L27, L28, L29, L30, L31, L32,
L33, Q26.

0.2A

27

Schematic change, JP15 Pin17 net to +3VS,


to LID_S W#

0.2A

27

0.2A

30

0.2A
0.2A

r R565 10K_0402

0.3

PT

0.3

PT

Debug Port change connector from SUYIN


12793A-10G2 to
AMP 5-17563 8-0
Power On switch board change from AM P 4-175638 to
SUYIN 12750AR-16 G2T-9

0.3

PT

0.3

PT

30

1. Schematic change, connect R381 pin2


2. De-pop R386, R381

0.3

PT

27

Schematic remove U1, CP1, CP2, C1, C5, C 10, C11, C109,
L26, L27, L28, L29, L30, L31, L32 , L33, Q26.
BOM change R20 from 1K_1% to 499_1%, R22
from 2K_1% to
1K_1%

0.3

PT

0.3

PT

BOM add R441 10K_0402, Depop R4

0.3

PT

36

CMOSREF not strong enough t o provide


the target 2/3 ratio devider

Change divider to 0.5K/1K at the ne xt available


opportunity to gain more CMOSR EF margin.

0.2A

None

M/B ID change t o PT

0.2A

17

38

None

Gerber rele ase

39

Cost do wn

Core_VCC and VTT capacitor

0.3
0.3

down page

B.Ver#

0.2A

37

reduce.

85201-2605

0.2A

rdBus Connector

Modify List
FDD Connector change to ACES

Gerber release, schematic cha

CP1, CP2, L26,


JP15 Pin18 net

to U40 Pin12

43 10K_0402

nge to 0.3

0.3

PT

0.3

PT

1.0

ST

1.0

ST

40

None

Remove Capaci tor

0.3B

1. BOM depop C126, C120, C293, C210,


C283, C118.
2. BOM change from 150UF_D2_6.3V (45mOhm) to
220U_D2_4V(25mOhm), Location C29, C39, C3 2, C292, C260,
C119, C153, C289, C37.
3. BOM depop C122, C127.
4. BOM change from 150UF_D2_6.3V (45mOhm) to
220U_D2_4V(25mOhm), Location C27,
C23, C303.
Schematic remove C120.

41

None

Resister Package e rror.

0.3B

24

Change R351 100K_0603 to R351

42

Suspend from lid switch, ca n't resume


from open L CD.

Change Lid switch power plan from +3

0.3C

27
29
30

1. Schematic JP15 Pin.17 t o +3VALW


2. Schematic JP12 Pin.15 t o +3VALW
3. Schematic R404 Pin.1 t o +3VALW

1.0

ST

43

For thermal module difference

Add stand-off on mother

0.3C

1.0

ST

0.3C

31

Schematic remove C39, add M11 S MDC200M157,


BOM add C283 220U_ 4V_D2.
BOM change C307, C325, C605 from 10 0UF_D_16V to
100UF_D_10 V.

11

Mosaic-P4

Change Capacitor

VS to +3VALW.

board.

44

None

45

CRT connector layout

spec.

1.0

ST

0.3C

1.0

ST

46

Factory DXF

47

Test point rev iew.

Layout modi fy.

0.3C

1.0

ST

Layout modi fy.

0.3C

1.0

48

3COM 3C920 referance RJMA G version


update .

VDDPCI[1:5] pins from +3VASB

ST

49

Poor quality w/static


recording func tion.

Change MIC-AMP power

50

None

51

None

shift.

fix.

noise on

100K_0402

Shift CRT connector

1.33mm

to +3VS.

0.3C

20

1. Schematic modify, U21 some pin change p


ower plan from
+3VASB to +3VS ( VDDPCI [1:5] )
2. Schematic C370, C371, C373 change po wer plan from
+3VASB to +3 VS.

1.0

ST

0.3C

24

1. Schematic modify, MIC-AMP change power


plan from VDDA
to AVDD_MIC with R567 49.9Ohm to
AVDD_AC97
2. Schematic add C633 10UF_ 10V_1206

1.0

ST

M/B ID change t o ST

0.3D

17

BOM depop R441, R444, add R442, R4

1.0

ST

Change Back-light gate pow er plan.

1.0

15

1. U12 power plan from +3VS


2. U12 from SH08 t o ST08

plan.

43 10K_0402

to +5VS.

Compal Electronics, Inc.


Title

P.I.R History
Size

Document Number

Rev
2

ADY11 LA-1181
Date:
5

Friday, November 16, 2001

Sheet
1

38

of

41

Version change list (P.I.R. List)


Item
D

Fixed Issue

Page 1 of 3

Reason for change

Rev.

CPU_CORE voltage is unstable

Change PWM frequency from 300KHZ to 200KHz

0.1B

+5VALWP is unstable

Change PWM frequency from 200KHz to 300KHz

Output capacitor of Charger interfere


mechanical (switch board)

PG#

Modify List

B.Ver#

Phase

33

1.Change PR197 from 100 to 0


2.Connect pin10 of PU6 to pin9 of PU6

0.1

SST

0.1B

36

1.Delete PR104 and add PR103 0_0402


2.Connect pin15 of PU9 to ground

0.1

SST

Change PC48 to small size,the height limited is 6mm in


this area

0.1B

35

Change PC48 from 100UF to 68UF

0.2

SST2

The time sequency of +1.5VS is error

Change REF voltage from 2VREF of MAX1718 to


2.5VREF of MAX1632

0.1B

37

.Change PR200 from 100K_1% to 200K_1%

0.2

SST2

The time sequency between 1.8VALWP


and 3.3VALWP is error

Delay 3.3VALWP start-up time

0.1B

36

Add PC172 680PF connected to pin7 of PU9

0.2

SST2

RTC battery that will be shortage.We


changed RTC battery from Panasonic
VL1220 to Maxell ML1220

Change LDO charger to 3.3V for Maxell ML1220

0.1B

37

Change PU8 from S-81235SG to S-81233SG

0.2

SST2

34

1.Change PR157 from 78.7K_1% to 84.5K_1%


2.Change PR48 from 249K_1% to 215K_1%

Correct part vaule

BOM and schematic vaule different

0.1D

37

Change PL14 vaule from"5UH_SPC_06703" to


"5UH_SPC_06704-5R0A"

0.1

SST

Correct curreent limited value

Modify current limited from 2.86A to 3.22A

0.1E

35

1. Change PR68 from 24.9K_1% to 21K_1%


2. Change PR65 from 14.3K_1% to 15.8K_1%

0.1

SST

Correct OCP of +VTT

Modify OCP current from 4.6A to 7A,because peak


current of +VTT is 6A in spec.

0.1E

33

1. Change PR201 from 10K_1% to 14.3K_1%


2. Change PR209 from 15K_1% to 150K_1%

0.1

SST

Based on EMI dept. test result, we must add bead


and change capacity for EMI issue

0.1F

34

1. Add PL4 FBM-L11-453215-900LMAT


2. Change PC 24 from 0.1UF to 470PF and add PC23
470PF

0.3

PT

0.1F

34

0.3

PT

Modify Vin Detector and Precharger Detector circuit

10

Add ferrite bead for EMI

11

Add NI-MH battery

12

Plug in AC adapter and battery on


time the system can't turn on.

Separate precharge path from VS net because leakage


current is larger than p recharge current

0.1F

37

1. Connect pad2 of PD16 to VIN


2. Add PR20 1.5K and change PR84,PR85,and PR126 to
1.5K

0.3

PT

13

Safety protection for RTC battery

Add PR21 to prevent damging PR95 to damage RTC


battery

0.1F

37

1.Add PR21 200 ohm

0.3

PT

14

Design margin is not enough

0.1F

35

Change battery OVP from 18.1V to 18.3V and


BATT-OVP will be changed from 4V to 4.04V

0.3

PT

prevent NI-MH battery over charge/discharge

increase design margin for battery OVP prevent it


misses

Add PF1 7A fuse

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL LECTRONICS,INC.
E
AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THECUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS HEET
S
NOR THE INFORMATION CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECTRONICS,INC.
Date:
5

PIR
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
1

39

of

41

Version change list (P.I.R. List)

Page 2 of 3

Fixed Issue

Reason for change

Rev.

PG#

15

noise issue from DC-DC

Change choice heighter capacitor

0.1F

35

16

Implement 6cell li-on

Add identifird signal 6C/8C#/4C#

0.1F

33

17

modify charge voltage

Change 4S charge voltage to 17V for 4 cell/8 cell


and NI-MH,other 3S is 12.75V for 6cell

18

AC adapter is changed to 60W

Item

0.1F

modify constant power limited to 49W and


disable air adapter

20

21

Add compensation solution


for +5VALWP

AC adapter is changed to 70W

Charger can't charge

B.Ver#

Modify List
Change PC60 form 2.2F_1206_25V to 4.7UF_1210_25
1.Add PR1 100K and PR2 1K_1%
2.Add PR3 no-pop

33

1. Change PR80 from 100K_0.1% to 152_0.1%


2. Change PR81 from 316K_0.1% to 309_0.1%
3. Add PR4 305K_0.1% and PR5 100K
4. Add PQ9 2N7002 and PQ10 DTC115EK
5. Add PC173 0.1U
1. No-pop PCN1 and Populate PCN3
2. No-pop PR29 and PQ11

34

3. Change PR68 from 21K_1% to 28.7K_1%


4. No-pop PQ30, PR65,PR131,PC101

35

1. Populate PC122 47PF_0402


2. Populate PR179 2M_0402
3. Populate PR137 10.2K_0402_1%
4. Populate PC123 100PF_0402
5. Change PR136 from 0_0402 to
10K_0402_1%

34

Phase

0.3

PT

0.3

PT

0.3

PT

0.3

PT

0.1G

19

The solution will reduce quantity of output


capacitor and increase stability

0.1G

modify constant power limited to 64W and


support air line adaptor identified

0.1H

Pin3 of PQ9 isn't connectted pad2 of PR80

0.3C

33

1. No-pop PCN3 and Populate PCN1


2. Populate PR29 and PQ11

34

3. Change PR68 from 28.7K_1% to21K_1%


4. Populate PQ30, PR65,PR131,PC101

34

Pin3 of PQ9 isn't connectted pad2 of PR80

0.3

PT

0.3

PT

1.0

PT2

22

power limited for airline adapter is


disabled

23

Delete on-pop component

24

Add FUSE for safety of battery

25

Fix Battery OVP protect point

The control signal can't turn on PQ30

0.3C

34

1.Change control signal from AIR_ADP# to


AIR_ADP
2.Change PQ30 from TP0610T to 2N7002

1.0

PT2

0.3C

35

Delete PC84,PC85,PC88

1.0

PT2

Support NI-MH battery

0.3D

33

Reverse PF1 and add PJP4

1.0

ST

Fix the table of Battery OVP and reserve


PC115 about OP Amps oscillates

1.0

34

1.0

ST

Because the reverse component is not need

No-pop PC115

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL LECTRONICS,INC.
E
AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THECUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS HEET
S
NOR THE INFORMATION CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECTRONICS,INC.
Date:
5

PIR
Document Number

Rev
2

ADY11 LA-1181
Friday, November 16, 2001

Sheet
1

40

of

41

Version change list (P.I.R. List)


Item
26

Page 3 of 3

Fixed Issue

Reason for change

Rev.

PG#

enhance conductivity of connector

enhance conductivity of battery connector based on


customer's requirement

1.0

33

Modify List

B.Ver#

Change PCN2 from BTC-07GR1 to BTC-07GR4

1.0

Phase
ST

27

modify constant power limit spec.

28

Fix DFX issue

29

Fix DFX issue

modify constant power limited from 3.22A to 3.07A

The PL14 and PL15 is co-layout, but PL15 will not


be used.
Delete PJP9 for SMT process.

1.0

34

1.0

36

1.0

36

1. Change PR68 from 21K_1% to 22.6_1%


2. Change PR65 from 15.8K_1% to19.6K_1%

Delete PL15

1.0

ST2

1.0

ST2

Delete PJP9

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL LECTRONICS,INC.
E
AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THECUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS HEET
S
NOR THE INFORMATION CONTAINS MAY BE Size
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECTRONICS,INC.
Date:
5

PIR
Document Number

Rev
2

ADY11 LA-1181
Tuesday, November 20, 2001

Sheet
1

41

of

41

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