Neil Chainani

Lab 12 Pre-Lab Report

CONTROL PATH
module ctrl ( input wire clock , input wire clear , input wire less_than , input wire proceed , output reg a , output reg sq , output reg dl , output reg out ); reg[1:0] present, next; always @(posedge clock or posedge clear) begin if (clear == 1) present <= begin; else present <= next; end always @(*) begin case(present) start: if(proceed == 1) next = test; else next = begin; test: if(less_than == 1) next = update; else next = done; update: next = test; done: next = done; default next = begin; endcase end always @(*) begin a = 0; sq = 0; dl = 0; out = 0; case(present) start: a = 1; test: ; update:

begin sq = 1; dl = 1; end done: out = 1; default ; endcase end endmodule

DATA PATH
module data ( input wire clk , input wire reset , input wire ald , input wire sqld , input wire dld , input wire outld , input wire [7:0] sw , output reg lteflg , output wire [3:0] root ); wire [7:0] a; wire [8:0] sqrt, s; wire [4:0] del, dp2; wire [3:0] dm1; always @(*) begin if(sqrt <= {1'b0,a}) less_than <= 1; else less_than <= 0; end register #(.N(8),.BIT0(0),.BIT1(0))aReg (.load(ald),.clk(clk),.reset(reset),.d(sw),.q(a)); register #(.N(9),.BIT0(1),.BIT1(0))sqReg (.load(sqld),.clk(clk),.reset(reset),.d(s),.q(sqrt)); register #(.N(5),.BIT0(1),.BIT1(1))delReg (.load(dld),.clk(clk),.reset(reset),.d(dp2),.q(del)); register #(.N(4),.BIT0(0),.BIT1(0))outReg (.load(outld),.clk(clk),.reset(reset),.d(dm1),.q(root));

endmodule

Supplementary Module:
module register #(parameter N = 4, parameter BIT0 = 1, parameter BIT1 = 1) (input wire load , input wire clk , input wire reset , input wire [N-1:0] d , output reg [N-1:0] q ); always @(posedge clk or posedge reset) if(reset == 1) begin q[N-1:2] <= 0; q[0] <= BIT0; q[1] <= BIT1; end else if(load == 1) q <= d; endmodule module binary_to_dec( input [7:0] binary, output reg [3:0] hundreds, output reg [3:0] tens, output reg [3:0] ones ); integer i; always@(binary) begin hundreds=4'd0; tens=4'd0; ones=4'd0; for(i=7;i>=0;i=i-1) begin if(hundreds >= 5) hundreds = hundreds + 3; if(tens >= 5) tens = tens + 3; if(ones >= 5) ones = ones + 3; hundreds=hundreds << 1; hundreds[0] = tens[3]; tens = tens << 1; tens[0] = ones[3]; ones = ones << 1; ones[0] = binary[i]; end end

endmodule

TEST BENCH
module sqrt_tb; // Inputs reg clk; reg clr; reg go; reg [7:0] sw; // Outputs wire done; wire [3:0] root; // Instantiate the Unit Under Test (UUT) sqrt uut ( .clk(clk), .clr(clr), .go(go), .sw(sw), .done(done), .root(root) ); initial begin // Initialize Inputs clk = 0; clr = 1; go = 0; #10; clr=0; sw=25; go=1; #75; #100; clr=1; go=0; #30; clr=0; sw=49; go=1; #75; #100; clr=1; go=0; end always #5 clk =! clk; endmodule