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Internal Use Only

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PLASMA TV SERVICE MANUAL


CHASSIS : PB21A

MODEL : 60PA6500
CAUTION

60PA6500-SA

BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

P/NO : MFL67341906 (1201-REV00)

Printed in Korea

CONTENTS

CONTENTS . ............................................................................................. 2 SAFETY PRECAUTIONS ......................................................................... 3 SPECIFICATION........................................................................................ 4 ADJUSTMENT INSTRUCTION................................................................. 5 BLOCK DIAGRAM. .................................................................................. 12 EXPLODED VIEW .................................................................................. 13 SCHEMATIC CIRCUIT DIAGRAM ..............................................................

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LGE Internal Use Only

SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

General Guidance
An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks. It will also protect the receiver and it's components from being damaged by accidental shorts of the circuitry that may be inadvertently introduced during the service operation. If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified. When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1 W), keep the resistor 10 mm away from PCB. Keep wires away from high voltage or high temperature parts.

Leakage Current Hot Check (See below Figure)


Plug the AC cord directly into the AC outlet. Do not use a line Isolation Transformer during this check. Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to 0.5 mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Before returning the receiver to the customer,


always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock. With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 M and 5.2 M. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer.

AC Volt-meter

Leakage Current Cold Check(Antenna Cold Check)

To Instrument's exposed METALLIC PARTS

0.15u

Good Earth Ground such as WATER PIPE, CONDUIT etc.

1.5 Kohm/10W

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LGE Internal Use Only

NOTE : Specifications and others are subject to change without notice for improvement.

SPECIFICATION

1. Application range

This spec sheet is applied all of the PDP TV with PB21A chassis.

2. Requirement for Test

Each part is tested as below without special appointment. (1) Temperature: 25 C 5 C(77 F 9 F), CST: 40 C 5 C (2) Relative Humidity: 65 % 10 % (3) Power Voltage : Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models. (4)  Specification and performance of each parts are followed each drawing and specification by part number in accordance with BOM. (5)  The receiver must be operated for about 5 minutes prior to the adjustment.

3. Test method

(1) Performance: LGE TV test method followed (2) Demanded other specification - Safety : CE, IEC specification - EMC : CE, IEC

4. Model General Specification


No 1 Item Receiving System Specification 1) SBTVD / NTSC / PAL-M / PAL-N 2) DVB-T 2 Available Channel 1) VHF : 02~13 2) UHF : 14~69 3) DTV : 07-69 (VHF high/UHF) 4) CATV : 02~135 1) VHF : 02~13 2) UHF : 14~69 3) DTV : 14~69 (UHF) 4) CATV : 02~135 3 4 5 Input Voltage Market Screen Size 1) AC 100 ~ 240V 50/60Hz Brazil / chile / Peru / Venezuela / Costarica / Uruguay 42 inch Wide(1024 768) 50 inch Wide(1024 768) 50 inch Wide(1920 1080) 60 inch Wide(1920 1080) 16:9 FS PDP42T4#### PDP50T4#### PDP50R4#### PDP60R4#### (1024 768) (1024 768) (1920 1080) (1920 1080) 42PA all model 50PA4 all model 50PA6 all model 60PA6 all model 42PA all model 50PA4 all model 50PA6 all model 60PA6 all model Remark 50A6500-SA 50A4900-SA 42/50PA4500-DF 50A6500-SA 50A4900-SA

42/50PA4500-DF

6 7 8

Aspect Ratio Tuning System Module

9 10

Operating Environment Storage Environment

1) Temp : 0 ~ 40 deg 2) Humidity : ~ 80 % 1) Temp : -20 ~ 60 deg 2) Humidity : ~ 85 %

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ADJUSTMENT INSTRUCTION
1. Application Range
This spec. sheet applies to PB21A chassis applied PDP TV all models manufactured in TV factory.

4. PCB Assembly Adjustment


4.1. Using RS-232C
Adjustment sequence
Order 1.  Inter the Adjustment mode 2. C  hange the Source 3.Start Adjustment 4. R  eturn the Response 5. R  ead Adjustment data ( main ) ad 00 20 ( main ) ad 00 30 command aa 00 00 a 00 OK00x Set response

- A  djust 3 items at 3.1. PCB assembly adjustments " 4.1. Adjustment sequence" one after the order.

2. Specification

(1)  Because this is not a hot chassis, it is not necessary to use an isolation transformer. However, the use of isolation transformer will help protect test instrument. (2)  Adjustment must be done in the correct order. But it is flexible when its factory local problem occurs. (3) T he adjustment must be performed in the circumstance of 25 C 5 C of temperature and 65 % 10 % of relative humidity if there is no specific designation. (4)  The input voltage of the receiver must keep AC 100-240 V~, 50/60 Hz. (5)  Before adjustment, execute Heat-Run for 5 minutes.  A fter Receive 100% Full white pattern (06CH) then process Heat-run (or 8. Test pattern condition of Ez-Adjust status) How to make set white pattern 1) Press Power ON button of Service Remocon 2)  Press ADJ button of Service remocon. Select 10. Test pattern and, after select White using navigation button, and then you can see 100% Full White pattern. * In this status you can maintain Heat-Run useless any pattern generator * Notice:  i f you maintain one picture over 20 minutes (Especially sharp distinction black with white pattern 13Ch, or Cross hatch pattern 09Ch) then it can appear image stick near black level.

XB 00 40 XB 00 60 ad 00 10

b 00 OK40x (Adjust 480i Comp1 ) (Adjust 1080p Comp1) b 00 OK60x (Adjust 1080p RGB) OKx ( Success condition ) NGx ( Failed condition ) (main : component1 480i, RGB 1080p) 000000000000000000000000007c007b006dx (main : component1 1080p) 000000070000000000000000007c0083 0077x NG 03 00x (Failed condition) NG 03 01x (Failed condition) NG 03 02x (Failed condition) OK 03 03x (Success condition) d 00 OK90x

6. Confirm Adjustment

ad 00 99

7. End of Adjustment

ad 00 90

< See ADc Adjustment RS232c Protocol_Ver1.0 > Necessary items before Adjustment items Pattern Generator : (MSPG-925FA)  Adjust 480i comp1 (MSPG-925FA:model :209, pattern :65) - comp1 Mode  Adjust 1080p comp1 (MSPG-925FA:model :225 , pattern :65) - comp1 Mode  Addjust RGB (MSPG-925FA:model :225 , pattern :65) - RGB-Pc Mode * If you want more information then see the below Adjustment method (Factory Adjustment) Adjustment sequence aa 00 00: Enter the ADc Adjustment mode. xb 00 40: change the mode to component1 (No actions) ad 00 10: Adjust 480i comp ad 00 10: Adjust 1080p comp xb 00 60: change to RGB-Pc mode(No action) ad 00 10: Adjust 1080p RGB xb 00 90: Endo of Adjustmennt

3. Adjustment items

3.1. PCB Assembly adjustment

Adjust 480i Comp1 Adjust 1080p Comp1/RGB If it is necessary, it can adjustment at Manufacture Line  You can see set adjustment status at 9. ADJUST CHECK of the In-start menu

3.2. Set Assembly Adjustment

EDID (The Extended Display Identification Data ) Color Temperature (White Balance) Adjustment Make sure RS-232C control Selection Factory output option

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LGE Internal Use Only

5. Factory Adjustment

->  PU21A/PB21A : USE INTERNAL ADC(LM1) : using internal pattern.

5.1.  Auto Adjust Component 480i/1080p RGB 1080p

Summary :  A djustment component 480i/1080i and RGB 1080p is Gain and Black level setting at Analog to Digital converter, and compensate the RGB deviation Using instrument  A djustment remocon, 801GF(802B, 802F, 802R) or MSPG925FA pattern generator ( I t can output 480i/1080i horizontal 100% color bar pattern signal, and its output level must setting 0.7V0.1V p-p correctly)

* caution : Set Volume 0 after adjustment

5.2. Use Internal ADC(S7R)


< Adjustment pattern : 480i / 1080p 60Hz Pattern >  You must make it sure its resolution and pattern cause every instrument can have different setting  Adjustment method 480i Comp1, Adjust 1080p Comp1/ RGB (Factory adjustment) ADC 480i Component1 adjustment - Check connection of Component1 - MSPG-925FA -> Model: 209, Pattern 65  Set Component 480i mode and 100% Horizontal Color Bar Pattern(HozTV31Bar), then set TV set to Component1 mode and its screen to NORMAL ADC 1080p Component1 / RGB adjustment - Check connection both of Component1 and RGB - MSPG-925FA -> Model: 225, Pattern 65  Set Component 1080p mode and 100% Horizontal Color Bar Pattern(HozTV31Bar), then set TV set to Component1 mode and its screen to NORMAL  After get each the signal, wait more a second and enter the IN-START with press IN-START key of Service remocon. After then select 7. External ADC with navigator button and press Enter.  After Then Press key of Service remocon Right Arrow (VOL+) You can see ADC Component1 Success Component1 1080p, RGB 1080p Adjust is same method.  C omponent 1080p Adjustment in Component1 input mode RGB 1080p adjustment in RGB input mode  If you success RGB 1080p Adjust. You can see ADC RGB-DTV Success

- A DJ(EZ ADJUST) -> 6.ADC Calibration -> ADC Calibration(START) * E DID (The Extended Display Identification Data)/DDC (Display Data Channel) Download. Summary  It is established in VESA, for communication between PC and Monitor without order from user for building user condition. It helps to make easily use realize Plug and Play function. For EDID data write, we use DDC2B protocol. - Auto Download After enter Service Mode by pushing ADJ key, Enter EDID D/L mode. Enter START by pushing OK key. Caution: - N ever connect HDMI & D-sub Cable when the user downloading . - Use the proper cables below for EDID Writing

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LGE Internal Use Only

 It only needs to PCM EDID D/L for North America Product. (PU21A)

EDID data (Model name = LG TV) - RGB FHD 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 68 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 50 54 A1 08 00 31 40 45 40 61 40 81 80 D1 C0 01 01 01 01 01 01 1A 36 80 A0 70 38 1F 40 30 20 25 00 40 84 63 00 00 1A 66 21 50 B0 51 00 1B 30 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 00 ED - South Centural America _2D_FHD HDMI 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

* Edid data and Model option download(RS232) NO Item CMD 1 CMD 2 Data 0 Enter download MODE download Mode In A A 0 0 When transfer the Mode In, Carry the command. EDID data Model option download download A E 00 10 Automatically download (The use of a internal pattern)

0F 50 54 A1 08 00 31 40 45 40 61 40 81 80 D1 C0 01 01 01 01 01 01 1A 36 80 A0 70 38 1F 40 30 20 25 00 40 84 63 00 00 1A 66 21 50 B0 51 00 1B 30 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 D4 02 03 27 F1 4F 90 1F 04 13 05 14 03 02 12 20 22 15 11 16 01 26 15 07 50 09 57 07 67 03 0C 00 10 00 B8 2D E3 05 03 01 02 3A 80 18 71 38 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 0E 1F 00 80 51 00 1E 30 40 80 37 00 40 84 63 00 00 1C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4B

- Manual Download Write HDMI EDID data Using instruments - Jig. (PC Serial to D-Sub connection) for PC, DDC adjustment. - S/W for DDC recording (EDID data write and read) - D-sub jack - Additional HDMI cable connection Jig. Preparing and setting. - Set instruments and Jig. Like pic.5), then turn on PC and Jig. - Operate DDC write S/W (EDID write & read) - It will operate in the DOS mode.

< For write EDID data, setting Jig and another instruments >

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- South Centural America _2D_FHD HDMI 2 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 50 54 A1 08 00 31 40 45 40 61 40 81 80 D1 C0 01 01 01 01 01 01 1A 36 80 A0 70 38 1F 40 30 20 25 00 40 84 63 00 00 1A 66 21 50 B0 51 00 1B 30 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 D4 02 03 27 F1 4F 90 1F 04 13 05 14 03 02 12 20 22 15 11 16 01 26 15 07 50 09 57 07 67 03 0C 00 20 00 B8 2D E3 05 03 01 02 3A 80 18 71 38 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 0E 1F 00 80 51 00 1E 30 40 80 37 00 40 84 63 00 00 1C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3B

- Adjustment Color Temperature(White balance) Using Instruments Color Analyzer: CA-210 (CH 10) - Using LCD color temperature, Color Analyzer (CA210) must use CH 10, which Matrix compensated (White, Red, Green, Blue compensation) with CS2100. See the Coordination bellowed one.  Auto-adjustment Equipment (It needs when Auto-adjustment It is availed communicate with RS-232C : Baud rate: 115200) V  ideo Signal Generator MSPG-925F 720p, 216Gray (Model: 217, Pattern 78) Connection Diagram (Auto Adjustment) Using Inner Pattern

Using HDMI input - South Centural America _2D_FHD HDMI 3 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0F 50 54 A1 08 00 31 40 45 40 61 40 81 80 D1 C0 01 01 01 01 01 01 1A 36 80 A0 70 38 1F 40 30 20 25 00 40 84 63 00 00 1A 66 21 50 B0 51 00 1B 30 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 D4 02 03 27 F1 4F 90 1F 04 13 05 14 03 02 12 20 22 15 11 16 01 26 15 07 50 09 57 07 67 03 0C 00 30 00 B8 2D E3 05 03 01 02 3A 80 18 71 38 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 0E 1F 00 80 51 00 1E 30 40 80 37 00 40 84 63 00 00 1C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2B - See Working Guide if you want more information about EDID communication. < connection Diagram for Adjustment White balance > White Balance Adjustment If you cant adjust with inner pattern, then you can adjust it using HDMI pattern. You can select option at Ez-Adjust Menu 7. White Balance there items NONE, INNER, HDMI. It is normally setting at inner basically. If you cant adjust using inner pattern you can select HDMI item, and you can adjust. In manual Adjust case, if you press ADJ button of service remocon, and enter Ez-Adjust Menu 7. White Balance, then automatically inner pattern operates. (In case of Inner originally Test-Pattern. On will be selected in The Test-Pattern. On/Off. Connect all cables and equipments like Pic.5) S  et Baud Rate of RS-232C to 115200. It may set 115200 orignally. Connect RS-232C cable to set Connect HDMI cable to set

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LGE Internal Use Only

 When Color temperature (White balance) Adjustment (Automatically) - Press Power only key of service remocon and operate automatically adjustment. - Set BaudRate to 115200. You must start wb 00 00 and finish it wb 00 ff. If it needs, then adjustment Offset. White Balance Adjustment (Manual adjustment) Test Equipment: CA-210 - Using PDP color temperature, Color Analyzer (CA-210) must use CH 10, which Matrix compensated (White, Red, Green, Blue compensation) with CS-2100. See the Coordination bellowed one. Manual adjustment sequence is like bellowed one. - Turn to Ez-Adjust mode with press ADJ button of service remocon. - Select 10.Test Pattern with CH+/- button and press enter. Then set will go on Heat-run mode. Over 30 minutes set let on Heat-run mode. - Let CA-210 to zero calibration and must has gap more 10cm from center of PDP module when adjustment. - Press ADJ button of service remocon and select 7.White-Balance in Ez-Adjust then press button of navigation key. (When press button then set will go to full white mode) - Adjust at three mode (Cool, Medium, Warm) - If cool mode Let B-Gain to 192 and R, G, B-Cut to 64 and then control  R, G gain adjustment High Light adjustment. - If Medium and Warm mode Let R-Gain to 192 and R, G, B-Cut to 64 and then control G, B gain adjustment High Light adjustment. - All of the three mode Let R-Gain to 192 and R, G, B-Cut to 64 and then control  G, B gain adjustment High Light adjustment. - With volume button (+/-) you can adjust. - After all adjustment finished, with Enter ( key) turn to Ez-Adjust mode. Then with ADJ button, exit from adjustment mode * Attachment: W  hite Balance adjustment coordination and color temperature. Using CS-1000 Equipment. - COOL : T=11000K, uv=0.000, x=0.276 y=0.283 - MEDIUM : T=9300K, uv=0.000, x=0.285 y=0.293 - WARM : T=6500K, uv=0.000, x=0.313 y=0.329

RS-232C Command (Commonly apply) RS-232C COMMAND [CMD ID DATA] wb wb wb wb wb wb 00 00 00 00 00 00 00 10 1f 20 2f ff Meaning White Balance adjustment start. Start of adjust gain (Inner white pattern) End of gain adjust Start of offset adjust (Inner white pattern) End of offset adjust End of White Balance adjust (Inner pattern disappeared) wb 00 00: Start Auto-adjustment of white balance. wb 00 10: Start Gain Adjustment (Inner pattern) jb 00 c0 : wb 00 1f: End of Adjustment * If it needs, offset adjustment (wb 00 20-start, wb 00 2fend)  wb 00 ff: End of white balance adjustment (inner pattern disappear) Adjustment Mapping information RS-232C COMMAND [CMD ID DATA] Cool R Gain G Gain B Gain R Cut G Cut B Cut jg jh ji Mid Ja Jb Jc Warm jd je jf 00 00 00 M I N CENTER (DEFAULT) Cool 184 187 192 64 64 64 Mid 192 183 161 64 64 64 Warm 192 159 95 64 64 64 192 192 192 127 127 127 M A X

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6. GND and ESD Testing


 When tester will measure on Cool condition, adjust W30 on TV display menu.

6.1. Prepare GND and ESD Testing.

Check the connection between set and power cord

6.2. Operate GND and ESD auto-test.


 When tester will measure on medium condition, adjust 0 on TV display menu.

 When tester will measure on warm condition, adjust W30 on TV display menu. Using CA-210 Equipment. (10 CH) Color temperature COOL MEDIUM WARM Item Min Typ Max Unit Remark cd/m - 100% Window White Pattern - 100IRE(255Gray) - Picture: Vivid(Medium) 49 60 +20 % - 85IRE(216Gray) 100% Window White Pattern - Picture: Vivid(Medium) Test Equipment CA-210 CA-210 CA-210 White average brightness Color Coordination x 0.276 0.002 0.285 0.002 0.313 0.002 y 0.283 0.002 0.293 0.002 0.329 0.002

 Fully connected (Between set and power cord) set enter the Auto-test sequence. Connect D-Jack AV jack test equipment. Turn on Auto-controller(GWS103-4) Start Auto GND test. If its result is NG, then notice with buzzer. If its result is OK, then automatically it turns to ESD Test. Operate ESD test If its result is NG, then notice with buzzer.  If its result is OK, then process next steps. Notice it with Good lamp and STOPER Down.

6.3. Check Items.

- Contrast value: 216 Gray Brightness uniformity -20

Test Voltage GND: 1.5KV/min at 100mA Signal: 3KV/min at 100mA Test time: just 1 second. Test point  GND test: Test between Power cord GND and Signal cable metal GND.  ESD test: Test between Power cord GND and Live and neutral. Leakage current: Set to 0.5mA(rms)

6.4. POWER PCB Assy Voltage adjustment


6.4.1. Test equipment : D.M.M 1EA 6.4.2. Connection Diagram for Measuring
: refer to fig.1 <XPOWER4 60R4 PSU> (Va, Vs voltage adjustment)

- Brightness spec.

5.3. Test of RS-232C control.

- Press In-Start button of Service Remocon then set the 4.Baud Rate to 115200. Then check RS-232C control and

5.4. Selection of Country option.

- Selection of country option is allowed only North American model (Not allowed Korean model). It is selection of Country about Rating and Time Zone.  Models: All models which PU11A Chassis (See the first page.)  Press In-Start button of Service Remocon, then enter the Option Menu with PIP CH- Button  Select one of these three (USA, CANADA, MEXICO) depends on its market using Vol. +/-button. * Caution :  Dont push The INSTOP KEY after completing the function inspection. * Caution : Inspection only PAL M / NTSC

(fig.1) PCB Assy Voltage adjustment

6.4.3. Adjustment method

6.4.3.1. Vs adjustment (refer fig.1) (1)  Connect + terminal of D.M.M. to Vs pin of P811, connect -terminal to GND pin of P811 (2)  After turning VR901, voltage of D.M.M adjustment as same as Vs voltage which on label of panel left/top ( deviation ; 0.5V) 6.4.3.2. Va adjustment (refer fig.1) (1) After receiving 100% Full White Pattern, HEAT RUN. (2)  Connect + terminal of D.M.M. to Va pin of P811, connect -terminal to GND pin of P811 (3)  After turning VR502,voltage of D.M.M adjustment as same as Va voltage which on label of panel left/top (deviation; 0.5V)
LGE Internal Use Only

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7. Default Service option.


7.1. ADC-Set.
R-Gain adjustment Value (default 128) G-Gain adjustment Value (default 128) B-Gain adjustment Value (default 128) R-Offset adjustment Value (default 128) G-Offset adjustment Value (default 128) B-Offset adjustment Value (default 128)

Select download file (epk file)

7.2. White balance. Value.


Center(Default) COOL R Gain G Gain B Gain R Cut G Cut B Cut 192 192 192 64 64 64 Mid 192 192 192 64 64 64 Warm 192 192 192 64 64 64

7.3. Temperature Threshold


Threshold Down Low Threshold Up Low Threshold Down High Threshold Up High 20 23 70 75

8. USB DOWNLOAD(*.epk file download)


Put the USB Stick to the USB socket Press Menu key, and move OPTION

After download is finished, remove the USB stick.  Press IN-START key of ADJ remote control, check the S/W version.

9. Tool option
Press FAV Press 7 times Tool option 1 Tool option 2 Tool option 3 Tool option 4 Tool option 5 Country code Country Group Country 60PA6500-SA 49344 39178 3697 51270 10 03 BR BR

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LGE Internal Use Only

BLOCK DIAGRAM

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LGE Internal Use Only

EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

300

310

303

304

305

208

209

520

601

540

301

580

206

201

200

302

204

205

207

202

203

501

240

590

120

LV1 910 900


- 13 LGE Internal Use Only

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400

A2

A10

A9

A12

+5V

Full SCART
+3.3V

MULTI E MMBT3906(NXP) Q103-*1 L103 120-ohm EU

EU JK100 PSC008-02
SHIELD 23 AV_DET 22 COM_GND 21 SYNC_IN 20 SYNC_OUT

R104 10K EU AV/SC1_DET R105 1K EU R129 0 EU SC1_SOG_IN AV/SC1_CVBS_IN R117 75 EU C109 27pF 50V EU C111 220pF 50V EU Q100 MMBT3904(NXP) EU E C C B R136 330 EU E

C R144 470 EU B Q103 ISA1530AC1 EU R146 18K EU C B E Q104 MMBT3904(NXP) EU R134 100 1/4W EU SC1_FB R135 0 EU R141 220 EU R142 390 READY EU KDS184 D112 A2 SC1_ID R114 10K EU R120 2.7K EU MULTI D112-*1 MMBD6100 A2 C A1 EU R155 3K E EU MMBT3904(NXP) Q106 EU C 12K R160 R143 180 EU C116 10uF 16V EU DTV/MNT_VOUT C117 0.1uF 16V READY

PDP GP4 LM1 EAX64280503

SC1_VOUT
5% 1/16W R113 75 EU R118 470K EU C106 100uF 16V EU R123 33 EU C110 1000pF 50V READY

19 SYNC_GND2 18 SYNC_GND1 17 RGB_IO 16 R_OUT 15 RGB_GND 14 R_GND 13 D2B_OUT 12 G_OUT 11 D2B_IN 10 G_GND 9 ID 8 B_OUT 7 AUDIO_L_IN 6 B_GND 5 AUDIO_GND 4 AUDIO_L_OUT 3 AUDIO_R_IN 2 AUDIO_R_OUT 1 R107 75 SC1_B+/COMP1_Pb+ R108 75 SC1_G+/COMP1_Y+ R106 75 SC1_R+/COMP1_Pr+

R147 10K EU

R119 75 EU

EU 1K R158 B SC_RE1 E EU 1K R157 SC_RE2

REC_8

C A1 E EU MMBT3904(NXP) B Q107 C

EU MMBT3904(NXP) B Q105 C EU 12K R159

AV/SC1_L_IN R115 470K EU C102 R121 1000pF 10K 50V EU READY R126 12K EU

EU 7.5K R156

AV/SC1_R_IN R116 470K EU C103 R124 1000pF 10K EU 50V READY R127 12K EU

P_17V IC101 AZ4580MTR-E1 P_17V


OUT1 1 8 VCC

R122 0 EU R125 0 EU

C107 5600pF 50V EU C108 5600pF 50V EU

R138 2K EU Q101 MMBT3904(NXP) EU

C113 10uF 16V EU

C114 27pF 50V EU R145 6.8K EU

R149 15K EU

IN1-

OUT2

R137 2K EU

IN1+ SCART1_Lout R154 5.6K EU VEE

IN2EU 5.6K R153

IN2+

SCART1_Rout

DTV_R_OUT
R139 2K EU Q102 MMBT3904(NXP) EU C112 10uF 16V EU

C115 27pF 50V EU

R148 15K EU

R152 6.8K EU

+3.3V_ST

EU R189 10K SCART1_MUTE

R140 2K EU

EU CI_OE AR105

33 /PCM_OE /PCM_WE /PCM_IORD /PCM_IOWR

CI SLOT

+5V_CI_ON

CI_WE CI_IORD CI_IOWR AR106 EU 33

C100 22uF 10V EU

C101 0.1uF 16V EU

CI_ADDR[12] CI_ADDR[13] CI_ADDR[14] REG

PCM_A[12] PCM_A[13] PCM_A[14] /PCM_REG EU BUF2_FE_TS_DATA[0-7] BUF2_FE_TS_DATA[0] AR108 33 EU BUF1_FE_TS_DATA[0] BUF1_FE_TS_DATA[1] BUF1_FE_TS_DATA[2] BUF1_FE_TS_DATA[3]

+5V

BUF2_FE_TS_DATA[1] 33 PCM_A[8] PCM_A[9] PCM_A[10] PCM_A[11] BUF2_FE_TS_DATA[2] BUF2_FE_TS_DATA[3]

R151 10K EU /CI_CD1 CI_TS_DATA[4] CI_TS_DATA[5] CI_TS_DATA[6] CI_TS_DATA[7] AR100

R102 100 EU EU

JK102 10067972-000LF EU 35
36 37 33 38 39 40 41 42 R111 10K EU 43 44 45 46 47 48 49 READY R112 0 50 51 52 53 54 R109 10K EU 55 56 57 58 59 60 61 62 63 R110 0 READY 64 65 66 67 68 2 G2 69 G1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 R128 READY 0 EU

CI_ADDR[8] CI_ADDR[9] AR103 33 PCM_D[3] PCM_D[4] PCM_D[5] PCM_D[6] PCM_D[7] R130 33 EU 1/16W R1315% 33 EU R133 10K EU /PCM_CE CI_ADDR[10] CI_ADDR[11]

AR107

AR109 33 EU BUF2_FE_TS_DATA[4] BUF1_FE_TS_DATA[4] BUF2_FE_TS_DATA[5] BUF1_FE_TS_DATA[5] BUF1_FE_TS_DATA[6] BUF1_FE_TS_DATA[7] BUF2_FE_TS_DATA[6] BUF2_FE_TS_DATA[7]

+3.3V_CI +3.3V_CI
EU R165 10K

BUF1_FE_TS_DATA[0-7]

BUF1_FE_TS_DATA[0-7] CI_ADDR[10] CI_ADDR[11] CI_ADDR[9] CI_ADDR[8] CI_ADDR[13] CI_ADDR[14] CI_WE CI_DET PCM_A[0] CI_ADDR[7]
1A2 1OE 1

CI_OE

CI_IORD CI_IOWR BUF2_FE_TS_SYN BUF2_FE_TS_DATA[0-7] BUF2_FE_TS_DATA[0] BUF2_FE_TS_DATA[1] BUF2_FE_TS_DATA[2] BUF2_FE_TS_DATA[3]

IC100 TC74LCX244FT
20 VCC

EU C105 0.1uF 16V

AR110 33 BUF1_FE_TS_SYN BUF1_FE_TS_VAL_ERR BUF1_FE_TS_CLK

EU

BUF2_FE_TS_SYN BUF2_FE_TS_VAL_ERR BUF2_FE_TS_CLK

EU

1A1

19

2OE

2Y4

18

1Y1

CI_ADDR[0]
2A4

R132

100 EU

PCM_A[1]
2Y3

17

PCM_A[7]
1Y2

/PCM_IRQA

CI_ADDR[6]
1A3

16

CI_ADDR[1]
2A3

PCM_A[2]
2Y2

15

PCM_A[6]
1Y3

CI_ADDR[5] BUF2_FE_TS_VAL_ERR BUF2_FE_TS_CLK CI_ADDR[12] CI_ADDR[7] CI_ADDR[6] CI_ADDR[5] CI_ADDR[4] CI_ADDR[3] CI_ADDR[2]
1A4

14

CI_ADDR[2]
2A2

BUF2_FE_TS_DATA[4] BUF2_FE_TS_DATA[5] BUF2_FE_TS_DATA[6] BUF2_FE_TS_DATA[7] PCM_RST /PCM_WAIT REG CI_TS_CLK CI_TS_VAL CI_TS_SYNC AR102 33 EU AR101 33 EU R100 EU 33 R101 EU 33

PCM_A[3]
2Y1

13

PCM_A[5]
1Y4

CI_ADDR[4]
GND

12

CI_ADDR[3]
2A1

10

11

PCM_A[4]

CI POWER ENABLE CONTROL


+5V Q114 RSR025P03 EU D L100 120-ohm EU +5V_CI_ON

BUF2_FE_TS_DATA[0-7]

5% 1/16W

CI_ADDR[1] EU AR104 33 CI_ADDR[0] PCM_D[0] PCM_D[1] PCM_D[2] CI_ADDR[0-14]

R184 10K READY

R187 10K EU

C131 0.1uF 16V READY

C104 0.1uF 16V EU

R198 10K READY

AO3407A S D R188 2K EU C PCM_D[0-7] PCM_5V_CTL PCM_D[0-7] B R181 10K EU

3.3V_CI
+3.3V +3.3V_CI

CI_TS_DATA[0] CI_TS_DATA[1] CI_TS_DATA[2] CI_TS_DATA[3] R150 10K EU +5V /CI_CD2

MULTI Q114-*1 Q113 MMBT3904(NXP) EU

R103 100 EU

L101 120-ohm EU

C136 0.1uF 16V READY

C137 0.1uF 16V EU

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

GP4_S7LR SCART,CI Slot

2011-10-20 1 6

LGE Internal Use Only

SPDIF HDMI_1
5V_HDMI_1 +5V SHIELD 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CK+ D0D0_GND D0+ D0+_HDMI1 D1D1-_HDMI1 D1_GND D1+ D1+_HDMI1 D2D2-_HDMI1 D2_GND D2+ D2+_HDMI1 2 1 3 5 4 6 JP202 R208 33 HDMI_1 R281 10K HDMI_1 5V_DET_HDMI_1 C B JP201 R201 1.8K HDMI_1 Q200 MMBT3904(NXP) HDMI_1 E R204 3.3K HDMI_1 R207 R282 33 10K HDMI_1 HDMI_1 R202 10K HDMI_1 R217 10K HDMI_1

SIDE_HDMI_1
5V_HDMI_2 +5V BODY_SHIELD 20 19 18 17 16 15
20

SIDE_HDMI_2
5V_HDMI_3 +5V

JK204 JST1223-001 1 GND

MULTI JK204-*1 2F01TC1-CLM97-4F 1 Fiber Optic GND

JK200-*1 YKF45-7058V HDMI1_NON Screw DATA2+ 1 DATA2_SHIELD DATA2DATA1+ DATA1_SHIELD 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

R200 1K HDMI_1

R226 1K SIDE_HDMI_1

5V_DET_HDMI_2 C B JP204 R203 10K SIDE_HDMI_1 HPD2

BODY_SHIELD 20 19 18 17 DDC_SDA_2 DDC_SCL_2 16 15 14 CEC_REMOTE CK-_HDMI2 13 12 11 10 9 8 D0+_HDMI2 7 6 5 D1+_HDMI2 4 3 2 D2+_HDMI2 1 CK+

5V_DET_HDMI_3 R240 1K SIDE_HDMI_2

Fiber Optic

For CEC
+3.3V_ST C B JP207 Q202 R241 MMBT3904(NXP) 1.8K SIDE_HDMI_2 SIDE_HDMI_2 R288 10K SIDE_HDMI_2 R209 10K SIDE_HDMI_2 HPD3 R260 56K READY

+5V

VCC C219 0.1uF 16V R285 100 SPDIF_OUT C220 10pF 50V

VCC

HPD1

DATA1DATA0+

DATA0_SHIELD DATA0CLK+ CLK_SHIELD CLKCEC NC SCL

R286 10K SIDE_HDMI_1

FIX_POLE

DDC_SDA_1 DDC_SCL_1 HDMI_ARC CEC_REMOTE CK-_HDMI1

SDA DDC/CEC_GND +5V_POWER HPD

JP205

SHIELD

14 13 12 11 10 9 8 7 CK+

JP208

R232 33 SIDE_HDMI_1

R246 33 SIDE_HDMI_2

DDC_SCL_3

R261 0 READY

CEC_REMOTE CK-_HDMI3

CEC_REMOTE

D224 MMBD301LT1G 30V READY R268 100

CEC_REMOTE_S7

S
D222 READY

SIDE USB
Q203 BSS83
READY

PEN_TOUCH +5V_ST D225 B140A 40V

1A SPEC
IC207 AP2337SA-7 VOUT

PEN_TOUCH VIN 3 1 GND

+3.3V

SWITCH ADDED
IC204 AP2191SG-13

SHIELD

R269 27K READY

R227 1.8K SIDE_HDMI_1

Q201 MMBT3904(NXP) SIDE_HDMI_1 E R230 3.3K R231 R287 SIDE_HDMI_1 33 10K SIDE_HDMI_1 SIDE_HDMI_1

R237 10K SIDE_HDMI_1

R250 10K SIDE_HDMI_2 E R244 3.3K R289 SIDE_HDMI_2 R245 10K 33 SIDE_HDMI_2 SIDE_HDMI_2 DDC_SDA_3

VINPUT

VIN

+3.3V +5V +5V_ST

CK+_HDMI1 D0-_HDMI1

CK+_HDMI2 D0D0-_HDMI2 D0_GND D0+ D1D1-_HDMI2 D1_GND D1+ D2D2-_HDMI2 D2_GND D2+

CK+_HDMI3 D0D0-_HDMI3 D0_GND

G
D0+ D0+_HDMI3 D1D1-_HDMI3 1 D1_GND USB DOWN STREAM D1+ D1+_HDMI3 D2D2-_HDMI3 D2_GND D2+ D2+_HDMI3

Capacitors on VBUSA should be placed as closd to connector as possible.

R264 10K

NC

GND

R270 10K

R243 0

OUT_2

JK209 3AU04S-305-ZC-(LG)

IN_1

R247 0 READY

$0.11 C212 0.1uF 16V C213 10uF 10V USB1_OCD


OUT_1 6 3 IN_2

R258 33

FLG

EN

R271 33

USB1_CTL

SIDE_USB_DM

SIDE_USB_DP

JK200 HDMI_1

JK201 SIDE_HDMI_1

JK202 SIDE_HDMI_2

10mm

JK211 PPJ239-01 NON_EU 6H 5H 4H 5G 4F 5F 7F 5E 7E 4D 5D 6D 6N 5N 4N 5M 5L 7L 5K 7K 4J 5J 6J [RD1]E-LUG

COMPONENT2

RS232C
JK203 SPG09-DB-009

+3.3V_ST
R283 R284 0 0

S7_TXD S7_RXD PM_TXD PM_RXD

ETHERNET
+3.3V_ST
C229 0.1uF 16V
JK210 XRJV-01V-0-D12-080

1/16W 5%

[RD1]O-SPRING_2 [RD1]CONTACT_2
R299 0

JK208 PPJ234-02 EU 6A [GN]O-SPRING 5A [GN]CONTACT 4A [BL]E-LUG-S 7B [BL]O-SPRING R252 75 COMP2_Pb+ 5B [RD]E-LUG-S 7C R253 75 [RD]O-SPRING_1 5C [RD]CONTACT_1 4C COMP2_Pr+ 5 10 R267 1K 4 9 Q204 MMBT3904(NXP) USA E R256 10K 5D 4E 5E [WH]O-SPRING [RD]CONTACT_2 [RD]O-SPRING_2 [RD]E-LUG R255 470K R254 470K R257 10K R263 12K R262 12K COMP2_R_IN COMP2_L_IN C R265 10K AV2_DET 3 8 [GN]E-LUG R251 75 COMP2_Y+

R278 10K

R279 10K VCC

IC206 MAX3232CDR
16 1 C1+ C228 0.1uF 16V C225 0.1uF 16V

+2.5V

+3.3V
R259 10K

1 6 R276 100 R266 1K 2 COMP2_DET 7 +5V_ST R277 100

JK210-*1

TP
2

BS-R430051

GND

15

V+

R296 10K READY

1 ET_NET_UDE

TN
4

[WH1]O-SPRING [RD1]CONTACT_1 [RD1]O-SPRING_1 [RD1]E-LUG-S [BL1]O-SPRING [BL1]E-LUG-S [GN1]CONTACT [GN1]O-SPRING [GN1]E-LUG [RD2]E-LUG
6

DOUT1

14

C1-

RP
5

R228 10K USA TX R229 100K USA B R233 100K USA

RIN1

13

C2+ C226 0.1uF 16V

ET_NET 5

ROUT1

12

C2-

RN
7

8 9

DIN1

11

V8 8

C200 0.1uF 16V ET_NET

D200 D204 5.6V 5.6V ET_NET ET_NET

D205 5.6V ET_NET

D206 5.6V ET_NET

DIN2 R274 0 NON_RGB PC_SER_DATA R275 0 NON_RGB PC_SER_CLK ROUT2

10

DOUT2
9 9

RIN2

C227 0.1uF 16V

R273 0 ET_NET R280 0 ET_NET

R291 0 ET_NET R290 0 ET_NET

6E

RGB PC
JK205 SPG09-DB-010
+5V_ST

PC AUDIO
JK207 PEJ027-04 USA JK206 PEJ027-04 3 6A DSUB_R+ 7A R215 75 R205 33 R216 75 RGB_DDC_SDA DSUB_G+ DSUB_HSYNC DSUB_B+ 7B C202 10pF 50V C203 10pF 50V DSUB_VSYNC R224 10K R225 1K DSUB_DET RGB_DDC_SCL PC_SER_DATA R212 10 PC_SER_CLK 6B 4 5 E_SPRING 7A T_TERMINAL1 4 B_TERMINAL1 R_SPRING T_SPRING 6B B_TERMINAL2 T_TERMINAL2 R221 10K PC_L_IN R219 470K R223 12K R220 10K PC_R_IN R218 470K 1/16W 5% R222 12K 5 7B 3 6A E_SPRING T_TERMINAL1 IR B_TERMINAL1 R_SPRING T_SPRING B_TERMINAL2 TX T_TERMINAL2 R210 10 USA

R297 10K RED_GND GND_2

R298 10K

[RD2]O-SPRING_2
NON_EU

NON_EU R234 10K NON_EU R235 470K R236 12K

1
COMP1_R_IN

11 7 12 8

RED GREEN_GND DDC_DATA GREEN BLUE_GND H_SYNC

R214 75

R213 0 NON_USA

[RD2]CONTACT [WH2]O-SPRING [RD2]O-SPRING_1

NON_EU R239 10K NON_EU NON_EU R238 470K R242 12K COMP1_L_IN

3 9 4 10 5
SC1_R+/COMP1_Pr+

13

BLUE NC V_SYNC R206 33

+3.3V

14

GND_1 SYNC_GND DDC_CLOCK

15

DDC_GND

[RD2]E-LUG-S [BL2]O-SPRING
SC1_B+/COMP1_Pb+

16
SHILED

R211 10

GND

[BL2]E-LUG-S
+3.3V

[GN2]CONTACT [GN2]O-SPRING

NON_EU R248 10K

NON_EU R249 1K COMP1_DET

SC1_G+/COMP1_Y+

[GN2]E-LUG

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

GP4_S7LR
JACK INTERFACE

2011-10-20 2 6

LGE Internal Use Only

TUNER
TUNER TDSS-G101D TDSS-H101F TDSH-T101F TDSN_B001F TDSN_G201D OPT1 DVB-T/C ATSC OPT2 HNIM HNIM OPT3 X X RF_SW RF_SW X
RF_SWITCH R310 1K FE_TS_DATA[0-7]

BUF1_FE_TS_DATA[0-7] AR300 FNIM 33 FE_TS_DATA[0] BUF1_FE_TS_DATA[0] BUF1_FE_TS_DATA[1] FE_TS_DATA[1] FE_TS_DATA[2] FE_TS_DATA[3] BUF1_FE_TS_DATA[2] BUF1_FE_TS_DATA[3]

AR301 FNIM 33 BUF1_FE_TS_DATA[4] FE_TS_DATA[4] FE_TS_DATA[5] FE_TS_DATA[6] FE_TS_DATA[7] AR302 33 FE_TS_SYN FE_TS_VAL_ERR FE_TS_CLK BUF1_FE_TS_DATA[5] BUF1_FE_TS_DATA[6] BUF1_FE_TS_DATA[7] FNIM BUF1_FE_TS_SYN BUF1_FE_TS_VAL_ERR BUF1_FE_TS_CLK

DVB-T_SCA HNIM SBTVD DVB_T2 FNIM FNIM

RF_SWITCH_CTL C307 0.1uF 16V RF_SWITCH

Close to Tuner Pin TU304 TDSN-G301D


DVB_T2 1 2 3 4 5 6 7 8 9 10 11 NC_1 RESET SCL SDA +B1[3.3V] SIF +B2[1.8V] CVBS +B3[2.5V] NC_2 NC_3 +B4[3.3V] +B5[1.23V] NC_4 GND ERROR SYNC VALID MCLK D0 D1 D2 D3 D4 D5 D6 D7 28 SHIELD SBTVD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 RF_S/W_CTL RESET SCL SDA +B1[3.3V] SIF +B2[1.8V] CVBS NC_1 NC_2 NC_3 +B3[3.3V] +B4[1.23V] NC_4 GND ERROR SYNC FE_TS_SYN VALID FE_TS_VAL_ERR MCLK D0 D1 D2 D3 D4 D5 D6 D7 FE_TS_CLK FE_TS_DATA[0] FE_TS_DATA[1] FE_TS_DATA[2] FE_TS_DATA[3] FE_TS_DATA[4] FE_TS_DATA[5] FE_TS_DATA[6] FE_TS_DATA[7] TU_CVBS FE_TS_DATA[0-7] READY R300 0 12 SHIELD 12 SHIELD 12 SHIELD R316 470 C308 0.1uF 16V R312 4.7K B E MMBT3906(NXP) Q301 C R317 82 TU_SIF

TU303 TDSN_B001F
DVB_T/C

TU302 TDSS-G101D ATSC 1 2 3 4 5 6 7 8 9 10 11 NC RESET SCL SDA +3.3V SIF +1.8V CVBS IF_AGC DIF[P] DIF[N]

TU301 TDSS-H101F

TU300 TDSH-T101F DVB_T_SCA

+3.3V_TU

+3.3V_TU

+1.8V_TU

+2.5V_TU

1 2 3 4 5 6 7 8 9 10 11

NC RESET SCL SDA +B1[3.3V] SIF +B2[1.8V] CVBS IF_AGC DIF[P] DIF[N]

1 2 3 4 5 6 7 8 9 10 11

RF_S/W_CTL RESET SCL SDA +B1[3.3V] SIF +B2[1.8V] CVBS IF_AGC DIF[P] DIF[N] C302 0.1uF 16V C303 10uF 16V 16V 0.1uF C310 C304 68pF 50V

R308 R301 2.2K 100 R307 22

R309 2.2K

R311 10K TUNER_RESET

TU_SCL TU_SDA

R306 22 C305 68pF 50V

C311 0.1uF 16V

DVB_T2 0 HNIM 0 HNIM 0 HNIM 0

R302 R303 IF_AGC_MAIN R304 R305 IF_P_MSTAR IF_N_MSTAR

Close to Tuner Pin


READY R313 0 +5V

+1.25V_TU
C300 10uF 6.3V FNIM

12 13 C301 0.1uF 16V FNIM 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SHIELD

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
TUNER

Tuner block

6
LGE Internal Use Only

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

VIDEO/AUDIO
IC400-*1 LGE2111A-TE
C7 E6 F5 B6 E5 D5 B7 E7 F7 AB5 AB3 A9 F4 AB1 N6 AB2 AC2 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO45 GPIO46 GPIO49 GPIO50 GPIO51 GPIO52 I2C_SCKM0/GPIO53 I2C_SDAM0/GPIO54 GPIO73 GPIO74 Dvix only LVB0P LVB0N LVB1P LVB1N LVB2P LVB2N LVB3P LVB3N LVB4P LVB4N LVA0P LVA0N LVA1P LVA1N LVA2P LVA2N LVA3P LVA3N LVA4P LVA4N V23 U24 V25 V24 W25 W23 AA23 Y24 AA25 AA24 AB25 AB23 AC25 AB24 AD25 AC24 AE23 AC23 AC22 AD23

IC400 LGE2111A-T8

R450 100 C451 HNIM


AC4 VIFP VIFM AC3 IP IM AD4 SIFP SIFM AC5 AE3 AD3

HNIM 0.1uF HNIM 0.1uF

IC400 LGE2111A-T8
READY HNIM C456 C459 100pF 100pF 50V 50V C460 100pF 50V HNIM PCM_D[0-7] IF_P_MSTAR PCM_D[0] PCM_D[1] PCM_D[2] PCM_D[3] PCM_D[4] PCM_D[5] PCM_D[6] PCM_D[7] PCM_A[0] PCM_A[1] PCM_A[2] PCM_A[3] PCM_A[4] PCM_A[5] PCM_A[6] PCM_A[7] PCM_A[8] PCM_A[9] PCM_A[10] PCM_A[11] PCM_A[12] PCM_A[13] PCM_A[14] /PCM_REG +5V /PCM_OE /PCM_WE /PCM_IORD R476 /PCM_IOWR 10K EU /PCM_CE
W21 AA18 AB22 AE20 AA15 AE21 AB21 Y15 W20 V20 W22 AB18 AA20 AA21 Y19 AB17 Y16 AB19 AB20 AA16 AA19 AC21 AA17 Y20 PCMREG_N/GPIO123 AB15 AA22 AD22 AD20 AD21 AC20 Y18 Y21 PCMCE_N/GPIO115 PCMIRQA_N/GPIO105 PCMCD_N/GPIO130 PCMWAIT_N/GPIO100 PCM_RESET/GPIO129 Y14 U21 V21 R20 T20 U22 PCM2_CE_N/GPIO131 PCM2_IRQA_N/GPIO132 PCM2_CD_N/GPIO135 PCM2_WAIT_N/GPIO133 PCM2_RESET/GPIO134 TS0DATA_[0]/GPIO77 TS0DATA_[1]/GPIO78 TS0DATA_[2]/GPIO79 UART1_TX/GPIO43 UART1_RX/GPIO44 UART2_TX/GPIO65 UART2_RX/GPIO64 UART3_TX/GPIO47 UART3_RX/GPIO48 TS0DATA_[3]/GPIO80 TS0DATA_[4]/GPIO81 TS0DATA_[5]/GPIO82 TS0DATA_[6]/GPIO83 TS0DATA_[7]/GPIO84 AC15 TS1CLK/GPIO98 I2C_SCKM2/DDCR_CK/GPIO72 I2C_SDAM2/DDCR_DA/GPIO71 D2 D1 DDCA_DA/UART0_TX DDCA_CK/UART0_RX TS1DATA_[0]/GPIO88 TS1DATA_[1]/GPIO89 TS1DATA_[2]/GPIO90 TS1DATA_[3]/GPIO91 PWM0/GPIO66 PWM1/GPIO67 PWM2/GPIO68 PWM3/GPIO69 PWM4/GPIO70 PWM_PM/GPIO199 TS1DATA_[4]/GPIO92 TS1DATA_[5]/GPIO93 TS1DATA_[6]/GPIO94 TS1DATA_[7]/GPIO95 TS1VALID/GPI96 TS1SYNC/GPIO97 AD16 AE15 AE14 AC13 AC14 AD12 AD13 AD14 AD15 AC16 TS0CLK/GPIO87 TS0VALID/GPIO85 TS0SYNC/GPIO86 Y13 Y11 AA12 AB12 AA14 AB14 AA13 AB11 AA10 Y12 PCMOE_N/GPIO113 PCMWE_N/GPIO197 PCMIORD_N/GPIO111 PCMIOWR_N/GPIO109 PM_SPI_SCK/GPIO1 PM_SPI_CZ0/GPIO_PM[12]/GPIO0 PM_SPI_SDI/GPIO2 PM_SPI_SDO/GPIO3 PCMADR[0]/GPIO125 PCMADR[1]/GPIO124 PCMADR[2]/GPIO122 PCMADR[3]/GPIO121 PCMADR[4]/GPIO99 PCMADR[5]/GPIO101 PCMADR[6]/GPIO102 PCMADR[7]/GPIO103 PCMADR[8]/GPIO108 PCMADR[9]/GPIO110 PCMADR[10]/GPIO114 PCMADR[11]/GPIO112 PCMADR[12]/GPIO104 PCMADR[13]/GPIO107 PCMADR[14]/GPIO106 GPIO_PM[0]/GPIO6 PM_UART_TX/GPIO_PM[1]/GPIO7 GPIO_PM[2]/GPIO8 GPIO_PM[3]/GPIO9 GPIO_PM[4]/GPIO10 PM_UART_RX/GPIO_PM[5]/GPIO11 PM_SPI_SCZ1/GPIO_PM[6]/GPIO12 GPIO_PM[7]/GPIO13 GPIO_PM[8]/GPIO14 GPIO_PM[9]/GPIO15 PM_SPI_SCZ2/GPIO_PM[10]/GPIO16 GPIO_PM[11]/GPIO17 A2 D3 B2 B1 H5 K6 K5 J6 K4 L6 C2 L5 M6 M5 C1 M4 PCMDATA[0]/GPIO126 PCMDATA[1]/GPIO127 PCMDATA[2]/GPIO128 PCMDATA[3]/GPIO120 PCMDATA[4]/GPIO119 PCMDATA[5]/GPIO118 PCMDATA[6]/GPIO117 PCMDATA[7]/GPIO116 NF_CE1Z/GPIO138 NF_WPZ/GPIO198 NF_CEZ/GPIO137 NF_CLE/GPIO136 NF_REZ/GPIO139 NF_WEZ/GPIO140 NF_ALE/GPIO141 NF_RBZ/GPIO142 AE18 AC17 AD18 AC18 AC19 AD17 AE17 AD19 1/16W AR400 22 1/16W AR401 22

LVDS
C7 E6 F5 B6 E5 D5 B7 E7 F7 AB5 AB3 A9 F4 AB1 N6 USB1_OCD SCART1_MUTE /FLASH_WP ERROR_DET USB1_CTL MODEL_OPT_3 READY R487 R432 22 R489 33 R490 33 SPI_SCK /SPI_CS SPI_SDI SPI_SDO AB2 AC2

IC400 LGE2111A-T8

CK+_HDMI2 CK-_HDMI2 D0+_HDMI2 D0-_HDMI2 D1+_HDMI2 D1-_HDMI2 D2+_HDMI2 D2-_HDMI2 DDC_SDA_2 DDC_SCL_2 HPD2

J2 J3 K3 J1 K2 K1 L2 L3 T5 T4 V5 RXACKP RXACKN RXA0P RXA0N RXA1P RXA1N RXA2P RXA2N DDCDA_DA/GPIO24 DDCDA_CK/GPIO23 HOTPLUGA/GPIO19

R451 HNIM C432 C433

C452 100 0.1uF 0.1uF

IF_N_MSTAR PCM_A[0-14] TU_SIF

5V_DET_HDMI_1 5V_DET_HDMI_2 5V_DET_HDMI_3 /PF_WP /PF_CE0 /PF_CE1 /PF_OE /PF_WE PF_ALE /F_RB COMP1_DET AV/SC1_DET AMP_RESET_N TUNER_RESET PCM_5V_CTL AMP_SCL AMP_SDA 100 R449 MODEL_OPT_1 AC_DET PM_TXD DISP_EN 5V_ON RL_ON PM_RXD RF_SWITCH_CTL

AB25 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO45 GPIO46 GPIO49 GPIO50 GPIO51 GPIO52 I2C_SCKM0/GPIO53 I2C_SDAM0/GPIO54 GPIO73 GPIO74 LVB0P LVB0N LVB1P LVB1N LVB2P LVB2N LVB3P LVB3N LVB4P LVB4N AE24 LVACKP LVACKN LVBCKP LVBCKN AD24 Y23 W24 T25 GPIO196 RXA2RXA2+ RXB2RXB2+ LVA0P LVA0N LVA1P LVA1N LVA2P LVA2N LVA3P LVA3N LVA4P LVA4N V23 U24 V25 V24 W25 W23 AA23 Y24 AA25 AA24 RXB4RXB4+ RXB3RXB3+ RXBCKRXBCK+ RXB1RXB1+ RXB0RXB0+ AB23 AC25 AB24 AD25 AC24 AE23 AC23 AC22 AD23 RXA4RXA4+ RXA3RXA3+ RXACKRXACK+ RXA1RXA1+ RXA0RXA0+

R464 R465

47 47 +3.3V

R446

10K

L400 120-ohm Main HNIM

C457 1000pF 50V READY

HNIM R452 AD2


IF_AGC RF_AGC AE2

AE6
AE24 LVACKP LVACKN LVBCKP LVBCKN T25 GPIO196 GPIO193 GPIO194 GPIO195 U23 T24 T23 AD24 Y23 W24

I2C_SCKM1/GPIO75 I2C_SDAM1/GPIO76

AD6

0 HNIM C435 R437 0.1uF 0 HNIM READY TU_SCL TU_SDA +3.3V R466 3.3K 22 100 R468 3.3K

R497 C450 100pF 50V HNIM C1612 0.047uF 25V HNIM

100 C1613 0.1uF HNIM

IF_AGC_MAIN

HNIM

R438 1K R486 100

AD1 XIN R5 XOUT HOTPLUGB/GPIO20 AE9 AC9 AC10 AD9 AC11 AD10 AE11 AD11 AE8 AD8 AC8 F2 F3 G3 F1 G2 G1 H2 H3 R6 U6 P5 R4 RXDCKP RXDCKN RXD0P RXD0N RXD1P RXD1N RXD2P RXD2N DDCDD_DA/GPIO30 DDCDD_CK/GPIO29 HOTPLUGD/GPIO22 CEC/GPIO5 AUL0 AUR0 HSYNC0 VSYNC0 RIN0P RIN0M GIN0P GIN0M BIN0P BIN0M SOGIN0 AUL1 AUR1 AUL2 AUR2 AUL3 AUR3 AUL4 AUR4 AB9 AA11 Y9 AA9 AA7 AB8 Y8 Y10 AC7 AD7 I2S_OUT_WS/GPIO155 C10 I2S_OUT_BCK/GPIO156 I2S_OUT_MCK/GPIO154 I2S_OUT_SD/GPIO157 RXCCKP RXCCKN RXC0P RXC0N RXC1P RXC1N RXC2P RXC2N DDCDC_DA/GPIO28 DDCDC_CK/GPIO27 HOTPLUGC/GPIO21 I2S_IN_BCK/GPIO150 I2S_IN_SD/GPIO151 I2S_IN_WS/GPIO149 B10 C9 B9 USB1_DM USB1_DP USB0_DM USB0_DP AC12 AE12 E3 SPDIF_IN/GPIO152 SPDIF_OUT/GPIO153 D7 D6 AC1

C447 GND_2 P_SDA SPDIF_OUT R441 1M X-TAL_1 1 2 X-TAL_2 C448 X400 24MHz GND_1 4 3

5pF 5pF

SC_RE1 CK+_HDMI3 CK-_HDMI3 D0+_HDMI3 D0-_HDMI3 D1+_HDMI3 D1-_HDMI3 D2+_HDMI3 D2-_HDMI3 DDC_SDA_3 DDC_SCL_3 HPD3 CK+_HDMI1 CK-_HDMI1 D0+_HDMI1 D0-_HDMI1 D1+_HDMI1 D1-_HDMI1 D2+_HDMI1 D2-_HDMI1 DDC_SDA_1 DDC_SCL_1 HPD1 CEC_REMOTE_S7 R404 R405 R406 R407 R408 R409 R410 R411 R412 22 22 33 68 33 68 33 68 0

R461 R488

SIDE_USB_DM SIDE_USB_DP

/PCM_IRQA /PCM_WAIT

EU

E2

R473 10K

33

C8 D8 D9

R462

22

SUB_SDA SUB_SCL P_SCL AUD_SCK AUD_MASTER_CLK AUD_LRCH +3.3V AUD_LRCK C437 C438 EU 2.2uF 2.2uF R471 2.2K

C461 C462 0.1uF 0.1uF READY EU 16V 16V

PCM_RST /CI_CD1 /CI_CD2

Y22

22 EU R458 22 R459 EU

CI_TS_CLK CI_TS_VAL CI_TS_SYNC CI_TS_DATA[0] CI_TS_DATA[1] CI_TS_DATA[2] CI_TS_DATA[3] CI_TS_DATA[4] CI_TS_DATA[5] CI_TS_DATA[6] CI_TS_DATA[7] BUF1_FE_TS_CLK BUF1_FE_TS_VAL_ERR BUF1_FE_TS_SYN BUF1_FE_TS_DATA[0] BUF1_FE_TS_DATA[1] BUF1_FE_TS_DATA[2] BUF1_FE_TS_DATA[3] BUF1_FE_TS_DATA[4] BUF1_FE_TS_DATA[5] BUF1_FE_TS_DATA[6] BUF1_FE_TS_DATA[7]

CI_TS_DATA[0-7]

U23 T24 T23

GPIO193 GPIO194 GPIO195

DSUB_HSYNC DSUB_VSYNC DSUB_R+ DSUB_G+ DSUB_B+ R400 10K SC1_ID SC1_FB SC1_R+/COMP1_Pr+ SC1_G+/COMP1_Y+ SC1_B+/COMP1_Pb+ SC1_SOG_IN R403 2.4K

P2 R3

AV/SC1_L_IN AV/SC1_R_IN

R472 2.2K

UART_TXD UART_RXD S7_TXD S7_RXD

22 22 R481 R482

R479 R480 22 22

D4 E4 N25 N24 B8 A8

EU NON_EU C472 NON_EU C478 C443 C444 C445 C446 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF COMP1_L_IN COMP1_R_IN COMP2_L_IN COMP2_R_IN PC_L_IN PC_R_IN I2C_SCL I2C_SDA RGB_DDC_SDA RGB_DDC_SCL

C401 C402 C403 C404 C405 C406 C407

0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 1000pF

N2 P3 N3 N1 M3 M2 M1

R477 R478 R469 R470

22 22 22 22

P23 P24

BUF1_FE_TS_DATA[0-7]

V2 V3 HSYNC1 VSYNC1 RIN1P RIN1M GIN1P GIN1M BIN1P BIN1M SOGIN1 AUOUTL0 AUOUTL2 AUOUTL3 AUOUTR0 AUOUTR2 AUOUTR3 W6 V6 V4 Y7 W5 U5

R413 R414 R415 R416 R417 R418

33 68 33 68 33 68

C408 C409 C410 C411 C412 C413 C414

0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 1000pF

U3 U2 T1 T2 R2 R1 T3

EU R442 SCART1_Lout 100 EU SCART1_Rout R444 100

PWM0 PWM1 COMP2_DET SC_RE2 LED_RED KEY1 KEY2 TOUCH_VER_CHK AMP_MUTE

P21 N23 P22 R21 P20 F6

POWER
K12

IC400 LGE2111A-T8
G10 AVDDLV_USB G9 H9 K10 VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 AVDD1P0 FB_CORE AVDDL_MOD AVDD10_LAN DVDD_DDR GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 W9 W10 W11 W12 Y17 AVDD25_LAN V18 AVDD2P5_ADC_1 AVDD2P5_ADC_2 AVDD2P5_ADC_3 AVDD25_REF GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 AVDD_MOD_1 AVDD_MOD_2 GND_64 GND_65 GND_66 W14 GND_67 AVDD25_PGA AVSS_PGA GND_68 GND_69 GND_70 AVDD_NODIE L7 AVDD_DVI_USB_1 AVDD_DVI_USB_2 AVDD3P3_MPLL AVDD_DMPLL GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 DVDD_NODIE GND_78 GND_79 AVDD_AU33 AVDD_EAR33 GND_80 GND_81 GND_82 VDDP_1 VDDP_2 GND_83 GND_84 GND_85 AVDD_LPLL_1 AVDD_LPLL_2 V19 VDDP_NAND GND_86 GND_87 GND_88 GND_89 GND_90 J17 K15 K16 L15 AVDD_DDR0_D_1 AVDD_DDR0_D_2 AVDD_DDR0_D_3 AVDD_DDR0_C K17 AVDD_DDR1_D_1 AVDD_DDR1_D_2 AVDD_DDR1_D_3 AVDD_DDR1_C GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99 GND_100 GND_101 E9 GND_EFUSE GND_102 GND_103 GND_104 A23 B17 C23 A5 C11 C19 C22 D14 D18 D19 E17 E18 E19 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 G11 G12 G13 G14 G17 G18 G19 G24 H11 H12 H13 H14 H15 H16 H17 H18 H19 J9 J10 J11 J12 J13 J14 J15 J16 J18 J19 J25 K9 K13 K14 H10 K18 K19 K22 L8 L9 J8 L12 L13 L18 L19 M8 K8 M10 M11 L14 M15 M16 M18 M25 N10 N11 N13 N14 N15 N16 N17 N19 K7 P8 P9 M9 P11 P13 P16 P17 P18 P12 R8 R9 R11 R12 R13 R17 T8 T9 N7 T11 T12 T13 T14 T15 T16 T17 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 R18 V9 V10 V11 V12 V14 V17 T7 E8

H6 G5 G4 J5 J4 SAR0/GPIO31 SAR1/GPIO32 SAR2/GPIO33 SAR3/GPIO34 SAR4/GPIO35

R498 0 NON_EU
AA2

COMP2_Pr+ COMP2_Y+ COMP2_Pb+

R420 R421 R422 R423 R424 R425 R426

33 68 33 68 33 68 0

C415 C416 C417 C418 C419 C420 C421

0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 1000pF

Y2 AA3 W2 Y3 V1 W3 W1

HSYNC2 RIN2P RIN2M GIN2P GIN2M BIN2P BIN2M SOGIN2 EARPHONE_OUTL EARPHONE_OUTR CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBSOUT0 CVBSOUT1 ET_RXD[1]/RN/GPIO63 ET_TXD[1]/LED1/GPIO56 B5 ET_TX_CLK/TN/GPIO59 VCOM ET_TX_EN/GPIO58 ET_MDC/GPIO61 ET_MDIO/GPIO62 ET_COL/LED0/GPIO55 C3 A3 B3 B4 ET_RXD[0]/RP/GPIO60 ET_TXD[0]/TP/GPIO57 A6 C4 C6 C5 AUVAG AUVRP AA6 AB6 AUVRM AE5 AC6 AD5

R23 VSYNC_LIKE/GPIO145 R24 SPI1_CK/GPIO201 SPI1_DI/GPIO202 SPI2_CK/GPIO203 SPI2_DI/GPIO204

+1.10V_VDDC

C431 4.7uF

C434 1uF

C449 0.1uF

C454 10uF

R25

L401 BLM18SG121TN1D

T21 T22

VDDC : 2026mA MIUVDDC L405 120-ohm Main C436 0.1uF Close to the Main IC

C1406 C1407 C1408 C1409 C1410 C1411 C1412 C1413

0.1uF 0.1uF 0.1uF 10uF 10uF 10uF 0.1uF 10uF

K11 L10 M12 M13 N12 P14 P15 R10 R14 R15 T10

TU_CVBS AV/SC1_CVBS_IN COMP2_Y+ C400 1000pF READY DTV/MNT_VOUT

R427 33 C422 R428 EU 33EUC423 R429 33 C424

0.047uF 0.047uF 0.047uF

AA8 Y4 W4 AA5 Y5 AA4 Y6 AA1

RP TP RN ETH_LED1 R402 EU 22 DSUB_DET AV2_DET ETH_LED0 R445 R460 R431 R443 49.9 49.9 49.9 49.9 1% 1% 1% 1% ET_NET ET_NET ET_NET ET_NET C426 0.1uF ET_NET C458 0.1uF ET_NET TN CI_DET

MODEL OPTION
PIN NAME MODEL_OPT_1 MODEL_OPT_2 PIN NO. A9 F4 HIGH 3D FHD LOW

DDR
2D HD A-TMA0 A-TMA1 A-TMA2 A-TMA3 A-TMA4 A-TMA5 A-TMA6 A-TMA7 A-TMA8 A-TMA9 A-TMA10 A-TMA11 A-TMA12 A-TMA13 A-TMA14
A11 C14 B11 F12 C15 E12 A14 D11 B14 D12 C16 C13 A15 E11 B13 A_DDR3_A[0] A_DDR3_A[1] A_DDR3_A[2] A_DDR3_A[3] A_DDR3_A[4] A_DDR3_A[5] A_DDR3_A[6] A_DDR3_A[7] A_DDR3_A[8] A_DDR3_A[9] A_DDR3_A[10] A_DDR3_A[11] A_DDR3_A[12] A_DDR3_A[13] A_DDR3_A[14]

P10

50V

IC400 LGE2111A-T8
+2.5V
B23 B_DDR3_A[0] B_DDR3_A[1] B_DDR3_A[2] B_DDR3_A[3] B_DDR3_A[4] B_DDR3_A[5] B_DDR3_A[6] B_DDR3_A[7] B_DDR3_A[8] B_DDR3_A[9] B_DDR3_A[10] B_DDR3_A[11] B_DDR3_A[12] B_DDR3_A[13] B_DDR3_A[14] D25 F22 G22 E24 F21 E23 D22 D24 D21 C24 C25 F23 E21 D23

FB_CORE

P19 R16 L11 M14

R433

68

C428

0.047uF

AB4

+3.3V

N4 IRIN/GPIO4 ARC0 HWRESET T6 N5

TX SOC_RESET

R1401 1K READY

R401 1K FHD

R430 1K 3D MODEL_OPT_1

B-TMA0 B-TMA1 B-TMA2 B-TMA3 B-TMA4 B-TMA5 B-TMA6 B-TMA7 B-TMA8 B-TMA9 B-TMA10 B-TMA11 B-TMA12 B-TMA13 B-TMA14

L402 120-ohm Main L414 Main 120-ohm +3.3V_ST L403 120-ohm Main

C1415 C1416 C1417 AVDD2P5:172mA C425 AVDD25_PGA:13mA C439 0.1uF C1418 L413 120-ohm Main C469

0.1uF 0.1uF 10uF 0.1uF 0.1uF

C440 0.1uF Close to the Main IC AVDD_NODIE:7.362mA

0.1uF

U19

L406 +3.3V 120-ohm Main AVDD33 C441 0.1uF Close to the Main IC L408 120-ohm Main C473 C474 C475 C442 0.1uF Close to the Main IC C476 C477 1uF 10uF 0.1uF 0.1uF 0.1uF C471 C427 0.1uF 10uF

W15 U7

IC400-*2 LGE2111A-TE SPIL


C7 E6 F5 B6 E5 D5 B7 E7 F7 AB5 AB3 V23 U24 V25 V24 W25 W23 AA23 Y24 AA25 AA24 AE24 LVACKP LVACKN LVBCKP LVBCKN T25 GPIO196 GPIO193 GPIO194 GPIO195 U23 T24 T23 AD24 Y23 W24 LVB0N LVB1P LVB1N LVB2P LVB2N LVB3P LVB3N LVB4P LVB4N A9 F4 AB1 N6 AB2 AC2

IC400-*3 LGE2111A-T8 SPIL

RF_SWITCH_CTL

ARC
AB25

HDMI_ARC R1400 1K READY R419 1K HD R467 1K 2D

MODEL_OPT_3

E6 F5 B6 E5 D5 B7 E7 F7 AB5 AB3 A9 F4 AB1 N6 AB2 AC2

GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO45 GPIO46 GPIO49 GPIO50

LVA0P LVA0N LVA1P LVA1N LVA2P LVA2N LVA3P LVA3N LVA4P LVA4N

GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO45 GPIO46 GPIO49 GPIO50

LVA0P LVA0N LVA1P LVA1N LVA2P LVA2N LVA3P LVA3N LVA4P LVA4N

16V

C7

AB25 AB23 AC25 AB24 AD25 AC24 AE23 AC23 AC22 AD23

AB23 AC25 AB24 AD25 AC24 AE23 AC23 AC22 AD23 V23 U24 V25 V24 W25 W23 AA23 Y24 AA25 AA24 AE24

C1419 0.1uF READY

R1406 150 READY R1407 63.4 READY +3.3V_ST GND

A-TMBA0 A-TMBA1 A-TMBA2 A-TMCK A-TMCKB A-TMCKE

F13 B15 E13 C17 A17 B16 A_DDR3_MCLK A_DDR3_MCLKZ A_DDR3_MCLKE B_DDR3_MCLK B_DDR3_MCLKZ B_DDR3_MCLKE A_DDR3_BA[0] A_DDR3_BA[1] A_DDR3_BA[2] B_DDR3_BA[0] B_DDR3_BA[1] B_DDR3_BA[2]

G20 F24 F20 G25 G23 F25

B-TMBA0 B-TMBA1 B-TMBA2 B-TMCK B-TMCKB B-TMCKE

M7 P7 R7 M19 V7 W7 R19 T19 W18

LVB0P GPIO51 USA_SPIL_MAIN IC GPIO52 I2C_SCKM0/GPIO53 I2C_SDAM0/GPIO54 GPIO73 GPIO74

GPIO51EU_SPIL_MAIN ICLVB0P GPIO52 I2C_SCKM0/GPIO53 I2C_SDAM0/GPIO54 GPIO73 GPIO74 LVB0N LVB1P LVB1N LVB2P LVB2N LVB3P LVB3N LVB4P LVB4N LVACKP LVACKN LVBCKP LVBCKN

SOC_RESET

A-TMODT A-TMRASB A-TMCASB A-TMWEB A-TMRESETB

E14 B12 A12 C12 F11 A_DDR3_RESET B_DDR3_RESET A_DDR3_ODT A_DDR3_RASZ A_DDR3_CASZ A_DDR3_WEZ B_DDR3_ODT B_DDR3_RASZ B_DDR3_CASZ B_DDR3_WEZ

D20 B25 B24 A24 E20

AU33:31mA

B-TMODT B-TMRASB B-TMCASB B-TMWEB B-TMRESETB

C429 22uF 16V

AD24 Y23 W24 T25

C487 10uF 16V READY R436 10 SOC_RESET

W19

A-TMDQSL A-TMDQSLB A-TMDQSU A-TMDQSUB

B19 C18 B18 A18 E15 A21 D17 G15 B21 F15 B22 F14 A22 D15 G16 B20 F16 C21 E16 A20 D16 C20 A_DDR3_DQU[0] A_DDR3_DQU[1] A_DDR3_DQU[2] A_DDR3_DQU[3] A_DDR3_DQU[4] A_DDR3_DQU[5] A_DDR3_DQU[6] A_DDR3_DQU[7] B_DDR3_DQU[0] B_DDR3_DQU[1] B_DDR3_DQU[2] B_DDR3_DQU[3] B_DDR3_DQU[4] B_DDR3_DQU[5] B_DDR3_DQU[6] B_DDR3_DQU[7] A_DDR3_DQL[0] A_DDR3_DQL[1] A_DDR3_DQL[2] A_DDR3_DQL[3] A_DDR3_DQL[4] A_DDR3_DQL[5] A_DDR3_DQL[6] A_DDR3_DQL[7] B_DDR3_DQL[0] B_DDR3_DQL[1] B_DDR3_DQL[2] B_DDR3_DQL[3] B_DDR3_DQL[4] B_DDR3_DQL[5] B_DDR3_DQL[6] B_DDR3_DQL[7] A_DDR3_DQML A_DDR3_DQMU B_DDR3_DQML B_DDR3_DQMU A_DDR3_DQSU A_DDR3_DQSUB B_DDR3_DQSU B_DDR3_DQSUB A_DDR3_DQSL A_DDR3_DQSLB B_DDR3_DQSL B_DDR3_DQSLB

K24 K25 J21 J20 H24 L20 L23 J24 L24 J23 M24 H23 M23 K23 G21 L22 H22 K20 H20 L21 H21 K21

B-TMDQSL B-TMDQSLB B-TMDQSU B-TMDQSUB B-TMDML B-TMDMU B-TMDQL0 B-TMDQL1 B-TMDQL2 B-TMDQL3 B-TMDQL4 B-TMDQL5 B-TMDQL6 B-TMDQL7 B-TMDQU0 B-TMDQU1 B-TMDQU2 B-TMDQU3 B-TMDQU4 B-TMDQU5 B-TMDQU6 B-TMDQU7

L409 120-ohm Main VDD33_T/VDDP/U3_VD33_2:47mA VDD33_NAND C453 0.1uF +1.5V_DDR_IN C455 0.1uF

C479 C482 C483 C484 C485

1uF 10uF 10uF 10uF 0.1uF

GPIO196 GPIO193 GPIO194 GPIO195

U23 T24 T23

D400 KDS181

R434 100K

C430 0.1uF 16V

A-TMDML A-TMDMU A-TMDQL0 A-TMDQL1 A-TMDQL2 A-TMDQL3 A-TMDQL4 A-TMDQL5 A-TMDQL6 A-TMDQL7 A-TMDQU0 A-TMDQU1 A-TMDQU2 A-TMDQU3 A-TMDQU4 A-TMDQU5 A-TMDQU6 A-TMDQU7

Close to the Main IC C486 C492 AVDD_DDR0:55mA AVDD_DDR1:55mA L412 120-ohm Main C470 C488 C468 0.1uF 1uF 10uF Close to the Main IC C493 C494 C497 C498 0.1uF 0.1uF 10uF 10uF 0.1uF 10uF

L17 M17 L16

<LM1 CHIP Config> (AUD_SCK,AUD_MASTER_CLK,PWM1,PWM0)


B51_NO_EJ SB51_WOS SB51_WS MIPS_SPI_NO_EJ MIPS_SPI_EJ_1 MIPS_SPI_EJ_2 MIPS_WOS MIPS_WO : : : : : : : : 4b0000 4b0001 4b0010 4b0100 4b0101 4b0110 4b1001 4b1010 Boot from 8051 with SPI flash Secure B51 without scramble Secure B51 with scramble Boot from MIPS with SPI flash Boot from MIPS with SPI flash Boot from MIPS with SPI flash Secure MIPS without scramble Secure MIPS with scramble

C467 1000pF

+3.3V

CLose to Saturn7M IC
R455 1K READY R439 1K READY R447 1K READY R456 1K READY R453 1K VCC_1.5V_DDR

CLose to Saturn7M IC
VCC_1.5V_DDR

E22 F8 F17 F18 F19 G8 H8

AUD_SCK AUD_MASTER_CLK PWM1 R454 1K READY PWM0 LED_RED R457 1K

R483 1K 1% A-MVREFCA

R491 1K 1% B-MVREFCA R492 1K 1% C465 0.1uF C466 1000pF

N22 N21 N20 M22 M21 M20 F10 V15 W16 V8 T18

R463 1K

R440 1K

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

R448 1K

R484 1K 1%

C463 0.1uF

C464 1000pF

GP4_S7LR MAIN

2011-10-20 4 6

LGE Internal Use Only

VCC_1.5V_DDR M8 VREFCA A0 A1 A-MVREFDQ R503 1K 1% C503 C501 0.1uF 1000pF C524 C525 C526 C527 C528 C529 C530 C531 C532 C533 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF A1 A8 C1 C9 D2 E9
Hynix_1G_1600

DDR3 Memory 1GBit x 2


N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A-TMA0 A-TMA1 A-TMA2 A-TMA3 A-TMA4 A-TMA5 A-TMA6 A-TMA7 A-TMA8 A-TMA9 A-TMA10 A-TMA11 A-TMA12 A-TMA13

A2 MMBD6100 D500*-1

MULTI

IC501 H5TQ1G63DFR-H9C

LVDS
+5V R512 4.7K R513 4.7K

Key/IR
+3.3V_ST P501 12507WS-08L USA ZD502 5.48VTO5.76V 5.48VTO5.76V 5.48VTO5.76V 5.48VTO5.76V 5.48VTO5.76V R515 4.7K R518 100 C517 10pF 50V R540 10K R542 10K R517 100 R516 100 KEY2 5.48VTO5.76V 1

A1

NAND Flash 1GBit


NC_1 +3.3V NC_2 NC_3 NC_4

IC504 H27U1G8F2BTR-BC
+3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC_29 NC_28 NC_27 PCM_A[0-7] NC_26 I/O7 I/O6 I/O5 I/O4 NC_25 NC_24 NC_23 VCC_2 VSS_2 NC_22 NC_21 NC_20 I/O3 I/O2 I/O1 I/O0 NC_19 NC_18 NC_17 NC_16 C554 10uF 10V

+5V

R577 4.7K

R502 1K 1%

A-MVREFCA

H1 VREFDQ

A2 A3 A4 A5 ZQ A6 A7 A8 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 BA0 BA1 BA2 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 CS ODT RAS CAS WE NC_1 NC_2 NC_3 NC_4 NC_6 DQSL DQSL RESET CK CK CKE NC_5 A9 A10/AP A11 A12/BC A13

IR

+3.3V_ST

R505 240 1%

L8

ZD501

LD500 C D500 KDS184


C B

KEY1

3 R565 1K /F_RB 5 /PF_OE ZD503 R568 4.7K

NC_5 NC_6 R/B RE CE

AR518 22
PCM_A[7] PCM_A[6] PCM_A[5] PCM_A[4]

A1

A2

B2 D9 G7 K2 K8 N1 N9 R1 R9

C534 220pF 50V ZD500 R514 22

2K R579

E Q500 MMBT3904(NXP)

C535 220pF 50V LED_RED +3.3V_ST

P500 104060-8017
P503 TF05-51S

47K R578

M2 N8 M3 J7 K7 K9 L2 K1 J3 K3 L3 T2

A-TMBA0 A-TMBA1 A-TMBA2 R509 56 1% R511 56 1% C543 0.01uF 50V

A-TMCK A-TMCKB

R538 4.7K 1 2 3 4 5 6 7 8 9 RXA0RXA0+ RXA1RXA1+ RXA2RXA2+ RXACKRXACK+ RXA3RXA3+ RXA4RXA4+ 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RXB0RXB0+ RXB1RXB1+ RXB2RXB2+ RXBCKRXBCK+ RXB3RXB3+ RXB4RXB4+ 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 R576 R536 R537 READY 0 0 0 UART_RXD UART_TXD SUB_SDA SUB_SCL

1 2 3 4 5 6 7 8 9 10 11

R539 4.7K R519 100

C520 10pF 50V

/PF_CE0 NC_7 R566 1K READY C550 0.1uF NC_8 VCC_1 VSS_1 9 NC_9 NC_10

7 ZD507 ZD506

C522 10pF R520 50V 100 READY C523 10pF 50V READY

C555 0.1uF

A-TMCKE

5.48VTO5.76V ZD505 ZD504

+3.3V_ST 5.48VTO5.76V

CLE /PF_CE1 ALE PF_ALE WE /PF_WE WP /PF_WP R558 0 R556 3.3K R567 1K NC_11 NC_12 NC_13 NC_14 NC_15

AR519 22
PCM_A[3]
IC504-*1 K9F1G08U0D-SCB0

F1 H2
M8 H1 VREFDQ VREFCA

A-TMODT
12

IC501-*1 H5TQ1G63DFR-PBC
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A15 M2 N8 M3 J7 K7 K9 L2 K1 J3 K3 L3 T2 RESET CS ODT RAS CAS WE NC_1 NC_2 NC_3 F3 G3 C7 B7 E7 D3 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 DML DMU DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 NC_4 NC_6 CK CK CKE BA0 BA1 BA2 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 A1 A8 C1 C9 D2 E9 F1 H2 H9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ L8

A-TMRASB A-TMCASB A-TMWEB

H9 J1 J9 L1 L9 A-TMA14 T7

VCC_1.5V_DDR R506 10K

13 14 15 16

C547 0.1uF 16V

PCM_A[2] PCM_A[1] PCM_A[0]

SS NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 R/B RE CE NC_7 NC_8 VCC_1 VSS_1 NC_9 NC_10 CLE ALE WE WP NC_11 NC_12 NC_13 NC_14 NC_15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

NC_29 NC_28 NC_27 NC_26 I/O7 I/O6 I/O5 I/O4 NC_25 NC_24 NC_23 VCC_2 VSS_2 NC_22 NC_21 NC_20 I/O3 I/O2 I/O1 I/O0 NC_19 NC_18 NC_17 NC_16

A-TMRESETB

17 18 19

F3 G3 C7

A-TMDQSL A-TMDQSLB

20 21 22 23

A9 B3 E1 G8 J2 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQL7 DML DMU DQSU DQSU

A-TMDQSU A-TMDQSUB A-TMDML A-TMDMU


SS_1G_1333 SS_2G_1333

24 25 26

B7 E7 D3 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3

HD

27 28 29 30

SS_1G_1600

J8 M1
M8 H1 VREFDQ VREFCA

IC501-*2 K4B1G1646G-BCK0
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 NC_5 M2 N8 M3 J7 K7 K9 L2 K1 J3 K3 L3 T2 RESET CS ODT RAS CAS WE NC_1 NC_2 NC_3 F3 G3 C7 B7 E7 D3 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 DML DMU DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 NC_4 NC_6 CK CK CKE BA0 BA1 BA2 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 A1 A8 C1 C9 D2 E9 F1 H2 H9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ L8

IC501-*3 K4B1G1646G-BCH9

IC501-*4 K4B2G1646C
N3 P7 P3 H1 N2 P8 P2 L8 R8 R2 T8 B2 R3 L7 R7 N7 T3 M7 NC_5 M2 N8 M3 A1 BA0 BA1 BA2 A1 VDDQ_1 CK CK CKE L2 K1 J3 K3 L3 J1 T2 RESET CS ODT RAS CAS WE VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 NC_1 NC_2 NC_3 F3 G3 C7 B7 E7 D3 E3 F7 F2 F8 H3 H8 G2 H7 B1 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 B1 VSSQ_1 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B9 D1 D8 E2 E8 F9 G1 G9 DML DMU DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL A9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 NC_4 NC_6 J9 L1 L9 T7 A8 C1 C9 D2 E9 F1 H2 H9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ L8 VREFDQ H1 VREFCA M8

A-TMDQL0 A-TMDQL1 A-TMDQL2 A-TMDQL3 A-TMDQL4 A-TMDQL5 A-TMDQL6 A-TMDQL7 A-TMDQU0 A-TMDQU1 A-TMDQU2 A-TMDQU3 A-TMDQU4 A-TMDQU5 A-TMDQU6 A-TMDQU7

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 NC_5 M2 N8 M3 J7 K7 K9 L2 K1 J3 K3 L3 T2 RESET CS ODT RAS CAS WE NC_1 NC_2 NC_3 F3 G3 C7 B7 E7 D3 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 DML DMU DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL NC_4 NC_6 CK CK CKE BA0 BA1 BA2 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 ZQ VREFDQ VREFCA

M8

M9 P1 P9 T1 T9

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

D9 G7 K2 K8 N1 N9 R1 R9

A8 C1 C9 D2 E9 F1 H2 H9

J7 K7 K9

SERIAL FLASH 8MBit


+3.3V_ST +3.3V_ST +3.3V_ST

J9 L1 L9 T7

B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

IC505 W25Q80BVSSIG
IC505-*1 MX25L8006EM2I-12G
MX CS#

R564 10K /SPI_CS

B9 D1 D8 E2 E8 F9 G1 G9

D7 C3 C8 C2 A7 A2 B8 A3

R569 4.7K READY

CS

VCC

C556 0.1uF

RXA0RXA0+ RXA1RXA1+ RXA2RXA2+ RXACKRXACK+ RXA3RXA3+ RXA4RXA4+


SO/SIO1 WP#

VCC

HOLD#

DO[IO1] SPI_SDO R561 0 /FLASH_WP GND

FHD

42 43 44 45 46 47 48 49 50 51

HOLD[IO3]

SCLK

GND

SI/SIO0

%WP[IO2]

CLK SPI_SCK R575 DI[IO0] 33 SPI_SDI

IC500 H5TQ1G63DFR-H9C
VCC_1.5V_DDR M8 VREFCA A0 A1 B-MVREFDQ R501 1K 1% C502 C500 0.1uF 1000pF C506 C507 C508 C509 C510 C511 C512 C513 C514 C515 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF A1 A8
Hynix_1G_1600

R500 1K 1%

B-MVREFCA

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 NC_5

B-TMA0 B-TMA1 B-TMA2 B-TMA3 B-TMA4 B-TMA5 B-TMA6 B-TMA7 B-TMA8 B-TMA9 B-TMA10 B-TMA11 B-TMA12 B-TMA13

52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 B-TMCK 68 69 70 R508 56 1% R510 56 1% 71 72 73 74

H1 VREFDQ

A2 A3 A4 A5 ZQ A6 A7 A8 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 BA0 BA1 BA2 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 CS ODT RAS CAS WE NC_1 NC_2 NC_3 NC_4 NC_6 DQSL DQSL RESET CK CK CKE A9 A10/AP A11 A12/BC A13

RXB0RXB0+ RXB1RXB1+ RXB2RXB2+ RXBCKRXBCK+ RXB3RXB3+ RXB4RXB4+


IC503-*1 R1EX24256BSAS0A
Renesas_IC503 A0 1 A1 VCC

R504 240 1%

L8

A0h

B2 D9 G7 K2 K8 N1 N9 R1 R9

EEPROM 1MBit
+3.3V

C552 0.1uF

WP

A2

SCL

IC503 AT24C256C-SSHL-T
A0 VCC

M2 N8 M3 J7 K7 K9 L2 K1 J3 K3 L3 T2

B-TMBA0 B-TMBA1 B-TMBA2

B-TMCKB

VSS

SDA

A1

WP

A2

C1 C9
M8 H1 VREFDQ VREFCA

SCL

R573 22 I2C_SCL R574 22 I2C_SDA

IC500-*1 H5TQ1G63DFR-PBC
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A15 M2 N8 M3 J7 K7 K9 L2 K1 J3 K3 L3 T2 RESET CS ODT RAS CAS WE NC_1 NC_2 NC_3 F3 G3 C7 B7 E7 D3 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 DML DMU DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 NC_4 NC_6 CK CK CKE BA0 BA1 BA2 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 A1 A8 C1 C9 D2 E9 F1 H2 H9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ L8

B-TMCKE

D2 E9 F1 H2 H9 J1 J9 L1 L9 B-TMA14 T7

C542 0.01uF 50V

75 76 77 78 79

P_SDA
GND

DISP_EN P_SCL PC_SER_DATA PC_SER_CLK

SDA

B-TMODT B-TMRASB B-TMCASB B-TMWEB B-TMRESETB R507 10K 81 VCC_1.5V_DDR

80

F3 G3 C7

B-TMDQSL B-TMDQSLB B-TMDQSU


SS_1G_1333 SS_2G_1333

SS_1G_1600

A9 B3
M8

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12

DQSU DQSU

IC500-*2 K4B1G1646G-BCK0
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 NC_5 M2 N8 M3 J7 K7 K9 L2 K1 J3 K3 L3 T2 RESET CS ODT RAS CAS WE NC_1 NC_2 NC_3 F3 G3 C7 B7 E7 D3 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 DML DMU DQSU DQSU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSL A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 NC_4 NC_6 CK CK CKE BA0 BA1 BA2 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 J9 L1 L9 T7 A1 A8 C1 C9 D2 E9 F1 H2 H9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ L8 VREFDQ H1 VREFCA

B7 E7

B-TMDQSUB
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7

IC500-*3 K4B1G1646G-BCH9
M8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 M7 NC_5 M2 N8 M3 BA0 BA1 BA2 A1 VDDQ_1 CK CK CKE L2 CS ODT RAS CAS WE VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 NC_1 RESET NC_2 NC_3 F3 NC_4 DQSL DQSL NC_6 J9 L1 L9 T7 F3 G3 A9 DQSU DQSU E7 DML DMU E3 F7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 B1 VSSQ_1 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B9 D1 D8 E2 E8 F9 G1 G9 D7 C3 C8 C2 A7 A2 B8 A3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 F2 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 E3 F7 F2 F8 H3 H8 G2 H7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E7 D3 DML DMU C7 B7 DQSU DQSU DQSL DQSL T2 A8 C1 C9 D2 E9 F1 H2 H9 L2 K1 J3 K3 L3 CS ODT RAS CAS WE J7 K7 K9 CK CK CKE VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 M2 N8 M3 BA0 BA1 BA2 M7 NC_5 ZQ L8 VREFDQ H1 VREFCA

IC500-*4 K4B2G1646C
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 B2 D9 G7 K2 K8 N1 N9 R1 R9 ZQ L8 VREFDQ H1 VREFCA M8

E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

HDCP EEPROM 8KBit


+3.3V

Addr:10101--

DML DMU

B-TMDML B-TMDMU B-TMDQL0 B-TMDQL1 B-TMDQL2 B-TMDQL3 B-TMDQL4 B-TMDQL5 B-TMDQL6 B-TMDQL7 B-TMDQU0 B-TMDQU1 B-TMDQU2 B-TMDQU3 B-TMDQU4 B-TMDQU5 B-TMDQU6 B-TMDQU7

D3 E3

R7 N7 T3

A1 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J1 NC_1 J9 L1 L9 T7 NC_2 NC_3 NC_4 NC_6 A8 C1 C9 D2 E9 F1 H2 H9

J7 K7 K9

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

F7 F2 F8 H3 H8 G2 H7 D7

K1 J3 K3 L3 T2

RESET

G3 C7 B7

A9 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

D3

IC502 CAT24C08WI-GT3-H-RECV(TV)

F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3

R563 4.7K

NC_1 NC_2

B1 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B9 D1 D8 E2 E8 F9 G1 G9

1 2

8 7

VCC WP SCL SDA

R570 4.7K R571 22 R572 22 I2C_SCL I2C_SDA

B1 B9 D1 D8 E2 E8 F9 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

A2 3 VSS 4

READY
6 5

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

C3 C8 C2 A7 A2 B8 A3

+1.5V_DDR_IN

VCC_1.5V_DDR

L500 500 Main

C544 10uF 10V

C545 0.1uF 16V

G1 G9

* LCI: LVDS Connection Indicator

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

GP4_S7LR
Memory.LVDS,IR

2011-10-20 5 6

LGE Internal Use Only

P_17V
P600 SMAW200-H18S1

+3.3V Multi
C642 0.01uF READY 100pF R639 3300pF 10K R648 120K C641

P_17V C613 10uF 25V READY C620 10uF 25V C621 0.1uF 50V R661 10K ERROR_DET +5V_ST C608 10uF 10V C610 0.1uF 16V R1 R617 59K 1% C623 22pF 50V READY R2 R619 17.4K 1% C624 1uF 10V

1 3 5 +3.3V_ST 7 9 R600 10K RL_ON 5V_ON C602 0.1uF 16V READY C603 0.1uF 16V READY 11 13 15 17

2 4 6 8 10 12 14 16 18 C607 0.1uF 16V AC_DET C606 0.1uF 16V R609 100 L600 120

+5V

V7V

FB2

SS2

1 THERMAL

+3.3V
VBST

C632 4.7uF 10V

EN2

EN

VIN

CMP2

C634 10uF 16V

L606 CIS21J121

LOW_P

RLIM2

DCON_EN

+5V

IC603 TPS54327DDAR [EP]GND

C636

DCON_EN

Power Wafer

1.5V DDR / 1.24V Core

R650 33K R634 56K

VFB

R670 4.7 READY C655 0.047uF 25V C609 3300pF READY

21

20

19

18

17

16

VREG5

SW

C628 4700pF 50V

L605 NR5040T2R2N 2.2uH C650 10uF 16V C629 10uF 16V C630 0.1uF 16V R622 0

15

R2
R656 47K 1% C656 22uF 16V C651 22uF 16V

19 SS 4 5 GND

V3V GND_1 PGOOD GND_2 GND_3

22 23 24 25 26 27 28 1 2 3 4 5 6 7

14 13 12

BST2 VIN2 LX2_2 LX2_1 LX1_2 LX1_1 VIN1


C653 10uF 25V C654 10uF 25V L608 NR5040T3R3N L607 NR5040T3R3N

C626 3300pF 50V

R657 43K 1%

C666 0.022uF 16V +1.5V_DDR_IN

IC605 TPS65253RHDR
THERMAL 29

11 10 9 8

R1

Vout=0.765*(1+R1/R2)
GND_4 GND_5

+1.10V_VDDC C683 22uF 16V C657 22uF 16V R653 4.3K 1% R654 51K 1% R655 100K 1% C661 0.022uF 16V

3.3Vst
+5V_ST IC600 AP2121N-3.3TRE1 VIN 3 C600 10uF 10V C601 0.1uF 16V 1 GND 2 VOUT C604-*1 1uF 10V MULTI C604 1uF 6.3V +3.3V_ST

2.5V Multi/2.5_TU
+3.3V IC601 TJ3940S-2.5V-3L VIN 3 1 C605 10uF 6.3V GND 2 VOUT +2.5V L613 120-ohm 2A DVB_T2 R612 1 C612 10uF 6.3V +2.5V_TU

1.25V_TU
+3.3V IC602 AP1117EG-13 FNIM IN OUT R620 1 FNIM C625 10uF 6.3V FNIM +1.25V_TU

3.3V_TU /1.8V_TU
+3.3V +3.3V_TU IC604 R2 AZ1117BH-ADJTRE1 220 100 R614 R613 5% 5% +1.8V_TU

R1 R2

R658 0 READY

FB_CORE

RLIM1

ROSC

CMP1

BST1

FB1

SS1

EN1

[EP]GND

C652 0.047uF 25V

L604 120-ohm 2A

INPUT C627 10uF 6.3V

ADJ/GND

0.01uF

ADJ/GND C671 10uF 10V DVB_T2 C682 0.1uF 16V DVB_T2 C617 10uF 6.3V FNIM

OUTPUT

R630 3K 1% R631 390K 1% R621 1 C631 10uF 6.3V

R635 3300pF 10K

R647 100K

R2
R615 1 FNIM

R1
R618 240 FNIM

C645

C648

C649

DCON_EN

R649 33K

R1

100pF READY

R662 56K

C611 3300pF 50V READY R666 4.7 READY

Vout=1.25*(1+R2/R1)

Vout=1.25*(1+R2/R1)

Vout=0.8*(1+R1/R2)

+3.3V

Audio AMP
R628 10K READY R627 10K C B R636 0 READY

EMI GND
R608 0 R607 0

AMP_MUTE READY

Q600 MMBT3904(NXP) E READY R637 0 C643 0.1uF 50V

EAPD/OUT4B TWARN/OUT4A VDD_DIG_1 GND_DIG_1

19 20 21 22 23 24 25 26 27Close-by 28 29 30

18 17 16 15 14 13 12 11

OUT3A/FFX3A OUT3B/FFX3B CONFIG VDD GND_REG


39 R685 R686 39 C660 0.1uF 50V

R605 0 R606 0

EMI_GND1

AC_DET R625 2.2 22 R638

PWRDN VDD_PLL

R604 0 L609 10.0uH C672 0.22uF 50V C674 0.22uF 50V C678 1000pF 50V 4 R602 0

EMI_GND2

OUT1A GND1 VCC1 OUT1B OUT2A VCC2 GND2


P_17V
C664 1uF C665 C662 1uF C663

C633 0.1uF 16V R626 0 AUD_MASTER_CLK

C637 4700pF 50V

C647 680pF 50V

FILTER_PLL GND_PLL

25V C669 0.1uF 50V 330pF 50V

READY AUD_SCK READY AUD_LRCK READY AUD_LRCH READY AMP_RESET_N

C635 22pF 50V C639 22pF 50V C640 22pF 50V C644 22pF 50V

Close-by
10 9 8 7

L610 10.0uH

C675 0.22uF 50V

C679 1000pF 50V

SMAW250-H04R P601

R629 2K

R601 0 R603 0

EMI_GND3

22 R640 22 R641 22 R642 22 R643 22 R644

XTI BICKI LRCKI SDI RESET INT_LINE SDA SCL

C670 25V 330pF 50V 39 R687

L611 10.0uH C673 0.22uF 50V

2 C676 0.22uF 50V C677 0.22uF 50V C680 1000pF 50V C681 1000pF 50V

0.1uF 50V

R688 39

EMI_GND4 GND

Close-by
31 32 THERMAL 33 37 34 35 36 Close-by 6 5 4 3 2 1

L612 10.0uH C667 0.1uF 50V C668 68uF 35V

OUT2B VCC_REG VSS TEST_MODE SA GND_SUB


C659 0.1uF 50V

R623

2K AMP_SDA

R645 22 R646 22

R624

2K AMP_SCL

R633 10K C638 0.1uF 50V C646 0.1uF 50V

GND_DIG_2 VDD_DIG_2 [EP]GND

STA368BWG IC606

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

GP4_S7LR
Power,AMP

2011-04-01 6
LGE Internal Use Only

8Pin Wafer to Main


P1 12507WS-08L

Green Eye Sensor

+3.3V_ST
OPT R3 4.7K 1

+3.3V_ST

IR Receiver

+3.3V_ST IR
OPT R13 2K IC2 KSM-903SMR1CL VDD IC1 CM3231A3OG 1 VOUT ZD3-*1 5.48VTO5.76V ZD1-*1 5.48VTO5.76V R1 47 R14 2.7K

3 KEY1

IR
3 SCLK

4 KEY2 5 LED_R 6 EYE_SCL 7 EYE_SDA 8 GND 1

EYE_SCL
SDAT

GND

ZD3 5.6B

ZD1 5.6B
R2 330

EYE_SDA
C1 0.1uF 16V C2 10uF 6.3V

VCC

OPT

+3.3V_ST
C4 0.1uF 16V

ZD6 5.6B

ZD7 5.6B

ZD2 5.6B

C3 10uF 6.3V

8 9 9

+3.3V_ST ZD6-*1 5.48VTO5.76V ZD7-*1 5.48VTO5.76V

ZD2-*1 5.48VTO5.76V

ZD4 5.6B

ZD5 5.6B

ZD4-*1 5.48VTO5.76V

ZD5-*1 5.48VTO5.76V

JTP1283

JTP1283

JTP1283

JTP1283

JTP1283

JTP1283

JTP1283

JTP1283

Tact Switch
3 3 3 3 3 3 3 2 2 2 2 2 2 2 3 SW1-*1 KEY2 SW2-*1 SW3-*1 SW4-*1 SW5-*1 SW6-*1 SW7-*1 SW8-*1 2

RED LED
+3.3V_ST

R15 10K KEY1 R5 27K JTP1289 JTP1289 R6 3.9K JTP1289 R7 10K JTP1289 R8 27K JTP1289 R9 620 JTP1289 R10 3.9K JTP1289 R11 10K JTP1289 R12 620

LED_R
OPT C5 0.1uF 16V

R4 4.7K

C B Q1 MMBT3904(NXP) E OPT C7 10uF 6.3V

LTST-C191KRKT LD1 EAV60793101

ZD8 5.6B

OPT C6 0.1uF 16V

SW1

SW2

SW3

SW4

SW5

SW6

SW7

SW8

ZD9 5.6B

ZD8-*1 5.48VTO5.76V

ZD9-*1 5.48VTO5.76V

Power 2.4V

Input 0.93V

Home 1.65V

OK 2.4V

Vol0.2V

Vol+ 0.93V

CH1.65V

CH+ 0.2V

(KEY1) (KEY1) (KEY2) (KEY2)

(KEY2) (KEY2) (KEY1) (KEY1)

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

EAX64342101 Tact/IR/Eye

12/04/2011 1 1
LGE Internal Use Only

GP2R, LM1 Training Manual

Table of contents
1. PCB layout. 2. GP2R vs LM1 3. GP2R. (Block, Power, I2C) 4. LM1. (Block, Power, I2C) 5. LM1 SOC Power sequence. 6. Memory test. 7. Pen touch overview.

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

1. PCB Layout.

GP2R (206 x 183)

LM1 (206 x 141.5)

LM1 use internal EDID&HDCP. (LM1 is Removing the EEPROM for EDID&HDCP) LM1 is optimizing Power block. (LM1 is reducing DC/DC, LDO, power application)

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

2. GP2R vs GP4 LM1.


Difference PDP Module Tool PCB VSC Main IC Jack Layout Sub Assy PSU SW JIG Power Wafer Stand by 3.5V 12V_secondary

GP2R 50PZ550
R3(FHD) PZ Tool 206x183 S7R

LM1 50PA6500
R4(FHD) PA Tool 206x141.5 S7LR New module. 50R4 Initial model. 12 years New tool.

Changes

change PCB Size. (smaller than GP2R.) Internal sub-Micom .(PM block)

Slim Depth PZ Tool 50R3 XP5 Bd GP2R GP2R . 18P O X

Slim Depth PA Tool 50R4 UP1 Bd LM1 LM1 . 18P O X

Same. GP2R 15pin, LM1 8pin Reduce power on time. PDP only code. Support DFT JIG. Develop new WAFER and CABLE. (12 years) Stand by 0.3W Stand by 3.5V . Not use 12V.

IR Wafer

15P

8P

LM1 not support 3D.

USB Memory

O DDR3

O DDR3

SIDE USB. DDR3 1Gbit . 2ea LGE Internal Use Only

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

3. GP2R Power measure Summary


Power Line +5V_ST +5V_ST_EN +3.3V_AVDD +2.5V_AVDD +1.5V_DDR_IN +1.26V_VDDC +3.3V_ST +17V +5V_TU +5V +3.3V_TU +1.2V_TU Voltage Spec [V] 4.845~5.355 4.845~5.355 3.14~3.6 2.38~2.62 1.425~1.575 1.2~1.32 3.234~3.366 16.15~17.85 4.75~5.25 4.845~5.355 3.15~3.46 1.20~1.32 Voltage [V] 5.01 5.00 3.31 2.53 1.57 1.27 3.30 17.03 4.99 5.03 3.26 1.27 None None None 0.5 1.5V +/-5% 0.5 Ripple spec [Vpp] Ripple [mV] 86 17 15 20 20 30 19 1.09A 20 57 26 21 Current [A] 0.009 0.710 0.285 0.200 0.310 0.770 0.024 1.420 0.170 2.600 0.320 0.300 Remark

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

3-1. GP2R Power Block Diagram


5Vst
L603 MAX 3A +5V_ST
C619 100u 16V C627 0.1u 16V C219 0.1u 16V

IC205 AT24C02BN RGB EDID

C654 22u 16V

C655 0.01u 25V

+5V_ST_EN Q600 C657 RTR030P02 C656


100u 16V 0.1u 16V

C600 0.1u 16V

IC600 AZ1085S 3.3V

C607 22u 6.3V

C608 0.1u 16V

L602 2A

+3.3V_AVDD
C615 0.1u 16V

2A/3ea
10u 2ea 0.1u 13ea

S7_3.3V_AVDD

NAND Flash/HDCP/EEPROM

IC604 TJ3964 C616


22u 6.3V

C623 0.1u 16V

+2.5V_AVDD 2A 2A/2ea
10u 1ea 0.1u 4ea

2.5V_AVDD

C609 10u 16V

C611 0.1u 16V

IC602 TPA54319

+1.5V_DDR_IN
C637 10u 10V C647 10u 10V C650 0.1u 16V 10u 2ea 0.1u 32ea

DDR

2A/2ea

10u 4ea

0.1u 10ea

S7 AVDD_DDR

C610 10u 16V

C612 0.1u 16V

IC603 TPA54319

+1.26V_VDDC
C651 10u 10V C652 10u 10V C653 0.1u 16V

2A/2ea

10u 2ea 10u 1ea

0.1u 2ea 0.1u 8ea

DVDD VDDC IC203 MAX3232CDR

C601 0.1u 16V

IC601 AP2121N 300mA

+3.3V_ST
C605 100u 16V C606 0.1u 16V C552 0.1u 16V

S7_MPLL IC503(S-FLASH) MX25L8005M2I-15G SUB ASSY

+17V

17V

C634 4.7u 50V

C635 4.7u 50V

C636 0.01u 50V

IC605 TPA54319

+5V_TU
C641 10u 16V C642 10u 16V

L610 2A

C304 22u 10V

C307 0.1u 16V

5V_TU

C341 68u 35V

C344 68u 35V

C340 0.1u 50V

IC303 Audio AMP STA338BWG13TR

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

3-2. GP2R Power Block Diagram


+5V
L604 3A L605 3A +5V
C621 100u 16V C624 100u 16V C628 0.1u 16V C631 22u 16V

L101 2A

C103 22u 10V

C104 0.1u 16V

+5V_CI_ON IC205 AT24C02 EDID USB

IC206 AP2191

C223 100u 16V

C222 0.1u 16V C235 0.1u 16V

SPDIF

L708 2A

C725 10u 16V

C728 0.1u 16V

IC704 TPS54319

C746 10u 10V

C747 10u 10V

C748 0.1u 16V

L709 2A

L710 2A
0.1u 16V 13ea

1.0V_LTX 1.0V

C750 0.1u 16V

IC706 AZ1085S

C753 22u 16V

C754 0.1u 16V

L708 2A

+3.3V_3D

C751 0.1u 16V

IC707 AZ1117ST C752 L705 2A L706 2A L707 2A


22u 16V

C755 0.1u 16V C789 10u 16V C753 10u 16V C805 100p 50V C754 100p 50V

R834 01/10W

C735 0.1u 16V 0.1u 16V 33ea

IC702 MX25L4005

1.8V

0.1u 16V 0.1u 16V 0.1u 16V

7ea

3.3V_LTX 3.3V_VDD 3.3V_PLL

7ea

3ea

C658 0.1u 16V

IC606 AZ1085S

C659 22u 6.3V

C660 0.1u 16V

L601 2A

C661 0.1u 16V

C126 0.1u 16V

L100 2A

C128 0.1u 16V C120 0.1u 16V C332 0.1u 50V

+3.3V_CI

IC101 74LCX244

IC303 Audio AMP

+3.3V_TU L300 2A
C302 0.1u 16V C309 22u 10V

+3.3V_TU

C313 0.1u 16V

IC301 AZ1117H

+1.2V_TU
C325 22u 10V C322 0.1u 16V C300 0.1u 16V

+1.2V_TU

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

3-3. LDO/DC-DC Start up


IC600 (+3.3V_AVDD/AZ1085S) IC602 (+1.5V_DDR_IN/TPS54319)

Vin Vout Vin Ve n Vo Io

IC604(+2.5V_AVDD/TJ3964S)

IC603 (+1.26V_VDDC/TPS54319)

Vin Vout Ve n Vo Io

Vin

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

3-4. LDO/DC-DC Start up


IC606 (+3.3V/AZ1085S)

Vout

Vin

IC605 (+5V_TU/TPS54231)

Vin Ve n Vo Io

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

3-5. GP2R I2C MAP


DDC_SCL/SDA_1~3
1 (R208,209) 2 (R233,234) 10K 3 (R256,257) DDCR_CK/GPIO72 DDCR_DA/GPIO71

+5V_HD MI

(N22)<I2C-SCL> (M22)<I2C-SDA>

2.2K (R480,R482) EEPROM EEPROM 0xA0 0xA0 Ch2 Ch2 HDCP HDCP EEPROM EEPROM 0xA8 0xA8 Ch2 Ch2

<EEPROM-SCL> +3.3 <EEPROM-SDA> V

HDMI1,2,3 HDMI1,2,3 0xA0 0xA0 Ch10,12,11 Ch10,12,11 TGPIO2/I2C_CLK TGPIO3/I2C_SDA

(R3) <TU_SCL> (T3) <TU_SDA>

4.7K (R319,R326)
TUNER TUNER TDTJ-S001D TDTJ-S001D 0x10/C2 0x10/C2 Ch6 Ch6

<SCL1> +3.3V_T <SDA1>

SATURN7R SATURN7R TGPIO0/UPGAIN TGPIO1/DNGAIN

+3.3V_S T

SUB_SCL SUB_SDA

I2S_IN_WS/GPIO174 (F15) I2S_IN_BCK/GPIO175 (F14)

(U1) (U2)

4.7K (R635,R633)
G_EYE G_EYE 0x20 0x20 Ch7 Ch7 I2S_IN_SD/GPIO176 SPDIF_IN/GPIO177

AMP AMP STA338BWG13TR STA338BWG13TR 0x38 0x38 Ch5 Ch5

2K (R360,R359)

<AMP_SCL> <AMP_SDA>

+3.3 V

TOUCH TOUCH 0x52 0x52 Ch7 Ch7

+3.3 (F13)<P_SCL> <MODULE_SCL/3DF_SCL> 4.7K (R780,R781) <MODULE_SDA/3DF_SDA> (G14)<P_SDA> 3.3K (R1412,R1411) V_A VDD LG8300 MODULE LG8300 MODULE
0x74 0x74 Ch4 Ch4 0x1C 0x1C Ch4 Ch4

DDCA_CK/UART0_RX DDCA_DA/UART0_TX

(B5) <RGB_DDC_SCL> (A5) <RGB_DDC_SDA>

10K (R237,R247)
EEPROM EEPROM RGB RGB 0xA0 0xA0 Ch8 Ch8 ISP ISP

+5.0 <DDC_SCL/UART_RX> <DDC_SDA/UART_TX> V_ST

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4. LM1 Power Block optimization.


1. GP2R vs LM1 Power Block.

Amp 17V

17V

Amp

1.8V Tuner LDO (1A) 1.25V _TU LDO (1A) 2.5V LDO (1A)

5V Tuner TPS54231 2A
AP2191 USB 3.3V Multi LDO (3A) 1.25V Tuner LDO 1.8V 3D DDR LDO 3.3V AVDD LDO (3A) 2.5V LDO

3.3V Multi TPS54327(3A)

5.1V

5.1V

3.3V 3D LDO (3A)

AP2191 USB

1V 3D core AOZ1073 3A

FET SW
St 5V 3.3V Standby LDO(AP2121)

1.5V DDR AOZ1073 3A 1.26V Core AOZ1073 3A


3.5V St.

1.24V core 1.5V DDR TPS65253(3A)

3.3V ST AP2121

DC/DC : 4 LDO : 7

DC/DC : 2

GP2R Power Block

LDO : 4

LM1 Power Block

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4-1. P_17V
Spec) 850mV 16mVrms 17V to 3.3V 283mVpp
C620 10uF 25V 3216 C621 0.1uF 50V 2012 TPS54327 (3A, $0.14) L605 2.2uH 3.5A 4.9x4.9 C629/50 10uF 16V 6.3V 3216 1608 0.00586 change

Spec) 165mV 8.66mVrms 37.5mVpp


C630 0.1uF 16V 1005

+3.3V L101 120 Ohm 2A 1608 C137 0.1uF 16V 1005

Spec) 165mV 4.7mVrms 46.6mVpp

+3.3V_CI

Buffer for CI_ADDR [0:7]

OP-Amp for SC

1 7 V

C667 0.1uF 50V 1608

C668 68uF 35V 8PI/6.3H

Audio AMP

L604 120 Ohm 2A 1608 C627 10uF 6.3V 1608

Spec) 165mV 13.5mVrms 158mVpp

+3.3V_TU
3.3V to 1.8V AP1117E18G (850mW)

Spec) 90mV 4.6mVrms 41.6mVpp


C631 10uF 6.3V 1608 C618 0.1uF 16V 1005

C693 10uF 25V 3225

C694 0.01uF 50V 1005

17V to 12V TPS54231D (2A)

Spec) 165mV 23.4mVrms 166.6mVpp

Tuner

C614 0.1uF C643 0.1uF C711 10uF 16V 3216 C712 0.1uF 50V 1608 C638 C646 0.1uF 50V 1608 16V

C615 10uF 16V 6.3V 3216 1608 change

LNB

50V 1608

Audio AMP

Spec) 165mV 8.5mVrms 186.6mVpp

1005

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4-2. P_17V
+3.3V
3.3V to 2.5V TJ3940S-2.5V (714mW)

+2.5V
x3 120 Ohm C612 10uF 6.3V 1608 2A 1608 C605 10uF 6.3V 1608

* Y17

Spec) 165mV 7.8mVrms 47.5mVpp


C1417 10uF 10V 6.3V 2012 1608 change x6 0.1uF 16V 1005

L613

LM1

120 Ohm 2A 1608 C682 0.1uF 16V 1005 C671 10uF 10V 6.3V 2012 1608 change

Tuner

DVB_T2

1 7 V

* W18/9

L408/9 120 Ohm 2A 1608 x5 0.1uF 16V 1005

Spec) 165mV 9.7mVrms 67.5mVpp


X4 10uF 10V 6.3V 2012 1608 change

x2 0.1uF 16V 1005

C554 10uF 10V 6.3V 2012 1608 change

Nand Flash
+1.25V_TU
3.3V to 1.25V AP1117EG-13 (???mW)

C625 10uF 6.3V 1608

LM1 HDCP

x3 0.1uF 16V 1005

C427 10uF 10V 6.3V 2012 1608 0.00636 change


* L7

Spec) 165mV 8.5mVrms 45mVpp

C552 0.1uF 16V 1005

NVR
C684 0.1uF 16V 1005 C685 10uF 6.3V 1608

Tuner

NOT_HNIM

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4-3. P_5V

L600 120 Ohm 5A 2012 C608 10uF 10V 16V 2012 3216 0.0005 change

Spec) 250mV 7mVrms 70mVpp


C610 0.1uF 16V 1005

+5V

USB OCD

C219 0.1uF 16V 1005

SPDIF

5 V

+5V_CI_ON
L100 120 Ohm 2A 1608 C104 0.1uF 16V 1005 C100 22uF 10V 16V 3216 3225 0.017 change

MOFET Switch

Spec) 250mV 31mVrms 135.4mVpp


C101 0.1uF 16V 1005

PCMCI

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4-4. P_5V
+5V
L606 120 Ohm 5A 2012 C653/4 10uF 25V 3225

+1.24V_VDDC
L405

* M14

???mVrms
C683/57 22uF 16V 3225

120 Ohm 2A 1608 x2 0.1uF 16V 1005

Spec) 55mV 9.4mVrms 48.3mVpp C1413 ???mVrms


10uF 10V 6.3V 2012 1608 change x3 10uF 10V 6.3V 2012 1608 change L412 120 Ohm
* R15

LM1
Spec) 55mV 17.7mVrms 70mVpp

5V to 1.1V TPS65253RH D (adjustable) $0.25

x3 0.1uF 16V 1005

5 V
C651/56 22uF 16V 3225

+1.5V_DDR_IN

* M17

Spec) 55mV 15.9mVrms 90mVpp


x4 10uF 10V 6.3V 2012 1608 change x4 0.1uF 16V 1005 C468 1uF 10V 1005

C467 1000pF 50V 1005

2A 1608

LM1 MIU0/1

VCC_1.5V_DDR
L500 500 Ohm 3A ??? C544 10uF 10V 6.3V 2012 1608 change C545 0.1uF 16V 1005

* IC501 / G7

Spec) 55mV 19.69mVrms 120.8mVpp


x2 1000pF 50V 1005 x2 0.1uF 16V 1005

DDR1/2

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4-5. STBY
Spec) 250mV 23mVrms 150mVpp

+3.3V_ST
RS232C

C600 10uF 10V 16V 2012 3216 0.0005 change

C601 0.1uF 16V 1005

5V to 3.3V AP2121N-3.3 (0.3A)

C604 1uF 6.3V 1005

C228 0.1uF 16V 1005

L406 120 Ohm 2A 1608 C469 0.1uF 16V 1005

LM1

S T B Y

C556 0.1uF 16V 1005

Serial Flash

C547 0.1uF 16V 1005

SUB Assy

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

4-6. GP4 LM1 I2C MAP


+3.3V_TU R3082.2K R309 2.2K

EAX64337201_0

I2C_SCKM1/GPIO75 I2C_SDAM1/GPIO76
IC400

AE6 AD6

TU_SCL TU_SDA

TU300 TDSS-G201D
+3.3V

GPIO49 GPIO50

AB5 AB3

AMP_SCL AMP_SDA

R624 2K

R623 2K

IC300 STA368BWG

+3.3V_AVDD

I2S_IN_WS/GPIO149 SPDIF_IN/GPIO152

D9 D7

P_SCL P_SDA

R468 3.3K

R466 3.3K

SCL_3.3V_MOD P500 SDA_3.3V_MOD LVDS

+3.3V_ST

I2S_IN_SD/GPIO151 I2S_IN_BCK/GPIO150

D8 C8

SUB_SCL SUB_SDA

R539 4.7K

R538 4.7K

P501 KEY/IR PIN8


+3.3V_AVDD

I2C_SCKM2/DDCR_CK/GPIO72 I2C_SDAM2/DDCR_DA/GPIO71

P23 P24

I2C_SCL I2C_SDA

R469 2.2K

R468 2.2K

IC503 EEPROM IC502 HDCP (OTP)


LGE Internal Use Only

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

5. GP4 LM1 SOC Power Sequence Procedure


Hot Point

288ms / [Spec] before all pwr input raise SOC_RESET +3.3V_AVDD Multi_PWR 0ms +1.10V_VDDC +1.5V_DDR_IN

SOC_RESET
Threshold

+3.3V_AVDD

+1.10V_VDDC

+1.5V_DDR_IN

SOC_RESET timing and Power sequence are ok.

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

5. GP4 LM1 SOC Power Sequence Procedure


Solution

Value of Capacitor and resister. Cap 22uF.


0CK226DC67A 22uF 6.3V $0.0117

Resister 100.

+3.3V_AVDD

1
SOC_RESET

Threshold

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

6. Memory margin test. (DDR)


STEP1. Setting like below. (Red box) STEP2. Call direct MIU Auto BIST function from Menu.

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

6. Memory margin test. (DDR)


STEP3. Setting like below and push Start DQS. (Red box) STEP4. below picture is test result. Red box is timing margin.

Normal operating board has timing margin 7~9. If timing margin under 7 ,its some problem DDR or Main MIU.

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7. Pen touch overview. (Installation_Pentouch Program.)

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7. Pen touch overview. (Installation_Pentouch Program.)

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7-1. Pen touch overview. (Check the installation status.)


1

Currently installed programs Check the LG Pentouch Multi-touch Driver or Pentouch TV

Check USB Dongle Driver in Device Manager -LG Pentouch Multi-touch Driver(MultiTouch) -LG Pentouch Multi-touch Driver(BUS) -LG Pentouch Multi-touch Driver(Dongle) the Dongle Driver should be displayed when connected USB Dongle

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7-2. Pen touch overview. (Pairing between Touch Pen and Dongle)

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7-3. Pen touch overview. (Pairing between Touch Pen and Dongle)

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7-4. Pen touch overview. (Using the Pentouch Function)


Image shown may differ from your monitor. You need the following items to use the Pentouch functions: 1 Enter the Pentouch mode on your monitor. - Press TOUCH button on the remote control or MENU to access the main menus. Then choose Pentouch function. 2 Select the correct computer input connection to enter the Pentouch mode.

3 Use the touch pen or the mouse to start the Pentouch program. Pressing the /Home button on the touch pen works in the same way as right-clicking the mouse.

Viewing the Screen Settings


I mage shown may differ from your monitor. If you press the OK button on the remote control, the screen shown below appears to indicate that the screen settings have been updated successfully.

The text "Pentouch" should be displayed to indicate that the Pentouch mode is activated. If not, restart the Pentouch mode. "1365x768 " should be displayed to indicate that the resolution has been set successfully. If not, set the monitor resolution again.(See p.38)

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only

7-5. Pen touch overview. (PDP Pen Touch Concept)

Principle 1. The Pen using PDP Cells light energy Step 1. The pen detect the PDP Cells light Step 2. The pen convert detected light to voltage Step 3. The pen calculate X,Y position Step 4. The pen transfer the X,Y data through RF

Principle 2. The position data processed Pentouch TV Application looks like PC mouse. Step 1. USB Dongle receive the position data. Step 2. USB Dongle Driver parsing the positon Step 3. Pentouch TV application drawing and click function. Step 4. The result was displayed PDP TV through HDMI or RGB cable.

Pen
The photo sensor in the pen detect the light

RF Wireless communication (2.4GHz)

USB Dongle
It can use Multi-Touch function by support 2 pens.

Plasma Display

Pentouch TV Application - It was developed by LG. - It can be using internet for web surfing , Flash Game etc.

The HDMI or RGB signal is PCs output that configuration set by clone mode.

Copyright 2012 LG Electronics Inc. All rights reserved. Only for training and service purposes

LGE Internal Use Only