8-bit Shifter

entity shifter is
port (si,clk,clr:in bit;s1,s2,s3,s4,s5,s6,s7,s8:inout bit);
end shifter;
architecture arc of shifter is
component dff is
port (d,clk,clr:in bit;q :out bit);
end component;
begin
d1: dff port map(si,clk,clr,s1);
d2:dff port map(s1,clk,clr,s2);
d3:dff port map(s2,clk,clr,s3);
d4:dff port map(s3,clk,clr,s4);
d5:dff port map(s4,clk,clr,s5);
d6:dff port map(s5,clk,clr,s6);
d7:dff port map(s6,clk,clr,s7);
d8:dff port map(s7,clk,clr,s8);
end architecture;
TEST BENCH SHIFTER
entity tb is
end tb;
architecture test of tb is
component shifter is
port (si,clk,clr:in bit;s1,s2,s3,s4,s5,s6,s7,s8:inout bit);
end component;
signal si1,clk1,clr1:bit;
signal s:bit_vector(7 downto 0);
begin shift1: shifter port
map(si1,clk1,clr1,s(0),s(1),s(2),s(3),s(4),s(5),s(6),s(7));
process begin si1<=not si1 after 30 ns;
clk1<=not clk1;
wait for 10 ns;
end process;
end architecture;

ALU

entity alu is
port (L,M:in bit_vector(3 downto 0);
CIN,SEL1,SEL2,SEL3: in bit;
FOUT: out bit_vector(3 downto 0));
end entity;
architecture alu_arch of alu is
component arthm_comp is
port (x,y: in bit_vector(3 downto 0);
cin,op1,op2: in bit;
f1: out bit_vector(3 downto 0));
end component;
component logical is
port(x: in bit_vector(3 downto 0);
y: in bit_vector(3 downto 0);
op1,op2: in bit;
f2: out bit_vector(3 downto 0));
end component;
component mux2x1 is port (i1,i2: in bit;s1: in bit;e: out bit);
end component;
signal val1,val2: bit_vector(3 downto 0);
begin AC: arthm_comp port map(L,M,CIN,SEL1,SEL2,val1);
LC: logical port map(L,M,SEL1,SEL2,val2);
MUX1: mux2x1 port map(val1(0),val2(0),SEL3,FOUT(0)); MUX2:
mux2x1 port map(val1(1),val2(1),SEL3,FOUT(1)); MUX3: mux2x1 port
map(val1(2),val2(2),SEL3,FOUT(2)); MUX4: mux2x1 port
map(val1(3),val2(3),SEL3,FOUT(3));
end alu_arch;


IMPLEMENTATION OF SHIFT OPERATION

LEFT SHIFTER
entity leftshifter is
port(a:in bit_vector;al:out bit_vector);
end leftshifter;
architecture leftsh_arch of leftshifter is begin
al(1)<=a(0);
al(2)<=a(1);
al(3)<=a(2);
al(0)<='0';
end leftsh_arch;
LOGICAL
entity logical is
port(a,b,s1,s0:in bit;z:out bit);
end logical;
architecture logical_arch of logical is
component mux4x1
port(a,b,c,d,s1,s0:in bit;z:out bit);
end component;
signal y0,y1,y2,y3:bit;
begin y0<=a and b;
y1<=a or b;
y2<=not a;
y3<=a nand b;
inst:mux4x1 port map(y0,y1,y2,y3,s1,s0,z);
end logical_arch;

RIGHT SHIFTER
entity rightshifter is
port(a:in bit_vector;ar:out bit_vector);
end rightshifter;
architecture rightsh_arch of rightshifter is begin
ar(0)<=a(1);
ar(1)<=a(2);
ar(2)<=a(3);
ar(3)<='0';
end rightsh_arch;

TEST BENCH

entity tb is
end tb;
architecture tb_arch of tb is
component alu
port(s,a,b:in bit_vector;f:out bit_vector);
end component;
signal s,a,b,f:bit_vector(3 downto 0);
begin
inst:alu port map(s,a,b,f);
process
begin s<="0011";
wait for 20 ns;
a<="1100";
wait for 20 ns;
b<="0011";
wait for 20 ns;
s<="1100";
wait for 20 ns;
a<="1001";
wait for 20 ns;
b<="0000";
wait for 20 ns;
end process;
end tb_arch;