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#xos3D36 (111 config 0x87560300 / subid 0x00 / feat 0x00000003 / bdl 0x00140400)
[serial#b84e028151c00a170d9e747427c7f8a8]
[oemid#3b39cffb34b3d6cb81cb2395cad8e4a14bb64bc2381f2968353d590e0d774fd9]
#step22
ruamm0 [0x98000000,0xbf2f0000[ (~657391616 bytes)
ruamm1 [0xc0000000,0xffd60000[ (~1070989312 bytes)
[0xbf0c0000,xos_public_ga=0xbf0c0000[ and [0xbf0e0000,0xbf100000[ are lost for a
lignment)
channel_index_ga=0x#ei
xos3 xload3 rc=6
[0xbec00000,ios_ga=0xbec00000[ and [0xbf000000,0xbf0afcbc[ are lost for alignmen
t)
step33
f_pll0=0x3b8b87c0
current_pll0=0x01000024
cpuclk_div_inclk_freq=999000000 HZ
pll_sysclk(from pll1)=0x01000026
freq_to_mux=0x3ec38140
cpuclk_div_bypass_freq=526500000 HZ
Gonna ramp "down", div.value=0x0060010e
Wrote the cpuclk_div_ctrl register...
Ramped DOWN. cpuclk_div=0x0060010e
reaching for bypass freq: cpuclk_div=0x00800200
Setting pll0=0x01000024
Slow ramped to cpuclk_div=0x00600100
Post-ramp: Current CPU freq=999100000 HZ, and SysClk @ 351000000 HZ
thimble 0x14 @(cpu=@999MHz/dsp=351MHz/sys=351MHz)
on 8756 rev ES1 (subid 0x00)
L2 cache settings tag 0x00000110 data 0x00000120
xos version = 0x36
xos serial = b84e028151c00a170d9e747427c7f8a8
Using zxenv ga=0xffd5c000 (va=0xa005c000)
Chip identified as SMP8756A03 (00) rev 1 dev (oemid: sigma)
Board ID.: 1162-E1 eMMC
Setting up H/W from XENV block at 0xa005c000.
Setting <SYSCLK avclk_mux> to 0x17400000.
Setting <SYSCLK hostclk_mux> to 0x00000131.
Setting <IRQ rise edge trigger lo> to 0xff28ca06.
Setting <IRQ fall edge trigger lo> to 0x0000c000.
Setting <IRQ rise edge trigger hi> to 0x8c10001f.
Setting <IRQ fall edge trigger hi> to 0x00000000.
Setting <IRQ GPIO map> to 0x000a0800.
Setting <PB default timing> to 0x03080202.
Setting <PB timing0> to 0x03080202.
Setting <PB Use timing0> to 0x000003f3.
Setting <PB timing1> to 0x04040000.
Setting <PB Use timing1> to 0x000003f4.
Setting <PB CS Config> to 0x04370007.
Setting <PB CS Ctrl> to 0x00000022.
Enabled Devices: 0x002303f8
Ethernet IR FIP I2CM I2CS SDIO SDIO1 USB SATA SCARD
Smartcard pin assignments:
OFF pin = 0
5V pin = 2
CMD pin = 1
PLL#1 postdivider = 0x0000060f
cd#0 disabled
cd#1 disabled
cd#2 want 96000000Hz: setting of 0x0000000043800000-2^28
csd_regs[1] = 0xffffffff
csd_regs[2] = 0x320f5913
csd_regs[3] = 0x00d04f01
Attempt to switch to 8 bit mode ...successful.
MBR sig check failed.
Failed to init!
Boot failed (no bootable image found) ..